1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Altera <www.altera.com>
6 #include <dt-bindings/reset/altr,rst-mgr.h>
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
36 next-level-cache = <&L2>;
41 compatible = "arm,cortex-a9-pmu";
42 interrupt-parent = <&intc>;
43 interrupts = <0 176 4>, <0 177 4>;
44 interrupt-affinity = <&cpu0>, <&cpu1>;
45 reg = <0xff111000 0x1000>,
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
53 reg = <0xfffed000 0x1000>,
60 compatible = "simple-bus";
62 interrupt-parent = <&intc>;
66 compatible = "simple-bus";
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
85 clocks = <&l4_main_clk>;
86 clock-names = "apb_pclk";
91 compatible = "fpga-region";
92 fpga-mgr = <&fpgamgr0>;
94 #address-cells = <0x1>;
99 compatible = "bosch,d_can";
100 reg = <0xffc00000 0x1000>;
101 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
102 clocks = <&can0_clk>;
107 compatible = "bosch,d_can";
108 reg = <0xffc01000 0x1000>;
109 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
110 clocks = <&can1_clk>;
115 compatible = "altr,clk-mgr";
116 reg = <0xffd04000 0x1000>;
119 #address-cells = <1>;
124 compatible = "fixed-clock";
129 compatible = "fixed-clock";
132 f2s_periph_ref_clk: f2s_periph_ref_clk {
134 compatible = "fixed-clock";
137 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
139 compatible = "fixed-clock";
142 main_pll: main_pll@40 {
143 #address-cells = <1>;
146 compatible = "altr,socfpga-pll-clock";
152 compatible = "altr,socfpga-perip-clk";
153 clocks = <&main_pll>;
154 div-reg = <0xe0 0 9>;
158 mainclk: mainclk@4c {
160 compatible = "altr,socfpga-perip-clk";
161 clocks = <&main_pll>;
162 div-reg = <0xe4 0 9>;
166 dbg_base_clk: dbg_base_clk@50 {
168 compatible = "altr,socfpga-perip-clk";
169 clocks = <&main_pll>, <&osc1>;
170 div-reg = <0xe8 0 9>;
174 main_qspi_clk: main_qspi_clk@54 {
176 compatible = "altr,socfpga-perip-clk";
177 clocks = <&main_pll>;
181 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
183 compatible = "altr,socfpga-perip-clk";
184 clocks = <&main_pll>;
188 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
190 compatible = "altr,socfpga-perip-clk";
191 clocks = <&main_pll>;
196 periph_pll: periph_pll@80 {
197 #address-cells = <1>;
200 compatible = "altr,socfpga-pll-clock";
201 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
204 emac0_clk: emac0_clk@88 {
206 compatible = "altr,socfpga-perip-clk";
207 clocks = <&periph_pll>;
211 emac1_clk: emac1_clk@8c {
213 compatible = "altr,socfpga-perip-clk";
214 clocks = <&periph_pll>;
218 per_qspi_clk: per_qsi_clk@90 {
220 compatible = "altr,socfpga-perip-clk";
221 clocks = <&periph_pll>;
225 per_nand_mmc_clk: per_nand_mmc_clk@94 {
227 compatible = "altr,socfpga-perip-clk";
228 clocks = <&periph_pll>;
232 per_base_clk: per_base_clk@98 {
234 compatible = "altr,socfpga-perip-clk";
235 clocks = <&periph_pll>;
239 h2f_usr1_clk: h2f_usr1_clk@9c {
241 compatible = "altr,socfpga-perip-clk";
242 clocks = <&periph_pll>;
247 sdram_pll: sdram_pll@c0 {
248 #address-cells = <1>;
251 compatible = "altr,socfpga-pll-clock";
252 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
255 ddr_dqs_clk: ddr_dqs_clk@c8 {
257 compatible = "altr,socfpga-perip-clk";
258 clocks = <&sdram_pll>;
262 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
264 compatible = "altr,socfpga-perip-clk";
265 clocks = <&sdram_pll>;
269 ddr_dq_clk: ddr_dq_clk@d0 {
271 compatible = "altr,socfpga-perip-clk";
272 clocks = <&sdram_pll>;
276 h2f_usr2_clk: h2f_usr2_clk@d4 {
278 compatible = "altr,socfpga-perip-clk";
279 clocks = <&sdram_pll>;
284 mpu_periph_clk: mpu_periph_clk {
286 compatible = "altr,socfpga-perip-clk";
291 mpu_l2_ram_clk: mpu_l2_ram_clk {
293 compatible = "altr,socfpga-perip-clk";
298 l4_main_clk: l4_main_clk {
300 compatible = "altr,socfpga-gate-clk";
305 l3_main_clk: l3_main_clk {
307 compatible = "altr,socfpga-perip-clk";
312 l3_mp_clk: l3_mp_clk {
314 compatible = "altr,socfpga-gate-clk";
316 div-reg = <0x64 0 2>;
320 l3_sp_clk: l3_sp_clk {
322 compatible = "altr,socfpga-gate-clk";
323 clocks = <&l3_mp_clk>;
324 div-reg = <0x64 2 2>;
327 l4_mp_clk: l4_mp_clk {
329 compatible = "altr,socfpga-gate-clk";
330 clocks = <&mainclk>, <&per_base_clk>;
331 div-reg = <0x64 4 3>;
335 l4_sp_clk: l4_sp_clk {
337 compatible = "altr,socfpga-gate-clk";
338 clocks = <&mainclk>, <&per_base_clk>;
339 div-reg = <0x64 7 3>;
343 dbg_at_clk: dbg_at_clk {
345 compatible = "altr,socfpga-gate-clk";
346 clocks = <&dbg_base_clk>;
347 div-reg = <0x68 0 2>;
353 compatible = "altr,socfpga-gate-clk";
354 clocks = <&dbg_at_clk>;
355 div-reg = <0x68 2 2>;
359 dbg_trace_clk: dbg_trace_clk {
361 compatible = "altr,socfpga-gate-clk";
362 clocks = <&dbg_base_clk>;
363 div-reg = <0x6C 0 3>;
367 dbg_timer_clk: dbg_timer_clk {
369 compatible = "altr,socfpga-gate-clk";
370 clocks = <&dbg_base_clk>;
376 compatible = "altr,socfpga-gate-clk";
377 clocks = <&cfg_h2f_usr0_clk>;
381 h2f_user0_clk: h2f_user0_clk {
383 compatible = "altr,socfpga-gate-clk";
384 clocks = <&cfg_h2f_usr0_clk>;
388 emac_0_clk: emac_0_clk {
390 compatible = "altr,socfpga-gate-clk";
391 clocks = <&emac0_clk>;
395 emac_1_clk: emac_1_clk {
397 compatible = "altr,socfpga-gate-clk";
398 clocks = <&emac1_clk>;
402 usb_mp_clk: usb_mp_clk {
404 compatible = "altr,socfpga-gate-clk";
405 clocks = <&per_base_clk>;
407 div-reg = <0xa4 0 3>;
410 spi_m_clk: spi_m_clk {
412 compatible = "altr,socfpga-gate-clk";
413 clocks = <&per_base_clk>;
415 div-reg = <0xa4 3 3>;
420 compatible = "altr,socfpga-gate-clk";
421 clocks = <&per_base_clk>;
423 div-reg = <0xa4 6 3>;
428 compatible = "altr,socfpga-gate-clk";
429 clocks = <&per_base_clk>;
431 div-reg = <0xa4 9 3>;
434 gpio_db_clk: gpio_db_clk {
436 compatible = "altr,socfpga-gate-clk";
437 clocks = <&per_base_clk>;
439 div-reg = <0xa8 0 24>;
442 h2f_user1_clk: h2f_user1_clk {
444 compatible = "altr,socfpga-gate-clk";
445 clocks = <&h2f_usr1_clk>;
449 sdmmc_clk: sdmmc_clk {
451 compatible = "altr,socfpga-gate-clk";
452 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
457 sdmmc_clk_divided: sdmmc_clk_divided {
459 compatible = "altr,socfpga-gate-clk";
460 clocks = <&sdmmc_clk>;
465 nand_x_clk: nand_x_clk {
467 compatible = "altr,socfpga-gate-clk";
468 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
472 nand_ecc_clk: nand_ecc_clk {
474 compatible = "altr,socfpga-gate-clk";
475 clocks = <&nand_x_clk>;
481 compatible = "altr,socfpga-gate-clk";
482 clocks = <&nand_x_clk>;
483 clk-gate = <0xa0 10>;
489 compatible = "altr,socfpga-gate-clk";
490 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
491 clk-gate = <0xa0 11>;
494 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
496 compatible = "altr,socfpga-gate-clk";
497 clocks = <&ddr_dqs_clk>;
501 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
503 compatible = "altr,socfpga-gate-clk";
504 clocks = <&ddr_2x_dqs_clk>;
508 ddr_dq_clk_gate: ddr_dq_clk_gate {
510 compatible = "altr,socfpga-gate-clk";
511 clocks = <&ddr_dq_clk>;
515 h2f_user2_clk: h2f_user2_clk {
517 compatible = "altr,socfpga-gate-clk";
518 clocks = <&h2f_usr2_clk>;
525 fpga_bridge0: fpga_bridge@ff400000 {
526 compatible = "altr,socfpga-lwhps2fpga-bridge";
527 reg = <0xff400000 0x100000>;
528 resets = <&rst LWHPS2FPGA_RESET>;
529 clocks = <&l4_main_clk>;
532 fpga_bridge1: fpga_bridge@ff500000 {
533 compatible = "altr,socfpga-hps2fpga-bridge";
534 reg = <0xff500000 0x10000>;
535 resets = <&rst HPS2FPGA_RESET>;
536 clocks = <&l4_main_clk>;
539 fpgamgr0: fpgamgr@ff706000 {
540 compatible = "altr,socfpga-fpga-mgr";
541 reg = <0xff706000 0x1000
543 interrupts = <0 175 4>;
546 gmac0: ethernet@ff700000 {
547 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
548 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
549 reg = <0xff700000 0x2000>;
550 interrupts = <0 115 4>;
551 interrupt-names = "macirq";
552 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
553 clocks = <&emac_0_clk>;
554 clock-names = "stmmaceth";
555 resets = <&rst EMAC0_RESET>;
556 reset-names = "stmmaceth";
557 snps,multicast-filter-bins = <256>;
558 snps,perfect-filter-entries = <128>;
559 tx-fifo-depth = <4096>;
560 rx-fifo-depth = <4096>;
564 gmac1: ethernet@ff702000 {
565 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
566 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
567 reg = <0xff702000 0x2000>;
568 interrupts = <0 120 4>;
569 interrupt-names = "macirq";
570 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
571 clocks = <&emac_1_clk>;
572 clock-names = "stmmaceth";
573 resets = <&rst EMAC1_RESET>;
574 reset-names = "stmmaceth";
575 snps,multicast-filter-bins = <256>;
576 snps,perfect-filter-entries = <128>;
577 tx-fifo-depth = <4096>;
578 rx-fifo-depth = <4096>;
582 gpio0: gpio@ff708000 {
583 #address-cells = <1>;
585 compatible = "snps,dw-apb-gpio";
586 reg = <0xff708000 0x1000>;
587 clocks = <&l4_mp_clk>;
590 porta: gpio-controller@0 {
591 compatible = "snps,dw-apb-gpio-port";
594 snps,nr-gpios = <29>;
596 interrupt-controller;
597 #interrupt-cells = <2>;
598 interrupts = <0 164 4>;
602 gpio1: gpio@ff709000 {
603 #address-cells = <1>;
605 compatible = "snps,dw-apb-gpio";
606 reg = <0xff709000 0x1000>;
607 clocks = <&l4_mp_clk>;
610 portb: gpio-controller@0 {
611 compatible = "snps,dw-apb-gpio-port";
614 snps,nr-gpios = <29>;
616 interrupt-controller;
617 #interrupt-cells = <2>;
618 interrupts = <0 165 4>;
622 gpio2: gpio@ff70a000 {
623 #address-cells = <1>;
625 compatible = "snps,dw-apb-gpio";
626 reg = <0xff70a000 0x1000>;
627 clocks = <&l4_mp_clk>;
630 portc: gpio-controller@0 {
631 compatible = "snps,dw-apb-gpio-port";
634 snps,nr-gpios = <27>;
636 interrupt-controller;
637 #interrupt-cells = <2>;
638 interrupts = <0 166 4>;
643 #address-cells = <1>;
645 compatible = "snps,designware-i2c";
646 reg = <0xffc04000 0x1000>;
647 resets = <&rst I2C0_RESET>;
648 clocks = <&l4_sp_clk>;
649 interrupts = <0 158 0x4>;
654 #address-cells = <1>;
656 compatible = "snps,designware-i2c";
657 reg = <0xffc05000 0x1000>;
658 resets = <&rst I2C1_RESET>;
659 clocks = <&l4_sp_clk>;
660 interrupts = <0 159 0x4>;
665 #address-cells = <1>;
667 compatible = "snps,designware-i2c";
668 reg = <0xffc06000 0x1000>;
669 resets = <&rst I2C2_RESET>;
670 clocks = <&l4_sp_clk>;
671 interrupts = <0 160 0x4>;
676 #address-cells = <1>;
678 compatible = "snps,designware-i2c";
679 reg = <0xffc07000 0x1000>;
680 resets = <&rst I2C3_RESET>;
681 clocks = <&l4_sp_clk>;
682 interrupts = <0 161 0x4>;
687 compatible = "altr,socfpga-ecc-manager";
688 #address-cells = <1>;
693 compatible = "altr,socfpga-l2-ecc";
694 reg = <0xffd08140 0x4>;
695 interrupts = <0 36 1>, <0 37 1>;
699 compatible = "altr,socfpga-ocram-ecc";
700 reg = <0xffd08144 0x4>;
702 interrupts = <0 178 1>, <0 179 1>;
706 L2: l2-cache@fffef000 {
707 compatible = "arm,pl310-cache";
708 reg = <0xfffef000 0x1000>;
709 interrupts = <0 38 0x04>;
712 arm,tag-latency = <1 1 1>;
713 arm,data-latency = <2 1 1>;
715 prefetch-instr = <1>;
717 arm,double-linefill = <1>;
718 arm,double-linefill-incr = <0>;
719 arm,double-linefill-wrap = <1>;
720 arm,prefetch-drop = <0>;
721 arm,prefetch-offset = <7>;
725 compatible = "altr,l3regs", "syscon";
726 reg = <0xff800000 0x1000>;
729 mmc: dwmmc0@ff704000 {
730 compatible = "altr,socfpga-dw-mshc";
731 reg = <0xff704000 0x1000>;
732 interrupts = <0 139 4>;
733 fifo-depth = <0x400>;
734 #address-cells = <1>;
736 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
737 clock-names = "biu", "ciu";
741 nand0: nand@ff900000 {
742 #address-cells = <0x1>;
744 compatible = "altr,socfpga-denali-nand";
745 reg = <0xff900000 0x100000>,
746 <0xffb80000 0x10000>;
747 reg-names = "nand_data", "denali_reg";
748 interrupts = <0x0 0x90 0x4>;
749 dma-mask = <0xffffffff>;
750 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
751 clock-names = "nand", "nand_x", "ecc";
755 ocram: sram@ffff0000 {
756 compatible = "mmio-sram";
757 reg = <0xffff0000 0x10000>;
761 compatible = "cdns,qspi-nor";
762 #address-cells = <1>;
764 reg = <0xff705000 0x1000>,
766 interrupts = <0 151 4>;
767 cdns,fifo-depth = <128>;
768 cdns,fifo-width = <4>;
769 cdns,trigger-address = <0x00000000>;
770 clocks = <&qspi_clk>;
774 rst: rstmgr@ffd05000 {
776 compatible = "altr,rst-mgr";
777 reg = <0xffd05000 0x1000>;
778 altr,modrst-offset = <0x10>;
781 scu: snoop-control-unit@fffec000 {
782 compatible = "arm,cortex-a9-scu";
783 reg = <0xfffec000 0x100>;
787 compatible = "altr,sdr-ctl", "syscon";
788 reg = <0xffc25000 0x1000>;
792 compatible = "altr,sdram-edac";
793 altr,sdr-syscon = <&sdr>;
794 interrupts = <0 39 4>;
798 compatible = "snps,dw-apb-ssi";
799 #address-cells = <1>;
801 reg = <0xfff00000 0x1000>;
802 interrupts = <0 154 4>;
804 clocks = <&spi_m_clk>;
809 compatible = "snps,dw-apb-ssi";
810 #address-cells = <1>;
812 reg = <0xfff01000 0x1000>;
813 interrupts = <0 155 4>;
815 clocks = <&spi_m_clk>;
819 sysmgr: sysmgr@ffd08000 {
820 compatible = "altr,sys-mgr", "syscon";
821 reg = <0xffd08000 0x4000>;
826 compatible = "arm,cortex-a9-twd-timer";
827 reg = <0xfffec600 0x100>;
828 interrupts = <1 13 0xf01>;
829 clocks = <&mpu_periph_clk>;
832 timer0: timer0@ffc08000 {
833 compatible = "snps,dw-apb-timer";
834 interrupts = <0 167 4>;
835 reg = <0xffc08000 0x1000>;
836 clocks = <&l4_sp_clk>;
837 clock-names = "timer";
838 resets = <&rst SPTIMER0_RESET>;
839 reset-names = "timer";
842 timer1: timer1@ffc09000 {
843 compatible = "snps,dw-apb-timer";
844 interrupts = <0 168 4>;
845 reg = <0xffc09000 0x1000>;
846 clocks = <&l4_sp_clk>;
847 clock-names = "timer";
848 resets = <&rst SPTIMER1_RESET>;
849 reset-names = "timer";
852 timer2: timer2@ffd00000 {
853 compatible = "snps,dw-apb-timer";
854 interrupts = <0 169 4>;
855 reg = <0xffd00000 0x1000>;
857 clock-names = "timer";
858 resets = <&rst OSC1TIMER0_RESET>;
859 reset-names = "timer";
862 timer3: timer3@ffd01000 {
863 compatible = "snps,dw-apb-timer";
864 interrupts = <0 170 4>;
865 reg = <0xffd01000 0x1000>;
867 clock-names = "timer";
868 resets = <&rst OSC1TIMER1_RESET>;
869 reset-names = "timer";
872 uart0: serial0@ffc02000 {
873 compatible = "snps,dw-apb-uart";
874 reg = <0xffc02000 0x1000>;
875 interrupts = <0 162 4>;
878 clocks = <&l4_sp_clk>;
881 dma-names = "tx", "rx";
884 uart1: serial1@ffc03000 {
885 compatible = "snps,dw-apb-uart";
886 reg = <0xffc03000 0x1000>;
887 interrupts = <0 163 4>;
890 clocks = <&l4_sp_clk>;
893 dma-names = "tx", "rx";
898 compatible = "usb-nop-xceiv";
903 compatible = "snps,dwc2";
904 reg = <0xffb00000 0xffff>;
905 interrupts = <0 125 4>;
906 clocks = <&usb_mp_clk>;
908 resets = <&rst USB0_RESET>;
909 reset-names = "dwc2";
911 phy-names = "usb2-phy";
916 compatible = "snps,dwc2";
917 reg = <0xffb40000 0xffff>;
918 interrupts = <0 128 4>;
919 clocks = <&usb_mp_clk>;
921 resets = <&rst USB1_RESET>;
922 reset-names = "dwc2";
924 phy-names = "usb2-phy";
928 watchdog0: watchdog@ffd02000 {
929 compatible = "snps,dw-wdt";
930 reg = <0xffd02000 0x1000>;
931 interrupts = <0 171 4>;
936 watchdog1: watchdog@ffd03000 {
937 compatible = "snps,dw-wdt";
938 reg = <0xffd03000 0x1000>;
939 interrupts = <0 172 4>;