arch/arm/dts/socfpga.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Altera <www.altera.com>
   4  */
   5
   6 #include <dt-bindings/reset/altr,rst-mgr.h>
   7
   8 / {
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11
  12         aliases {
  13                 serial0 = &uart0;
  14                 serial1 = &uart1;
  15                 timer0 = &timer0;
  16                 timer1 = &timer1;
  17                 timer2 = &timer2;
  18                 timer3 = &timer3;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 enable-method = "altr,socfpga-smp";
  25
  26                 cpu0: cpu@0 {
  27                         compatible = "arm,cortex-a9";
  28                         device_type = "cpu";
  29                         reg = <0>;
  30                         next-level-cache = <&L2>;
  31                 };
  32                 cpu1: cpu@1 {
  33                         compatible = "arm,cortex-a9";
  34                         device_type = "cpu";
  35                         reg = <1>;
  36                         next-level-cache = <&L2>;
  37                 };
  38         };
  39
  40         pmu: pmu@ff111000 {
  41                 compatible = "arm,cortex-a9-pmu";
  42                 interrupt-parent = <&intc>;
  43                 interrupts = <0 176 4>, <0 177 4>;
  44                 interrupt-affinity = <&cpu0>, <&cpu1>;
  45                 reg = <0xff111000 0x1000>,
  46                       <0xff113000 0x1000>;
  47         };
  48
  49         intc: intc@fffed000 {
  50                 compatible = "arm,cortex-a9-gic";
  51                 #interrupt-cells = <3>;
  52                 interrupt-controller;
  53                 reg = <0xfffed000 0x1000>,
  54                       <0xfffec100 0x100>;
  55         };
  56
  57         soc {
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 compatible = "simple-bus";
  61                 device_type = "soc";
  62                 interrupt-parent = <&intc>;
  63                 ranges;
  64
  65                 amba {
  66                         compatible = "simple-bus";
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69                         ranges;
  70
  71                         pdma: pdma@ffe01000 {
  72                                 compatible = "arm,pl330", "arm,primecell";
  73                                 reg = <0xffe01000 0x1000>;
  74                                 interrupts = <0 104 4>,
  75                                              <0 105 4>,
  76                                              <0 106 4>,
  77                                              <0 107 4>,
  78                                              <0 108 4>,
  79                                              <0 109 4>,
  80                                              <0 110 4>,
  81                                              <0 111 4>;
  82                                 #dma-cells = <1>;
  83                                 #dma-channels = <8>;
  84                                 #dma-requests = <32>;
  85                                 clocks = <&l4_main_clk>;
  86                                 clock-names = "apb_pclk";
  87                         };
  88                 };
  89
  90                 base_fpga_region {
  91                         compatible = "fpga-region";
  92                         fpga-mgr = <&fpgamgr0>;
  93
  94                         #address-cells = <0x1>;
  95                         #size-cells = <0x1>;
  96                 };
  97
  98                 can0: can@ffc00000 {
  99                         compatible = "bosch,d_can";
 100                         reg = <0xffc00000 0x1000>;
 101                         interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
 102                         clocks = <&can0_clk>;
 103                         status = "disabled";
 104                 };
 105
 106                 can1: can@ffc01000 {
 107                         compatible = "bosch,d_can";
 108                         reg = <0xffc01000 0x1000>;
 109                         interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
 110                         clocks = <&can1_clk>;
 111                         status = "disabled";
 112                 };
 113
 114                 clkmgr@ffd04000 {
 115                                 compatible = "altr,clk-mgr";
 116                                 reg = <0xffd04000 0x1000>;
 117
 118                                 clocks {
 119                                         #address-cells = <1>;
 120                                         #size-cells = <0>;
 121
 122                                         osc1: osc1 {
 123                                                 #clock-cells = <0>;
 124                                                 compatible = "fixed-clock";
 125                                         };
 126
 127                                         osc2: osc2 {
 128                                                 #clock-cells = <0>;
 129                                                 compatible = "fixed-clock";
 130                                         };
 131
 132                                         f2s_periph_ref_clk: f2s_periph_ref_clk {
 133                                                 #clock-cells = <0>;
 134                                                 compatible = "fixed-clock";
 135                                         };
 136
 137                                         f2s_sdram_ref_clk: f2s_sdram_ref_clk {
 138                                                 #clock-cells = <0>;
 139                                                 compatible = "fixed-clock";
 140                                         };
 141
 142                                         main_pll: main_pll@40 {
 143                                                 #address-cells = <1>;
 144                                                 #size-cells = <0>;
 145                                                 #clock-cells = <0>;
 146                                                 compatible = "altr,socfpga-pll-clock";
 147                                                 clocks = <&osc1>;
 148                                                 reg = <0x40>;
 149
 150                                                 mpuclk: mpuclk@48 {
 151                                                         #clock-cells = <0>;
 152                                                         compatible = "altr,socfpga-perip-clk";
 153                                                         clocks = <&main_pll>;
 154                                                         div-reg = <0xe0 0 9>;
 155                                                         reg = <0x48>;
 156                                                 };
 157
 158                                                 mainclk: mainclk@4c {
 159                                                         #clock-cells = <0>;
 160                                                         compatible = "altr,socfpga-perip-clk";
 161                                                         clocks = <&main_pll>;
 162                                                         div-reg = <0xe4 0 9>;
 163                                                         reg = <0x4C>;
 164                                                 };
 165
 166                                                 dbg_base_clk: dbg_base_clk@50 {
 167                                                         #clock-cells = <0>;
 168                                                         compatible = "altr,socfpga-perip-clk";
 169                                                         clocks = <&main_pll>, <&osc1>;
 170                                                         div-reg = <0xe8 0 9>;
 171                                                         reg = <0x50>;
 172                                                 };
 173
 174                                                 main_qspi_clk: main_qspi_clk@54 {
 175                                                         #clock-cells = <0>;
 176                                                         compatible = "altr,socfpga-perip-clk";
 177                                                         clocks = <&main_pll>;
 178                                                         reg = <0x54>;
 179                                                 };
 180
 181                                                 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
 182                                                         #clock-cells = <0>;
 183                                                         compatible = "altr,socfpga-perip-clk";
 184                                                         clocks = <&main_pll>;
 185                                                         reg = <0x58>;
 186                                                 };
 187
 188                                                 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
 189                                                         #clock-cells = <0>;
 190                                                         compatible = "altr,socfpga-perip-clk";
 191                                                         clocks = <&main_pll>;
 192                                                         reg = <0x5C>;
 193                                                 };
 194                                         };
 195
 196                                         periph_pll: periph_pll@80 {
 197                                                 #address-cells = <1>;
 198                                                 #size-cells = <0>;
 199                                                 #clock-cells = <0>;
 200                                                 compatible = "altr,socfpga-pll-clock";
 201                                                 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
 202                                                 reg = <0x80>;
 203
 204                                                 emac0_clk: emac0_clk@88 {
 205                                                         #clock-cells = <0>;
 206                                                         compatible = "altr,socfpga-perip-clk";
 207                                                         clocks = <&periph_pll>;
 208                                                         reg = <0x88>;
 209                                                 };
 210
 211                                                 emac1_clk: emac1_clk@8c {
 212                                                         #clock-cells = <0>;
 213                                                         compatible = "altr,socfpga-perip-clk";
 214                                                         clocks = <&periph_pll>;
 215                                                         reg = <0x8C>;
 216                                                 };
 217
 218                                                 per_qspi_clk: per_qsi_clk@90 {
 219                                                         #clock-cells = <0>;
 220                                                         compatible = "altr,socfpga-perip-clk";
 221                                                         clocks = <&periph_pll>;
 222                                                         reg = <0x90>;
 223                                                 };
 224
 225                                                 per_nand_mmc_clk: per_nand_mmc_clk@94 {
 226                                                         #clock-cells = <0>;
 227                                                         compatible = "altr,socfpga-perip-clk";
 228                                                         clocks = <&periph_pll>;
 229                                                         reg = <0x94>;
 230                                                 };
 231
 232                                                 per_base_clk: per_base_clk@98 {
 233                                                         #clock-cells = <0>;
 234                                                         compatible = "altr,socfpga-perip-clk";
 235                                                         clocks = <&periph_pll>;
 236                                                         reg = <0x98>;
 237                                                 };
 238
 239                                                 h2f_usr1_clk: h2f_usr1_clk@9c {
 240                                                         #clock-cells = <0>;
 241                                                         compatible = "altr,socfpga-perip-clk";
 242                                                         clocks = <&periph_pll>;
 243                                                         reg = <0x9C>;
 244                                                 };
 245                                         };
 246
 247                                         sdram_pll: sdram_pll@c0 {
 248                                                 #address-cells = <1>;
 249                                                 #size-cells = <0>;
 250                                                 #clock-cells = <0>;
 251                                                 compatible = "altr,socfpga-pll-clock";
 252                                                 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
 253                                                 reg = <0xC0>;
 254
 255                                                 ddr_dqs_clk: ddr_dqs_clk@c8 {
 256                                                         #clock-cells = <0>;
 257                                                         compatible = "altr,socfpga-perip-clk";
 258                                                         clocks = <&sdram_pll>;
 259                                                         reg = <0xC8>;
 260                                                 };
 261
 262                                                 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
 263                                                         #clock-cells = <0>;
 264                                                         compatible = "altr,socfpga-perip-clk";
 265                                                         clocks = <&sdram_pll>;
 266                                                         reg = <0xCC>;
 267                                                 };
 268
 269                                                 ddr_dq_clk: ddr_dq_clk@d0 {
 270                                                         #clock-cells = <0>;
 271                                                         compatible = "altr,socfpga-perip-clk";
 272                                                         clocks = <&sdram_pll>;
 273                                                         reg = <0xD0>;
 274                                                 };
 275
 276                                                 h2f_usr2_clk: h2f_usr2_clk@d4 {
 277                                                         #clock-cells = <0>;
 278                                                         compatible = "altr,socfpga-perip-clk";
 279                                                         clocks = <&sdram_pll>;
 280                                                         reg = <0xD4>;
 281                                                 };
 282                                         };
 283
 284                                         mpu_periph_clk: mpu_periph_clk {
 285                                                 #clock-cells = <0>;
 286                                                 compatible = "altr,socfpga-perip-clk";
 287                                                 clocks = <&mpuclk>;
 288                                                 fixed-divider = <4>;
 289                                         };
 290
 291                                         mpu_l2_ram_clk: mpu_l2_ram_clk {
 292                                                 #clock-cells = <0>;
 293                                                 compatible = "altr,socfpga-perip-clk";
 294                                                 clocks = <&mpuclk>;
 295                                                 fixed-divider = <2>;
 296                                         };
 297
 298                                         l4_main_clk: l4_main_clk {
 299                                                 #clock-cells = <0>;
 300                                                 compatible = "altr,socfpga-gate-clk";
 301                                                 clocks = <&mainclk>;
 302                                                 clk-gate = <0x60 0>;
 303                                         };
 304
 305                                         l3_main_clk: l3_main_clk {
 306                                                 #clock-cells = <0>;
 307                                                 compatible = "altr,socfpga-perip-clk";
 308                                                 clocks = <&mainclk>;
 309                                                 fixed-divider = <1>;
 310                                         };
 311
 312                                         l3_mp_clk: l3_mp_clk {
 313                                                 #clock-cells = <0>;
 314                                                 compatible = "altr,socfpga-gate-clk";
 315                                                 clocks = <&mainclk>;
 316                                                 div-reg = <0x64 0 2>;
 317                                                 clk-gate = <0x60 1>;
 318                                         };
 319
 320                                         l3_sp_clk: l3_sp_clk {
 321                                                 #clock-cells = <0>;
 322                                                 compatible = "altr,socfpga-gate-clk";
 323                                                 clocks = <&l3_mp_clk>;
 324                                                 div-reg = <0x64 2 2>;
 325                                         };
 326
 327                                         l4_mp_clk: l4_mp_clk {
 328                                                 #clock-cells = <0>;
 329                                                 compatible = "altr,socfpga-gate-clk";
 330                                                 clocks = <&mainclk>, <&per_base_clk>;
 331                                                 div-reg = <0x64 4 3>;
 332                                                 clk-gate = <0x60 2>;
 333                                         };
 334
 335                                         l4_sp_clk: l4_sp_clk {
 336                                                 #clock-cells = <0>;
 337                                                 compatible = "altr,socfpga-gate-clk";
 338                                                 clocks = <&mainclk>, <&per_base_clk>;
 339                                                 div-reg = <0x64 7 3>;
 340                                                 clk-gate = <0x60 3>;
 341                                         };
 342
 343                                         dbg_at_clk: dbg_at_clk {
 344                                                 #clock-cells = <0>;
 345                                                 compatible = "altr,socfpga-gate-clk";
 346                                                 clocks = <&dbg_base_clk>;
 347                                                 div-reg = <0x68 0 2>;
 348                                                 clk-gate = <0x60 4>;
 349                                         };
 350
 351                                         dbg_clk: dbg_clk {
 352                                                 #clock-cells = <0>;
 353                                                 compatible = "altr,socfpga-gate-clk";
 354                                                 clocks = <&dbg_at_clk>;
 355                                                 div-reg = <0x68 2 2>;
 356                                                 clk-gate = <0x60 5>;
 357                                         };
 358
 359                                         dbg_trace_clk: dbg_trace_clk {
 360                                                 #clock-cells = <0>;
 361                                                 compatible = "altr,socfpga-gate-clk";
 362                                                 clocks = <&dbg_base_clk>;
 363                                                 div-reg = <0x6C 0 3>;
 364                                                 clk-gate = <0x60 6>;
 365                                         };
 366
 367                                         dbg_timer_clk: dbg_timer_clk {
 368                                                 #clock-cells = <0>;
 369                                                 compatible = "altr,socfpga-gate-clk";
 370                                                 clocks = <&dbg_base_clk>;
 371                                                 clk-gate = <0x60 7>;
 372                                         };
 373
 374                                         cfg_clk: cfg_clk {
 375                                                 #clock-cells = <0>;
 376                                                 compatible = "altr,socfpga-gate-clk";
 377                                                 clocks = <&cfg_h2f_usr0_clk>;
 378                                                 clk-gate = <0x60 8>;
 379                                         };
 380
 381                                         h2f_user0_clk: h2f_user0_clk {
 382                                                 #clock-cells = <0>;
 383                                                 compatible = "altr,socfpga-gate-clk";
 384                                                 clocks = <&cfg_h2f_usr0_clk>;
 385                                                 clk-gate = <0x60 9>;
 386                                         };
 387
 388                                         emac_0_clk: emac_0_clk {
 389                                                 #clock-cells = <0>;
 390                                                 compatible = "altr,socfpga-gate-clk";
 391                                                 clocks = <&emac0_clk>;
 392                                                 clk-gate = <0xa0 0>;
 393                                         };
 394
 395                                         emac_1_clk: emac_1_clk {
 396                                                 #clock-cells = <0>;
 397                                                 compatible = "altr,socfpga-gate-clk";
 398                                                 clocks = <&emac1_clk>;
 399                                                 clk-gate = <0xa0 1>;
 400                                         };
 401
 402                                         usb_mp_clk: usb_mp_clk {
 403                                                 #clock-cells = <0>;
 404                                                 compatible = "altr,socfpga-gate-clk";
 405                                                 clocks = <&per_base_clk>;
 406                                                 clk-gate = <0xa0 2>;
 407                                                 div-reg = <0xa4 0 3>;
 408                                         };
 409
 410                                         spi_m_clk: spi_m_clk {
 411                                                 #clock-cells = <0>;
 412                                                 compatible = "altr,socfpga-gate-clk";
 413                                                 clocks = <&per_base_clk>;
 414                                                 clk-gate = <0xa0 3>;
 415                                                 div-reg = <0xa4 3 3>;
 416                                         };
 417
 418                                         can0_clk: can0_clk {
 419                                                 #clock-cells = <0>;
 420                                                 compatible = "altr,socfpga-gate-clk";
 421                                                 clocks = <&per_base_clk>;
 422                                                 clk-gate = <0xa0 4>;
 423                                                 div-reg = <0xa4 6 3>;
 424                                         };
 425
 426                                         can1_clk: can1_clk {
 427                                                 #clock-cells = <0>;
 428                                                 compatible = "altr,socfpga-gate-clk";
 429                                                 clocks = <&per_base_clk>;
 430                                                 clk-gate = <0xa0 5>;
 431                                                 div-reg = <0xa4 9 3>;
 432                                         };
 433
 434                                         gpio_db_clk: gpio_db_clk {
 435                                                 #clock-cells = <0>;
 436                                                 compatible = "altr,socfpga-gate-clk";
 437                                                 clocks = <&per_base_clk>;
 438                                                 clk-gate = <0xa0 6>;
 439                                                 div-reg = <0xa8 0 24>;
 440                                         };
 441
 442                                         h2f_user1_clk: h2f_user1_clk {
 443                                                 #clock-cells = <0>;
 444                                                 compatible = "altr,socfpga-gate-clk";
 445                                                 clocks = <&h2f_usr1_clk>;
 446                                                 clk-gate = <0xa0 7>;
 447                                         };
 448
 449                                         sdmmc_clk: sdmmc_clk {
 450                                                 #clock-cells = <0>;
 451                                                 compatible = "altr,socfpga-gate-clk";
 452                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 453                                                 clk-gate = <0xa0 8>;
 454                                                 clk-phase = <0 135>;
 455                                         };
 456
 457                                         sdmmc_clk_divided: sdmmc_clk_divided {
 458                                                 #clock-cells = <0>;
 459                                                 compatible = "altr,socfpga-gate-clk";
 460                                                 clocks = <&sdmmc_clk>;
 461                                                 clk-gate = <0xa0 8>;
 462                                                 fixed-divider = <4>;
 463                                         };
 464
 465                                         nand_x_clk: nand_x_clk {
 466                                                 #clock-cells = <0>;
 467                                                 compatible = "altr,socfpga-gate-clk";
 468                                                 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
 469                                                 clk-gate = <0xa0 9>;
 470                                         };
 471
 472                                         nand_ecc_clk: nand_ecc_clk {
 473                                                 #clock-cells = <0>;
 474                                                 compatible = "altr,socfpga-gate-clk";
 475                                                 clocks = <&nand_x_clk>;
 476                                                 clk-gate = <0xa0 9>;
 477                                         };
 478
 479                                         nand_clk: nand_clk {
 480                                                 #clock-cells = <0>;
 481                                                 compatible = "altr,socfpga-gate-clk";
 482                                                 clocks = <&nand_x_clk>;
 483                                                 clk-gate = <0xa0 10>;
 484                                                 fixed-divider = <4>;
 485                                         };
 486
 487                                         qspi_clk: qspi_clk {
 488                                                 #clock-cells = <0>;
 489                                                 compatible = "altr,socfpga-gate-clk";
 490                                                 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
 491                                                 clk-gate = <0xa0 11>;
 492                                         };
 493
 494                                         ddr_dqs_clk_gate: ddr_dqs_clk_gate {
 495                                                 #clock-cells = <0>;
 496                                                 compatible = "altr,socfpga-gate-clk";
 497                                                 clocks = <&ddr_dqs_clk>;
 498                                                 clk-gate = <0xd8 0>;
 499                                         };
 500
 501                                         ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
 502                                                 #clock-cells = <0>;
 503                                                 compatible = "altr,socfpga-gate-clk";
 504                                                 clocks = <&ddr_2x_dqs_clk>;
 505                                                 clk-gate = <0xd8 1>;
 506                                         };
 507
 508                                         ddr_dq_clk_gate: ddr_dq_clk_gate {
 509                                                 #clock-cells = <0>;
 510                                                 compatible = "altr,socfpga-gate-clk";
 511                                                 clocks = <&ddr_dq_clk>;
 512                                                 clk-gate = <0xd8 2>;
 513                                         };
 514
 515                                         h2f_user2_clk: h2f_user2_clk {
 516                                                 #clock-cells = <0>;
 517                                                 compatible = "altr,socfpga-gate-clk";
 518                                                 clocks = <&h2f_usr2_clk>;
 519                                                 clk-gate = <0xd8 3>;
 520                                         };
 521
 522                                 };
 523                 };
 524
 525                 fpga_bridge0: fpga_bridge@ff400000 {
 526                         compatible = "altr,socfpga-lwhps2fpga-bridge";
 527                         reg = <0xff400000 0x100000>;
 528                         resets = <&rst LWHPS2FPGA_RESET>;
 529                         clocks = <&l4_main_clk>;
 530                 };
 531
 532                 fpga_bridge1: fpga_bridge@ff500000 {
 533                         compatible = "altr,socfpga-hps2fpga-bridge";
 534                         reg = <0xff500000 0x10000>;
 535                         resets = <&rst HPS2FPGA_RESET>;
 536                         clocks = <&l4_main_clk>;
 537                 };
 538
 539                 fpgamgr0: fpgamgr@ff706000 {
 540                         compatible = "altr,socfpga-fpga-mgr";
 541                         reg = <0xff706000 0x1000
 542                                0xffb90000 0x4>;
 543                         interrupts = <0 175 4>;
 544                 };
 545
 546                 gmac0: ethernet@ff700000 {
 547                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 548                         altr,sysmgr-syscon = <&sysmgr 0x60 0>;
 549                         reg = <0xff700000 0x2000>;
 550                         interrupts = <0 115 4>;
 551                         interrupt-names = "macirq";
 552                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 553                         clocks = <&emac_0_clk>;
 554                         clock-names = "stmmaceth";
 555                         resets = <&rst EMAC0_RESET>;
 556                         reset-names = "stmmaceth";
 557                         snps,multicast-filter-bins = <256>;
 558                         snps,perfect-filter-entries = <128>;
 559                         tx-fifo-depth = <4096>;
 560                         rx-fifo-depth = <4096>;
 561                         status = "disabled";
 562                 };
 563
 564                 gmac1: ethernet@ff702000 {
 565                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
 566                         altr,sysmgr-syscon = <&sysmgr 0x60 2>;
 567                         reg = <0xff702000 0x2000>;
 568                         interrupts = <0 120 4>;
 569                         interrupt-names = "macirq";
 570                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
 571                         clocks = <&emac_1_clk>;
 572                         clock-names = "stmmaceth";
 573                         resets = <&rst EMAC1_RESET>;
 574                         reset-names = "stmmaceth";
 575                         snps,multicast-filter-bins = <256>;
 576                         snps,perfect-filter-entries = <128>;
 577                         tx-fifo-depth = <4096>;
 578                         rx-fifo-depth = <4096>;
 579                         status = "disabled";
 580                 };
 581
 582                 gpio0: gpio@ff708000 {
 583                         #address-cells = <1>;
 584                         #size-cells = <0>;
 585                         compatible = "snps,dw-apb-gpio";
 586                         reg = <0xff708000 0x1000>;
 587                         clocks = <&l4_mp_clk>;
 588                         status = "disabled";
 589
 590                         porta: gpio-controller@0 {
 591                                 compatible = "snps,dw-apb-gpio-port";
 592                                 gpio-controller;
 593                                 #gpio-cells = <2>;
 594                                 snps,nr-gpios = <29>;
 595                                 reg = <0>;
 596                                 interrupt-controller;
 597                                 #interrupt-cells = <2>;
 598                                 interrupts = <0 164 4>;
 599                         };
 600                 };
 601
 602                 gpio1: gpio@ff709000 {
 603                         #address-cells = <1>;
 604                         #size-cells = <0>;
 605                         compatible = "snps,dw-apb-gpio";
 606                         reg = <0xff709000 0x1000>;
 607                         clocks = <&l4_mp_clk>;
 608                         status = "disabled";
 609
 610                         portb: gpio-controller@0 {
 611                                 compatible = "snps,dw-apb-gpio-port";
 612                                 gpio-controller;
 613                                 #gpio-cells = <2>;
 614                                 snps,nr-gpios = <29>;
 615                                 reg = <0>;
 616                                 interrupt-controller;
 617                                 #interrupt-cells = <2>;
 618                                 interrupts = <0 165 4>;
 619                         };
 620                 };
 621
 622                 gpio2: gpio@ff70a000 {
 623                         #address-cells = <1>;
 624                         #size-cells = <0>;
 625                         compatible = "snps,dw-apb-gpio";
 626                         reg = <0xff70a000 0x1000>;
 627                         clocks = <&l4_mp_clk>;
 628                         status = "disabled";
 629
 630                         portc: gpio-controller@0 {
 631                                 compatible = "snps,dw-apb-gpio-port";
 632                                 gpio-controller;
 633                                 #gpio-cells = <2>;
 634                                 snps,nr-gpios = <27>;
 635                                 reg = <0>;
 636                                 interrupt-controller;
 637                                 #interrupt-cells = <2>;
 638                                 interrupts = <0 166 4>;
 639                         };
 640                 };
 641
 642                 i2c0: i2c@ffc04000 {
 643                         #address-cells = <1>;
 644                         #size-cells = <0>;
 645                         compatible = "snps,designware-i2c";
 646                         reg = <0xffc04000 0x1000>;
 647                         resets = <&rst I2C0_RESET>;
 648                         clocks = <&l4_sp_clk>;
 649                         interrupts = <0 158 0x4>;
 650                         status = "disabled";
 651                 };
 652
 653                 i2c1: i2c@ffc05000 {
 654                         #address-cells = <1>;
 655                         #size-cells = <0>;
 656                         compatible = "snps,designware-i2c";
 657                         reg = <0xffc05000 0x1000>;
 658                         resets = <&rst I2C1_RESET>;
 659                         clocks = <&l4_sp_clk>;
 660                         interrupts = <0 159 0x4>;
 661                         status = "disabled";
 662                 };
 663
 664                 i2c2: i2c@ffc06000 {
 665                         #address-cells = <1>;
 666                         #size-cells = <0>;
 667                         compatible = "snps,designware-i2c";
 668                         reg = <0xffc06000 0x1000>;
 669                         resets = <&rst I2C2_RESET>;
 670                         clocks = <&l4_sp_clk>;
 671                         interrupts = <0 160 0x4>;
 672                         status = "disabled";
 673                 };
 674
 675                 i2c3: i2c@ffc07000 {
 676                         #address-cells = <1>;
 677                         #size-cells = <0>;
 678                         compatible = "snps,designware-i2c";
 679                         reg = <0xffc07000 0x1000>;
 680                         resets = <&rst I2C3_RESET>;
 681                         clocks = <&l4_sp_clk>;
 682                         interrupts = <0 161 0x4>;
 683                         status = "disabled";
 684                 };
 685
 686                 eccmgr: eccmgr {
 687                         compatible = "altr,socfpga-ecc-manager";
 688                         #address-cells = <1>;
 689                         #size-cells = <1>;
 690                         ranges;
 691
 692                         l2-ecc@ffd08140 {
 693                                 compatible = "altr,socfpga-l2-ecc";
 694                                 reg = <0xffd08140 0x4>;
 695                                 interrupts = <0 36 1>, <0 37 1>;
 696                         };
 697
 698                         ocram-ecc@ffd08144 {
 699                                 compatible = "altr,socfpga-ocram-ecc";
 700                                 reg = <0xffd08144 0x4>;
 701                                 iram = <&ocram>;
 702                                 interrupts = <0 178 1>, <0 179 1>;
 703                         };
 704                 };
 705
 706                 L2: l2-cache@fffef000 {
 707                         compatible = "arm,pl310-cache";
 708                         reg = <0xfffef000 0x1000>;
 709                         interrupts = <0 38 0x04>;
 710                         cache-unified;
 711                         cache-level = <2>;
 712                         arm,tag-latency = <1 1 1>;
 713                         arm,data-latency = <2 1 1>;
 714                         prefetch-data = <1>;
 715                         prefetch-instr = <1>;
 716                         arm,shared-override;
 717                         arm,double-linefill = <1>;
 718                         arm,double-linefill-incr = <0>;
 719                         arm,double-linefill-wrap = <1>;
 720                         arm,prefetch-drop = <0>;
 721                         arm,prefetch-offset = <7>;
 722                 };
 723
 724                 l3regs@0xff800000 {
 725                         compatible = "altr,l3regs", "syscon";
 726                         reg = <0xff800000 0x1000>;
 727                 };
 728
 729                 mmc: dwmmc0@ff704000 {
 730                         compatible = "altr,socfpga-dw-mshc";
 731                         reg = <0xff704000 0x1000>;
 732                         interrupts = <0 139 4>;
 733                         fifo-depth = <0x400>;
 734                         #address-cells = <1>;
 735                         #size-cells = <0>;
 736                         clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
 737                         clock-names = "biu", "ciu";
 738                         status = "disabled";
 739                 };
 740
 741                 nand0: nand@ff900000 {
 742                         #address-cells = <0x1>;
 743                         #size-cells = <0x1>;
 744                         compatible = "altr,socfpga-denali-nand";
 745                         reg = <0xff900000 0x100000>,
 746                               <0xffb80000 0x10000>;
 747                         reg-names = "nand_data", "denali_reg";
 748                         interrupts = <0x0 0x90 0x4>;
 749                         dma-mask = <0xffffffff>;
 750                         clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
 751                         clock-names = "nand", "nand_x", "ecc";
 752                         status = "disabled";
 753                 };
 754
 755                 ocram: sram@ffff0000 {
 756                         compatible = "mmio-sram";
 757                         reg = <0xffff0000 0x10000>;
 758                 };
 759
 760                 qspi: spi@ff705000 {
 761                         compatible = "cdns,qspi-nor";
 762                         #address-cells = <1>;
 763                         #size-cells = <0>;
 764                         reg = <0xff705000 0x1000>,
 765                               <0xffa00000 0x1000>;
 766                         interrupts = <0 151 4>;
 767                         cdns,fifo-depth = <128>;
 768                         cdns,fifo-width = <4>;
 769                         cdns,trigger-address = <0x00000000>;
 770                         clocks = <&qspi_clk>;
 771                         status = "disabled";
 772                 };
 773
 774                 rst: rstmgr@ffd05000 {
 775                         #reset-cells = <1>;
 776                         compatible = "altr,rst-mgr";
 777                         reg = <0xffd05000 0x1000>;
 778                         altr,modrst-offset = <0x10>;
 779                 };
 780
 781                 scu: snoop-control-unit@fffec000 {
 782                         compatible = "arm,cortex-a9-scu";
 783                         reg = <0xfffec000 0x100>;
 784                 };
 785
 786                 sdr: sdr@ffc25000 {
 787                         compatible = "altr,sdr-ctl", "syscon";
 788                         reg = <0xffc25000 0x1000>;
 789                 };
 790
 791                 sdramedac {
 792                         compatible = "altr,sdram-edac";
 793                         altr,sdr-syscon = <&sdr>;
 794                         interrupts = <0 39 4>;
 795                 };
 796
 797                 spi0: spi@fff00000 {
 798                         compatible = "snps,dw-apb-ssi";
 799                         #address-cells = <1>;
 800                         #size-cells = <0>;
 801                         reg = <0xfff00000 0x1000>;
 802                         interrupts = <0 154 4>;
 803                         num-cs = <4>;
 804                         clocks = <&spi_m_clk>;
 805                         status = "disabled";
 806                 };
 807
 808                 spi1: spi@fff01000 {
 809                         compatible = "snps,dw-apb-ssi";
 810                         #address-cells = <1>;
 811                         #size-cells = <0>;
 812                         reg = <0xfff01000 0x1000>;
 813                         interrupts = <0 155 4>;
 814                         num-cs = <4>;
 815                         clocks = <&spi_m_clk>;
 816                         status = "disabled";
 817                 };
 818
 819                 sysmgr: sysmgr@ffd08000 {
 820                         compatible = "altr,sys-mgr", "syscon";
 821                         reg = <0xffd08000 0x4000>;
 822                 };
 823
 824                 /* Local timer */
 825                 timer@fffec600 {
 826                         compatible = "arm,cortex-a9-twd-timer";
 827                         reg = <0xfffec600 0x100>;
 828                         interrupts = <1 13 0xf01>;
 829                         clocks = <&mpu_periph_clk>;
 830                 };
 831
 832                 timer0: timer0@ffc08000 {
 833                         compatible = "snps,dw-apb-timer";
 834                         interrupts = <0 167 4>;
 835                         reg = <0xffc08000 0x1000>;
 836                         clocks = <&l4_sp_clk>;
 837                         clock-names = "timer";
 838                         resets = <&rst SPTIMER0_RESET>;
 839                         reset-names = "timer";
 840                 };
 841
 842                 timer1: timer1@ffc09000 {
 843                         compatible = "snps,dw-apb-timer";
 844                         interrupts = <0 168 4>;
 845                         reg = <0xffc09000 0x1000>;
 846                         clocks = <&l4_sp_clk>;
 847                         clock-names = "timer";
 848                         resets = <&rst SPTIMER1_RESET>;
 849                         reset-names = "timer";
 850                 };
 851
 852                 timer2: timer2@ffd00000 {
 853                         compatible = "snps,dw-apb-timer";
 854                         interrupts = <0 169 4>;
 855                         reg = <0xffd00000 0x1000>;
 856                         clocks = <&osc1>;
 857                         clock-names = "timer";
 858                         resets = <&rst OSC1TIMER0_RESET>;
 859                         reset-names = "timer";
 860                 };
 861
 862                 timer3: timer3@ffd01000 {
 863                         compatible = "snps,dw-apb-timer";
 864                         interrupts = <0 170 4>;
 865                         reg = <0xffd01000 0x1000>;
 866                         clocks = <&osc1>;
 867                         clock-names = "timer";
 868                         resets = <&rst OSC1TIMER1_RESET>;
 869                         reset-names = "timer";
 870                 };
 871
 872                 uart0: serial0@ffc02000 {
 873                         compatible = "snps,dw-apb-uart";
 874                         reg = <0xffc02000 0x1000>;
 875                         interrupts = <0 162 4>;
 876                         reg-shift = <2>;
 877                         reg-io-width = <4>;
 878                         clocks = <&l4_sp_clk>;
 879                         dmas = <&pdma 28>,
 880                                <&pdma 29>;
 881                         dma-names = "tx", "rx";
 882                 };
 883
 884                 uart1: serial1@ffc03000 {
 885                         compatible = "snps,dw-apb-uart";
 886                         reg = <0xffc03000 0x1000>;
 887                         interrupts = <0 163 4>;
 888                         reg-shift = <2>;
 889                         reg-io-width = <4>;
 890                         clocks = <&l4_sp_clk>;
 891                         dmas = <&pdma 30>,
 892                                <&pdma 31>;
 893                         dma-names = "tx", "rx";
 894                 };
 895
 896                 usbphy0: usbphy {
 897                         #phy-cells = <0>;
 898                         compatible = "usb-nop-xceiv";
 899                         status = "okay";
 900                 };
 901
 902                 usb0: usb@ffb00000 {
 903                         compatible = "snps,dwc2";
 904                         reg = <0xffb00000 0xffff>;
 905                         interrupts = <0 125 4>;
 906                         clocks = <&usb_mp_clk>;
 907                         clock-names = "otg";
 908                         resets = <&rst USB0_RESET>;
 909                         reset-names = "dwc2";
 910                         phys = <&usbphy0>;
 911                         phy-names = "usb2-phy";
 912                         status = "disabled";
 913                 };
 914
 915                 usb1: usb@ffb40000 {
 916                         compatible = "snps,dwc2";
 917                         reg = <0xffb40000 0xffff>;
 918                         interrupts = <0 128 4>;
 919                         clocks = <&usb_mp_clk>;
 920                         clock-names = "otg";
 921                         resets = <&rst USB1_RESET>;
 922                         reset-names = "dwc2";
 923                         phys = <&usbphy0>;
 924                         phy-names = "usb2-phy";
 925                         status = "disabled";
 926                 };
 927
 928                 watchdog0: watchdog@ffd02000 {
 929                         compatible = "snps,dw-wdt";
 930                         reg = <0xffd02000 0x1000>;
 931                         interrupts = <0 171 4>;
 932                         clocks = <&osc1>;
 933                         status = "disabled";
 934                 };
 935
 936                 watchdog1: watchdog@ffd03000 {
 937                         compatible = "snps,dw-wdt";
 938                         reg = <0xffd03000 0x1000>;
 939                         interrupts = <0 172 4>;
 940                         clocks = <&osc1>;
 941                         status = "disabled";
 942                 };
 943         };
 944 };