arch/arm/dts/sam9x60.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
   4  *
   5  * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
   8  */
   9
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/dma/at91.h>
  12 #include <dt-bindings/pinctrl/at91.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/clock/at91.h>
  16
  17 /{
  18         model = "Microchip SAM9X60 SoC";
  19         compatible = "microchip,sam9x60";
  20
  21         aliases {
  22                 serial0 = &dbgu;
  23                 gpio0 = &pioA;
  24                 gpio1 = &pioB;
  25                 gpio3 = &pioD;
  26                 spi0 = &qspi;
  27         };
  28
  29         clocks {
  30                 slow_xtal: slow_xtal {
  31                         compatible = "fixed-clock";
  32                         #clock-cells = <0>;
  33                         clock-frequency = <0>;
  34                 };
  35
  36                 main_xtal: main_xtal {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <0>;
  40                 };
  41         };
  42
  43         ahb {
  44                 compatible = "simple-bus";
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 ranges;
  48
  49                 sdhci0: sdhci-host@80000000 {
  50                         compatible = "microchip,sam9x60-sdhci";
  51                         reg = <0x80000000 0x300>;
  52                         clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
  53                         clock-names = "hclock", "multclk", "baseclk";
  54                         bus-width = <4>;
  55                         pinctrl-names = "default";
  56                         pinctrl-0 = <&pinctrl_sdhci0>;
  57                 };
  58
  59                 apb {
  60                         compatible = "simple-bus";
  61                         #address-cells = <1>;
  62                         #size-cells = <1>;
  63                         ranges;
  64
  65                         qspi: spi@f0014000 {
  66                                 compatible = "microchip,sam9x60-qspi";
  67                                 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
  68                                 reg-names = "qspi_base", "qspi_mmap";
  69                                 clocks =  <&qspi_clk>, <&qspick>;
  70                                 clock-names = "pclk", "qspick";
  71                                 #address-cells = <1>;
  72                                 #size-cells = <0>;
  73                                 status = "disabled";
  74                         };
  75
  76                         flx0: flexcom@f801c600 {
  77                                 compatible = "atmel,sama5d2-flexcom";
  78                                 reg = <0xf801c000 0x200>;
  79                                 clocks = <&flx0_clk>;
  80                                 #address-cells = <1>;
  81                                 #size-cells = <1>;
  82                                 ranges = <0x0 0xf801c000 0x800>;
  83                                 status = "disabled";
  84                         };
  85
  86                         macb0: ethernet@f802c000 {
  87                                 compatible = "cdns,sam9x60-macb", "cdns,macb";
  88                                 reg = <0xf802c000 0x100>;
  89                                 pinctrl-names = "default";
  90                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
  91                                 clock-names = "hclk", "pclk";
  92                                 clocks = <&macb0_clk>, <&macb0_clk>;
  93                                 status = "disabled";
  94                         };
  95
  96                         dbgu: serial@fffff200 {
  97                                 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
  98                                 reg = <0xfffff200 0x200>;
  99                                 pinctrl-names = "default";
 100                                 pinctrl-0 = <&pinctrl_dbgu>;
 101                                 clocks = <&dbgu_clk>;
 102                                 clock-names = "usart";
 103                         };
 104
 105                         pinctrl {
 106                                 #address-cells = <1>;
 107                                 #size-cells = <1>;
 108                                 compatible = "microchip,sam9x60-pinctrl", "simple-bus";
 109                                 ranges = <0xfffff400 0xfffff400 0x800>;
 110                                 reg = <0xfffff400 0x200         /* pioA */
 111                                        0xfffff600 0x200         /* pioB */
 112                                        0xfffff800 0x200         /* pioC */
 113                                        0xfffffa00 0x200>;       /* pioD */
 114
 115                                 /* shared pinctrl settings */
 116                                 dbgu {
 117                                         pinctrl_dbgu: dbgu-0 {
 118                                                 atmel,pins =
 119                                                         <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
 120                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
 121                                         };
 122                                 };
 123
 124                                 macb0 {
 125                                         pinctrl_macb0_rmii: macb0_rmii-0 {
 126                                                 atmel,pins =
 127                                                         <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
 128                                                          AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
 129                                                          AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
 130                                                          AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
 131                                                          AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
 132                                                          AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
 133                                                          AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
 134                                                          AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
 135                                                          AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
 136                                                          AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
 137                                         };
 138                                 };
 139
 140                                 sdhci0 {
 141                                         pinctrl_sdhci0: sdhci0 {
 142                                                 atmel,pins =
 143                                                         <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK  periph A with pullup */
 144                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA16 CMD periph A with pullup */
 145                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA15 DAT0 periph A */
 146                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA18 DAT1 periph A with pullup */
 147                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA19 DAT2 periph A with pullup */
 148                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;              /* PA20 DAT3 periph A with pullup */
 149                                         };
 150                                 };
 151                         };
 152
 153                         pioA: gpio@fffff400 {
 154                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 155                                 reg = <0xfffff400 0x200>;
 156                                 #gpio-cells = <2>;
 157                                 gpio-controller;
 158                                 clocks = <&pioA_clk>;
 159                         };
 160
 161                         pioB: gpio@fffff600 {
 162                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 163                                 reg = <0xfffff600 0x200>;
 164                                 #gpio-cells = <2>;
 165                                 gpio-controller;
 166                                 clocks = <&pioB_clk>;
 167                         };
 168
 169                         pioD: gpio@fffffa00 {
 170                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 171                                 reg = <0xfffffa00 0x200>;
 172                                 #gpio-cells = <2>;
 173                                 gpio-controller;
 174                                 clocks = <&pioD_clk>;
 175                         };
 176
 177                         pmc: pmc@fffffc00 {
 178                                 compatible = "atmel,at91sam9x5-pmc";
 179                                 reg = <0xfffffc00 0x200>;
 180                                 #address-cells = <1>;
 181                                 #size-cells = <0>;
 182
 183                                 main: mainck {
 184                                         compatible = "atmel,at91sam9x5-clk-main";
 185                                         #clock-cells = <0>;
 186                                 };
 187
 188                                 plla: pllack {
 189                                         compatible = "microchip,sam9x60-clk-pll";
 190                                         #clock-cells = <0>;
 191                                         clocks = <&main>;
 192                                         reg = <0>;
 193                                         atmel,clk-input-range = <8000000 24000000>;
 194                                         #atmel,pll-clk-output-range-cells = <4>;
 195                                         atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>;
 196                                 };
 197
 198                                 mck: masterck {
 199                                         compatible = "atmel,at91sam9x5-clk-master";
 200                                         #clock-cells = <0>;
 201                                         clocks = <&md_slck>, <&main>, <&plla>;
 202                                         atmel,clk-output-range = <140000000 200000000>;
 203                                         atmel,clk-divisors = <1 2 4 6>;
 204                                 };
 205
 206                                 system: systemck {
 207                                         compatible = "atmel,at91rm9200-clk-system";
 208                                         #address-cells = <1>;
 209                                         #size-cells = <0>;
 210
 211                                         qspick: qspick {
 212                                                 #clock-cells = <0>;
 213                                                 reg = <19>;
 214                                                 clocks = <&mck>;
 215                                         };
 216                                 };
 217
 218                                 periph: periphck {
 219                                         compatible = "microchip,sam9x60-clk-peripheral";
 220                                         #address-cells = <1>;
 221                                         #size-cells = <0>;
 222                                         clocks = <&mck>;
 223
 224                                         pioA_clk: pioA_clk {
 225                                                 #clock-cells = <0>;
 226                                                 reg = <2>;
 227                                         };
 228
 229                                         pioB_clk: pioB_clk {
 230                                                 #clock-cells = <0>;
 231                                                 reg = <3>;
 232                                         };
 233
 234                                         flx0_clk: flx0_clk {
 235                                                 #clock-cells = <0>;
 236                                                 reg = <5>;
 237                                         };
 238
 239                                         pioD_clk: pioD_clk {
 240                                                 #clock-cells = <0>;
 241                                                 reg = <44>;
 242                                         };
 243
 244                                         sdhci0_clk: sdhci0_clk {
 245                                                 #clock-cells = <0>;
 246                                                 reg = <12>;
 247                                         };
 248
 249                                         dbgu_clk: dbgu_clk {
 250                                                 #clock-cells = <0>;
 251                                                 reg = <47>;
 252                                         };
 253
 254                                         macb0_clk: macb0_clk {
 255                                                 #clock-cells = <0>;
 256                                                 reg = <24>;
 257                                         };
 258
 259                                         qspi_clk: qspi_clk {
 260                                                 #clock-cells = <0>;
 261                                                 reg = <35>;
 262                                         };
 263                                 };
 264
 265                                 generic: gck {
 266                                         compatible = "microchip,sam9x60-clk-generated";
 267                                         #address-cells = <1>;
 268                                         #size-cells = <0>;
 269                                         clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>;
 270
 271                                         sdhci0_gclk: sdhci0_gclk {
 272                                                 #clock-cells = <0>;
 273                                                 reg = <12>;
 274                                         };
 275                                 };
 276                         };
 277
 278                         pit: timer@fffffe40 {
 279                                 compatible = "atmel,at91sam9260-pit";
 280                                 reg = <0xfffffe40 0x10>;
 281                                 clocks = <&mck>;
 282                         };
 283
 284                         slowckc: sckc@fffffe50 {
 285                                 compatible = "atmel,at91sam9x5-sckc";
 286                                 reg = <0xfffffe50 0x4>;
 287
 288                                 slow_osc: slow_osc {
 289                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
 290                                         #clock-cells = <0>;
 291                                         clocks = <&slow_xtal>;
 292                                 };
 293
 294                                 slow_rc_osc: slow_rc_osc {
 295                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
 296                                         #clock-cells = <0>;
 297                                         clock-frequency = <32768>;
 298                                 };
 299
 300                                 td_slck: td_slck {
 301                                         compatible = "atmel,at91sam9x5-clk-slow";
 302                                         #clock-cells = <0>;
 303                                         clocks = <&slow_rc_osc>, <&slow_osc>;
 304                                 };
 305
 306                                 md_slck: md_slck {
 307                                         compatible = "atmel,at91sam9x5-clk-slow";
 308                                         #clock-cells = <0>;
 309                                         clocks = <&slow_rc_osc>;
 310                                 };
 311                         };
 312                 };
 313         };
 314
 315         onewire_tm: onewire {
 316                 compatible = "w1-gpio";
 317                 status = "disabled";
 318         };
 319 };