arch/arm/dts/sam9x60.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
   4  *
   5  * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
   6  *
   7  * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
   8  */
   9
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/dma/at91.h>
  12 #include <dt-bindings/pinctrl/at91.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/clock/at91.h>
  16
  17 /{
  18         model = "Microchip SAM9X60 SoC";
  19         compatible = "microchip,sam9x60";
  20
  21         aliases {
  22                 serial0 = &dbgu;
  23                 gpio0 = &pioA;
  24                 gpio1 = &pioB;
  25                 spi0 = &qspi;
  26         };
  27
  28         clocks {
  29                 slow_xtal: slow_xtal {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32                         clock-frequency = <0>;
  33                 };
  34
  35                 main_xtal: main_xtal {
  36                         compatible = "fixed-clock";
  37                         #clock-cells = <0>;
  38                         clock-frequency = <0>;
  39                 };
  40         };
  41
  42         ahb {
  43                 compatible = "simple-bus";
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46                 ranges;
  47
  48                 sdhci0: sdhci-host@80000000 {
  49                         compatible = "microchip,sam9x60-sdhci";
  50                         reg = <0x80000000 0x300>;
  51                         clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
  52                         clock-names = "hclock", "multclk", "baseclk";
  53                         bus-width = <4>;
  54                         pinctrl-names = "default";
  55                         pinctrl-0 = <&pinctrl_sdhci0>;
  56                 };
  57
  58                 apb {
  59                         compatible = "simple-bus";
  60                         #address-cells = <1>;
  61                         #size-cells = <1>;
  62                         ranges;
  63
  64                         qspi: spi@f0014000 {
  65                                 compatible = "microchip,sam9x60-qspi";
  66                                 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
  67                                 reg-names = "qspi_base", "qspi_mmap";
  68                                 clocks =  <&qspi_clk>, <&qspick>;
  69                                 clock-names = "pclk", "qspick";
  70                                 #address-cells = <1>;
  71                                 #size-cells = <0>;
  72                                 status = "disabled";
  73                         };
  74
  75                         macb0: ethernet@f802c000 {
  76                                 compatible = "cdns,sam9x60-macb", "cdns,macb";
  77                                 reg = <0xf802c000 0x100>;
  78                                 pinctrl-names = "default";
  79                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
  80                                 clock-names = "hclk", "pclk";
  81                                 clocks = <&macb0_clk>, <&macb0_clk>;
  82                                 status = "disabled";
  83                         };
  84
  85                         dbgu: serial@fffff200 {
  86                                 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
  87                                 reg = <0xfffff200 0x200>;
  88                                 pinctrl-names = "default";
  89                                 pinctrl-0 = <&pinctrl_dbgu>;
  90                                 clocks = <&dbgu_clk>;
  91                                 clock-names = "usart";
  92                         };
  93
  94                         pinctrl {
  95                                 #address-cells = <1>;
  96                                 #size-cells = <1>;
  97                                 compatible = "microchip,sam9x60-pinctrl", "simple-bus";
  98                                 ranges = <0xfffff400 0xfffff400 0x800>;
  99                                 reg = <0xfffff400 0x200         /* pioA */
 100                                        0xfffff600 0x200         /* pioB */
 101                                        0xfffff800 0x200         /* pioC */
 102                                        0xfffffa00 0x200>;       /* pioD */
 103
 104                                 /* shared pinctrl settings */
 105                                 dbgu {
 106                                         pinctrl_dbgu: dbgu-0 {
 107                                                 atmel,pins =
 108                                                         <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
 109                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
 110                                         };
 111                                 };
 112
 113                                 macb0 {
 114                                         pinctrl_macb0_rmii: macb0_rmii-0 {
 115                                                 atmel,pins =
 116                                                         <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
 117                                                          AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
 118                                                          AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
 119                                                          AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
 120                                                          AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
 121                                                          AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
 122                                                          AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
 123                                                          AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
 124                                                          AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
 125                                                          AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
 126                                         };
 127                                 };
 128
 129                                 sdhci0 {
 130                                         pinctrl_sdhci0: sdhci0 {
 131                                                 atmel,pins =
 132                                                         <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK  periph A with pullup */
 133                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA16 CMD periph A with pullup */
 134                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA15 DAT0 periph A */
 135                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA18 DAT1 periph A with pullup */
 136                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP                /* PA19 DAT2 periph A with pullup */
 137                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;              /* PA20 DAT3 periph A with pullup */
 138                                         };
 139                                 };
 140                         };
 141
 142                         pioA: gpio@fffff400 {
 143                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 144                                 reg = <0xfffff400 0x200>;
 145                                 #gpio-cells = <2>;
 146                                 gpio-controller;
 147                                 clocks = <&pioA_clk>;
 148                         };
 149
 150                         pioB: gpio@fffff600 {
 151                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 152                                 reg = <0xfffff600 0x200>;
 153                                 #gpio-cells = <2>;
 154                                 gpio-controller;
 155                                 clocks = <&pioB_clk>;
 156                         };
 157
 158                         pmc: pmc@fffffc00 {
 159                                 compatible = "atmel,at91sam9x5-pmc";
 160                                 reg = <0xfffffc00 0x200>;
 161                                 #address-cells = <1>;
 162                                 #size-cells = <0>;
 163
 164                                 main: mainck {
 165                                         compatible = "atmel,at91sam9x5-clk-main";
 166                                         #clock-cells = <0>;
 167                                 };
 168
 169                                 plla: pllack {
 170                                         compatible = "microchip,sam9x60-clk-pll";
 171                                         #clock-cells = <0>;
 172                                         clocks = <&main>;
 173                                         reg = <0>;
 174                                         atmel,clk-input-range = <8000000 24000000>;
 175                                         #atmel,pll-clk-output-range-cells = <4>;
 176                                         atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>;
 177                                 };
 178
 179                                 mck: masterck {
 180                                         compatible = "atmel,at91sam9x5-clk-master";
 181                                         #clock-cells = <0>;
 182                                         clocks = <&md_slck>, <&main>, <&plla>;
 183                                         atmel,clk-output-range = <140000000 200000000>;
 184                                         atmel,clk-divisors = <1 2 4 6>;
 185                                 };
 186
 187                                 system: systemck {
 188                                         compatible = "atmel,at91rm9200-clk-system";
 189                                         #address-cells = <1>;
 190                                         #size-cells = <0>;
 191
 192                                         qspick: qspick {
 193                                                 #clock-cells = <0>;
 194                                                 reg = <19>;
 195                                                 clocks = <&mck>;
 196                                         };
 197                                 };
 198
 199                                 periph: periphck {
 200                                         compatible = "microchip,sam9x60-clk-peripheral";
 201                                         #address-cells = <1>;
 202                                         #size-cells = <0>;
 203                                         clocks = <&mck>;
 204
 205                                         pioA_clk: pioA_clk {
 206                                                 #clock-cells = <0>;
 207                                                 reg = <2>;
 208                                         };
 209
 210                                         pioB_clk: pioB_clk {
 211                                                 #clock-cells = <0>;
 212                                                 reg = <3>;
 213                                         };
 214
 215                                         sdhci0_clk: sdhci0_clk {
 216                                                 #clock-cells = <0>;
 217                                                 reg = <12>;
 218                                         };
 219
 220                                         dbgu_clk: dbgu_clk {
 221                                                 #clock-cells = <0>;
 222                                                 reg = <47>;
 223                                         };
 224
 225                                         macb0_clk: macb0_clk {
 226                                                 #clock-cells = <0>;
 227                                                 reg = <24>;
 228                                         };
 229
 230                                         qspi_clk: qspi_clk {
 231                                                 #clock-cells = <0>;
 232                                                 reg = <35>;
 233                                         };
 234                                 };
 235
 236                                 generic: gck {
 237                                         compatible = "microchip,sam9x60-clk-generated";
 238                                         #address-cells = <1>;
 239                                         #size-cells = <0>;
 240                                         clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>;
 241
 242                                         sdhci0_gclk: sdhci0_gclk {
 243                                                 #clock-cells = <0>;
 244                                                 reg = <12>;
 245                                         };
 246                                 };
 247                         };
 248
 249                         pit: timer@fffffe40 {
 250                                 compatible = "atmel,at91sam9260-pit";
 251                                 reg = <0xfffffe40 0x10>;
 252                                 clocks = <&mck>;
 253                         };
 254
 255                         slowckc: sckc@fffffe50 {
 256                                 compatible = "atmel,at91sam9x5-sckc";
 257                                 reg = <0xfffffe50 0x4>;
 258
 259                                 slow_osc: slow_osc {
 260                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
 261                                         #clock-cells = <0>;
 262                                         clocks = <&slow_xtal>;
 263                                 };
 264
 265                                 slow_rc_osc: slow_rc_osc {
 266                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
 267                                         #clock-cells = <0>;
 268                                         clock-frequency = <32768>;
 269                                 };
 270
 271                                 td_slck: td_slck {
 272                                         compatible = "atmel,at91sam9x5-clk-slow";
 273                                         #clock-cells = <0>;
 274                                         clocks = <&slow_rc_osc>, <&slow_osc>;
 275                                 };
 276
 277                                 md_slck: md_slck {
 278                                         compatible = "atmel,at91sam9x5-clk-slow";
 279                                         #clock-cells = <0>;
 280                                         clocks = <&slow_rc_osc>;
 281                                 };
 282                         };
 283                 };
 284         };
 285 };