1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
5 * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
10 #include "skeleton.dtsi"
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
18 model = "Microchip SAM9X60 SoC";
19 compatible = "microchip,sam9x60";
30 slow_xtal: slow_xtal {
31 compatible = "fixed-clock";
33 clock-frequency = <0>;
36 main_xtal: main_xtal {
37 compatible = "fixed-clock";
39 clock-frequency = <0>;
44 compatible = "simple-bus";
49 sdhci0: sdhci-host@80000000 {
50 compatible = "microchip,sam9x60-sdhci";
51 reg = <0x80000000 0x300>;
52 clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
53 clock-names = "hclock", "multclk", "baseclk";
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_sdhci0>;
60 compatible = "simple-bus";
66 compatible = "microchip,sam9x60-qspi";
67 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
68 reg-names = "qspi_base", "qspi_mmap";
69 clocks = <&qspi_clk>, <&qspick>;
70 clock-names = "pclk", "qspick";
76 flx0: flexcom@f801c600 {
77 compatible = "atmel,sama5d2-flexcom";
78 reg = <0xf801c000 0x200>;
82 ranges = <0x0 0xf801c000 0x800>;
86 macb0: ethernet@f802c000 {
87 compatible = "cdns,sam9x60-macb", "cdns,macb";
88 reg = <0xf802c000 0x100>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_macb0_rmii>;
91 clock-names = "hclk", "pclk";
92 clocks = <&macb0_clk>, <&macb0_clk>;
96 dbgu: serial@fffff200 {
97 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
98 reg = <0xfffff200 0x200>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_dbgu>;
101 clocks = <&dbgu_clk>;
102 clock-names = "usart";
106 #address-cells = <1>;
108 compatible = "microchip,sam9x60-pinctrl", "simple-bus";
109 ranges = <0xfffff400 0xfffff400 0x800>;
110 reg = <0xfffff400 0x200 /* pioA */
111 0xfffff600 0x200 /* pioB */
112 0xfffff800 0x200 /* pioC */
113 0xfffffa00 0x200>; /* pioD */
115 /* shared pinctrl settings */
117 pinctrl_dbgu: dbgu-0 {
119 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
120 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
125 pinctrl_macb0_rmii: macb0_rmii-0 {
127 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
128 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
129 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
130 AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
131 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
132 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
133 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
134 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
135 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
136 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
141 pinctrl_sdhci0: sdhci0 {
143 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT /* PA17 CK periph A with pullup */
144 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 CMD periph A with pullup */
145 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA15 DAT0 periph A */
146 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 DAT1 periph A with pullup */
147 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 DAT2 periph A with pullup */
148 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 DAT3 periph A with pullup */
153 pioA: gpio@fffff400 {
154 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
155 reg = <0xfffff400 0x200>;
158 clocks = <&pioA_clk>;
161 pioB: gpio@fffff600 {
162 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
163 reg = <0xfffff600 0x200>;
166 clocks = <&pioB_clk>;
169 pioD: gpio@fffffa00 {
170 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
171 reg = <0xfffffa00 0x200>;
174 clocks = <&pioD_clk>;
178 compatible = "atmel,at91sam9x5-pmc";
179 reg = <0xfffffc00 0x200>;
180 #address-cells = <1>;
184 compatible = "atmel,at91sam9x5-clk-main";
189 compatible = "microchip,sam9x60-clk-pll";
193 atmel,clk-input-range = <8000000 24000000>;
194 #atmel,pll-clk-output-range-cells = <4>;
195 atmel,pll-clk-output-ranges = <140000000 1200000000 0 0>;
199 compatible = "atmel,at91sam9x5-clk-master";
201 clocks = <&md_slck>, <&main>, <&plla>;
202 atmel,clk-output-range = <140000000 200000000>;
203 atmel,clk-divisors = <1 2 4 6>;
207 compatible = "atmel,at91rm9200-clk-system";
208 #address-cells = <1>;
219 compatible = "microchip,sam9x60-clk-peripheral";
220 #address-cells = <1>;
244 sdhci0_clk: sdhci0_clk {
254 macb0_clk: macb0_clk {
266 compatible = "microchip,sam9x60-clk-generated";
267 #address-cells = <1>;
269 clocks = <&md_slck>, <&td_slck>, <&main>, <&mck>, <&plla>;
271 sdhci0_gclk: sdhci0_gclk {
278 pit: timer@fffffe40 {
279 compatible = "atmel,at91sam9260-pit";
280 reg = <0xfffffe40 0x10>;
284 slowckc: sckc@fffffe50 {
285 compatible = "atmel,at91sam9x5-sckc";
286 reg = <0xfffffe50 0x4>;
289 compatible = "atmel,at91sam9x5-clk-slow-osc";
291 clocks = <&slow_xtal>;
294 slow_rc_osc: slow_rc_osc {
295 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
297 clock-frequency = <32768>;
301 compatible = "atmel,at91sam9x5-clk-slow";
303 clocks = <&slow_rc_osc>, <&slow_osc>;
307 compatible = "atmel,at91sam9x5-clk-slow";
309 clocks = <&slow_rc_osc>;
315 onewire_tm: onewire {
316 compatible = "w1-gpio";