2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/rv1108-cru.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
16 compatible = "rockchip,rv1108";
18 interrupt-parent = <&gic>;
33 compatible = "arm,cortex-a7";
39 compatible = "arm,cortex-a7-pmu";
40 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
44 compatible = "arm,armv7-timer";
45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
46 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
47 clock-frequency = <24000000>;
51 compatible = "fixed-clock";
52 clock-frequency = <24000000>;
53 clock-output-names = "xin24m";
58 compatible = "simple-bus";
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0x102a0000 0x4000>;
66 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
68 arm,pl330-broken-no-flushp;
69 clocks = <&cru ACLK_DMAC>;
70 clock-names = "apb_pclk";
75 compatible = "mmio-sram";
76 reg = <0x10080000 0x2000>;
79 ranges = <0 0x10080000 0x2000>;
82 uart2: serial@10210000 {
83 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
84 reg = <0x10210000 0x100>;
85 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
88 clock-frequency = <24000000>;
89 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
90 clock-names = "baudclk", "apb_pclk";
91 pinctrl-names = "default";
92 pinctrl-0 = <&uart2m0_xfer>;
96 uart1: serial@10220000 {
97 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
98 reg = <0x10220000 0x100>;
99 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
102 clock-frequency = <24000000>;
103 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
104 clock-names = "baudclk", "apb_pclk";
105 pinctrl-names = "default";
106 pinctrl-0 = <&uart1_xfer>;
110 uart0: serial@10230000 {
111 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
112 reg = <0x10230000 0x100>;
113 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
116 clock-frequency = <24000000>;
117 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
118 clock-names = "baudclk", "apb_pclk";
119 pinctrl-names = "default";
120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
124 grf: syscon@10300000 {
125 compatible = "rockchip,rv1108-grf", "syscon";
126 reg = <0x10300000 0x1000>;
129 pmugrf: syscon@20060000 {
130 compatible = "rockchip,rv1108-pmugrf", "syscon";
131 reg = <0x20060000 0x1000>;
134 cru: clock-controller@20200000 {
135 compatible = "rockchip,rv1108-cru";
136 reg = <0x20200000 0x1000>;
137 rockchip,grf = <&grf>;
142 emmc: dwmmc@30110000 {
143 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
144 clock-freq-min-max = <400000 150000000>;
145 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
146 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
147 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
148 fifo-depth = <0x100>;
149 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
150 reg = <0x30110000 0x4000>;
154 sdio: dwmmc@30120000 {
155 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
156 clock-freq-min-max = <400000 150000000>;
157 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
158 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
159 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
160 fifo-depth = <0x100>;
161 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
162 reg = <0x30120000 0x4000>;
166 sdmmc: dwmmc@30130000 {
167 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
168 clock-freq-min-max = <400000 100000000>;
169 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
170 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
171 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
172 fifo-depth = <0x100>;
173 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
174 reg = <0x30130000 0x4000>;
178 usb_host_ehci: usb@30140000 {
179 compatible = "generic-ehci";
180 reg = <0x30140000 0x20000>;
181 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
185 usb_host_ohci: usb@30160000 {
186 compatible = "generic-ohci";
187 reg = <0x30160000 0x20000>;
188 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
192 usb20_otg: usb@30180000 {
193 compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
195 reg = <0x30180000 0x40000>;
196 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
203 compatible = "rockchip,sfc";
204 reg = <0x301c0000 0x200>;
205 #address-cells = <1>;
207 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
209 clock-names = "clk_sfc", "hclk_sfc";
210 pinctrl-0 = <&sfc_pins>;
211 pinctrl-names = "default";
215 gmac: ethernet@30200000 {
216 compatible = "rockchip,rv1108-gmac";
217 reg = <0x30200000 0x10000>;
218 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
219 interrupt-names = "macirq";
220 rockchip,grf = <&grf>;
221 clocks = <&cru SCLK_MAC>,
222 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
223 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
224 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
225 clock-names = "stmmaceth",
226 "mac_clk_rx", "mac_clk_tx",
227 "clk_mac_ref", "clk_mac_refout",
228 "aclk_mac", "pclk_mac";
229 pinctrl-names = "default";
230 pinctrl-0 = <&rmii_pins>;
236 gic: interrupt-controller@32010000 {
237 compatible = "arm,gic-400";
238 interrupt-controller;
239 #interrupt-cells = <3>;
240 #address-cells = <0>;
242 reg = <0x32011000 0x1000>,
246 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
250 compatible = "rockchip,rv1108-pinctrl";
251 rockchip,grf = <&grf>;
252 rockchip,pmu = <&pmugrf>;
253 #address-cells = <1>;
257 gpio0: gpio0@20030000 {
258 compatible = "rockchip,gpio-bank";
259 reg = <0x20030000 0x100>;
260 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
266 interrupt-controller;
267 #interrupt-cells = <2>;
270 gpio1: gpio1@10310000 {
271 compatible = "rockchip,gpio-bank";
272 reg = <0x10310000 0x100>;
273 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
283 gpio2: gpio2@10320000 {
284 compatible = "rockchip,gpio-bank";
285 reg = <0x10320000 0x100>;
286 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
292 interrupt-controller;
293 #interrupt-cells = <2>;
296 gpio3: gpio3@10330000 {
297 compatible = "rockchip,gpio-bank";
298 reg = <0x10330000 0x100>;
299 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
309 pcfg_pull_up: pcfg-pull-up {
313 pcfg_pull_down: pcfg-pull-down {
317 pcfg_pull_none: pcfg-pull-none {
321 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
322 drive-strength = <8>;
325 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
326 drive-strength = <12>;
329 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
331 drive-strength = <8>;
334 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
335 drive-strength = <4>;
338 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
340 drive-strength = <4>;
343 pcfg_output_high: pcfg-output-high {
347 pcfg_output_low: pcfg-output-low {
351 pcfg_input_high: pcfg-input-high {
357 rmii_pins: rmii-pins {
358 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
359 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
360 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
361 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
362 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
363 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
364 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
365 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
366 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
367 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
372 i2c1_xfer: i2c1-xfer {
373 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
374 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
379 i2c2m1_xfer: i2c2m1-xfer {
380 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
381 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
384 i2c2m1_gpio: i2c2m1-gpio {
385 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
386 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
391 i2c2m05v_xfer: i2c2m05v-xfer {
392 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
393 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
396 i2c2m05v_gpio: i2c2m05v-gpio {
397 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
398 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
403 i2c3_xfer: i2c3-xfer {
404 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
405 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
411 rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>,
412 <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>,
413 <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,
414 <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>,
415 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
416 <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>;
421 sdmmc_clk: sdmmc-clk {
422 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
425 sdmmc_cmd: sdmmc-cmd {
426 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
430 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
433 sdmmc_bus1: sdmmc-bus1 {
434 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
437 sdmmc_bus4: sdmmc-bus4 {
438 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
439 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
440 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
441 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
446 uart0_xfer: uart0-xfer {
447 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
448 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
451 uart0_cts: uart0-cts {
452 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
455 uart0_rts: uart0-rts {
456 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
459 uart0_rts_gpio: uart0-rts-gpio {
460 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
465 uart1_xfer: uart1-xfer {
466 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
467 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
470 uart1_cts: uart1-cts {
471 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
474 uart01rts: uart1-rts {
475 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
480 uart2m0_xfer: uart2m0-xfer {
481 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
482 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
487 uart2m1_xfer: uart2m1-xfer {
488 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
489 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
494 uart2_5v_cts: uart2_5v-cts {
495 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
498 uart2_5v_rts: uart2_5v-rts {
499 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;