arch/arm/dts/rv1108.dtsi

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/clock/rv1108-cru.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15
  16         compatible = "rockchip,rv1108";
  17
  18         interrupt-parent = <&gic>;
  19
  20         aliases {
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24                 spi0    = &sfc;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu0: cpu@f00 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf00>;
  35                 };
  36         };
  37
  38         arm-pmu {
  39                 compatible = "arm,cortex-a7-pmu";
  40                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
  41         };
  42
  43         timer {
  44                 compatible = "arm,armv7-timer";
  45                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
  46                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
  47                 clock-frequency = <24000000>;
  48         };
  49
  50         xin24m: oscillator {
  51                 compatible = "fixed-clock";
  52                 clock-frequency = <24000000>;
  53                 clock-output-names = "xin24m";
  54                 #clock-cells = <0>;
  55         };
  56
  57         amba {
  58                 compatible = "simple-bus";
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 pdma: pdma@102a0000 {
  64                         compatible = "arm,pl330", "arm,primecell";
  65                         reg = <0x102a0000 0x4000>;
  66                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
  67                         #dma-cells = <1>;
  68                         arm,pl330-broken-no-flushp;
  69                         clocks = <&cru ACLK_DMAC>;
  70                         clock-names = "apb_pclk";
  71                 };
  72         };
  73
  74         bus_intmem@10080000 {
  75                 compatible = "mmio-sram";
  76                 reg = <0x10080000 0x2000>;
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 ranges = <0 0x10080000 0x2000>;
  80         };
  81
  82         uart2: serial@10210000 {
  83                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
  84                 reg = <0x10210000 0x100>;
  85                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  86                 reg-shift = <2>;
  87                 reg-io-width = <4>;
  88                 clock-frequency = <24000000>;
  89                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
  90                 clock-names = "baudclk", "apb_pclk";
  91                 pinctrl-names = "default";
  92                 pinctrl-0 = <&uart2m0_xfer>;
  93                 status = "disabled";
  94         };
  95
  96         uart1: serial@10220000 {
  97                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
  98                 reg = <0x10220000 0x100>;
  99                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 100                 reg-shift = <2>;
 101                 reg-io-width = <4>;
 102                 clock-frequency = <24000000>;
 103                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 104                 clock-names = "baudclk", "apb_pclk";
 105                 pinctrl-names = "default";
 106                 pinctrl-0 = <&uart1_xfer>;
 107                 status = "disabled";
 108         };
 109
 110         uart0: serial@10230000 {
 111                 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
 112                 reg = <0x10230000 0x100>;
 113                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 114                 reg-shift = <2>;
 115                 reg-io-width = <4>;
 116                 clock-frequency = <24000000>;
 117                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 118                 clock-names = "baudclk", "apb_pclk";
 119                 pinctrl-names = "default";
 120                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 121                 status = "disabled";
 122         };
 123
 124         grf: syscon@10300000 {
 125                 compatible = "rockchip,rv1108-grf", "syscon";
 126                 reg = <0x10300000 0x1000>;
 127         };
 128
 129         saradc: saradc@1038c000 {
 130                 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
 131                 reg = <0x1038c000 0x100>;
 132                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 133                 #io-channel-cells = <1>;
 134                 clock-frequency = <1000000>;
 135                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 136                 clock-names = "saradc", "apb_pclk";
 137                 status = "disabled";
 138         };
 139
 140         pmugrf: syscon@20060000 {
 141                 compatible = "rockchip,rv1108-pmugrf", "syscon";
 142                 reg = <0x20060000 0x1000>;
 143         };
 144
 145         cru: clock-controller@20200000 {
 146                 compatible = "rockchip,rv1108-cru";
 147                 reg = <0x20200000 0x1000>;
 148                 rockchip,grf = <&grf>;
 149                 #clock-cells = <1>;
 150                 #reset-cells = <1>;
 151         };
 152
 153         emmc: dwmmc@30110000 {
 154                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 155                 clock-freq-min-max = <400000 150000000>;
 156                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 157                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 158                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 159                 fifo-depth = <0x100>;
 160                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 161                 reg = <0x30110000 0x4000>;
 162                 status = "disabled";
 163         };
 164
 165         sdio: dwmmc@30120000 {
 166                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 167                 clock-freq-min-max = <400000 150000000>;
 168                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 169                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 170                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 171                 fifo-depth = <0x100>;
 172                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 173                 reg = <0x30120000 0x4000>;
 174                 status = "disabled";
 175         };
 176
 177         sdmmc: dwmmc@30130000 {
 178                 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
 179                 clock-freq-min-max = <400000 100000000>;
 180                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 181                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 182                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 183                 fifo-depth = <0x100>;
 184                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 185                 reg = <0x30130000 0x4000>;
 186                 status = "disabled";
 187         };
 188
 189         usb_host_ehci: usb@30140000 {
 190                 compatible = "generic-ehci";
 191                 reg = <0x30140000 0x20000>;
 192                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 193                 status = "disabled";
 194         };
 195
 196         usb_host_ohci: usb@30160000 {
 197                 compatible = "generic-ohci";
 198                 reg = <0x30160000 0x20000>;
 199                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 200                 status = "disabled";
 201         };
 202
 203         usb20_otg: usb@30180000 {
 204                 compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
 205                              "snps,dwc2";
 206                 reg = <0x30180000 0x40000>;
 207                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 208                 hnp-srp-disable;
 209                 dr_mode = "otg";
 210                 status = "disabled";
 211         };
 212
 213         sfc: sfc@301c0000 {
 214                 compatible = "rockchip,sfc";
 215                 reg = <0x301c0000 0x200>;
 216                 #address-cells = <1>;
 217                 #size-cells = <0>;
 218                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 220                 clock-names = "clk_sfc", "hclk_sfc";
 221                 pinctrl-0 = <&sfc_pins>;
 222                 pinctrl-names = "default";
 223                 status = "disabled";
 224         };
 225
 226         gmac: ethernet@30200000 {
 227                 compatible = "rockchip,rv1108-gmac";
 228                 reg = <0x30200000 0x10000>;
 229                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 230                 interrupt-names = "macirq";
 231                 rockchip,grf = <&grf>;
 232                 clocks = <&cru SCLK_MAC>,
 233                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 234                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 235                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 236                 clock-names = "stmmaceth",
 237                         "mac_clk_rx", "mac_clk_tx",
 238                         "clk_mac_ref", "clk_mac_refout",
 239                         "aclk_mac", "pclk_mac";
 240                 pinctrl-names = "default";
 241                 pinctrl-0 = <&rmii_pins>;
 242                 phy-mode = "rmii";
 243                 max-speed = <100>;
 244                 status = "disabled";
 245         };
 246
 247         gic: interrupt-controller@32010000 {
 248                 compatible = "arm,gic-400";
 249                 interrupt-controller;
 250                 #interrupt-cells = <3>;
 251                 #address-cells = <0>;
 252
 253                 reg = <0x32011000 0x1000>,
 254                       <0x32012000 0x1000>,
 255                       <0x32014000 0x2000>,
 256                       <0x32016000 0x2000>;
 257                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 258         };
 259
 260         pinctrl: pinctrl {
 261                 compatible = "rockchip,rv1108-pinctrl";
 262                 rockchip,grf = <&grf>;
 263                 rockchip,pmu = <&pmugrf>;
 264                 #address-cells = <1>;
 265                 #size-cells = <1>;
 266                 ranges;
 267
 268                 gpio0: gpio0@20030000 {
 269                         compatible = "rockchip,gpio-bank";
 270                         reg = <0x20030000 0x100>;
 271                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 272                         clocks = <&xin24m>;
 273
 274                         gpio-controller;
 275                         #gpio-cells = <2>;
 276
 277                         interrupt-controller;
 278                         #interrupt-cells = <2>;
 279                 };
 280
 281                 gpio1: gpio1@10310000 {
 282                         compatible = "rockchip,gpio-bank";
 283                         reg = <0x10310000 0x100>;
 284                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 285                         clocks = <&xin24m>;
 286
 287                         gpio-controller;
 288                         #gpio-cells = <2>;
 289
 290                         interrupt-controller;
 291                         #interrupt-cells = <2>;
 292                 };
 293
 294                 gpio2: gpio2@10320000 {
 295                         compatible = "rockchip,gpio-bank";
 296                         reg = <0x10320000 0x100>;
 297                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 298                         clocks = <&xin24m>;
 299
 300                         gpio-controller;
 301                         #gpio-cells = <2>;
 302
 303                         interrupt-controller;
 304                         #interrupt-cells = <2>;
 305                 };
 306
 307                 gpio3: gpio3@10330000 {
 308                         compatible = "rockchip,gpio-bank";
 309                         reg = <0x10330000 0x100>;
 310                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 311                         clocks = <&xin24m>;
 312
 313                         gpio-controller;
 314                         #gpio-cells = <2>;
 315
 316                         interrupt-controller;
 317                         #interrupt-cells = <2>;
 318                 };
 319
 320                 pcfg_pull_up: pcfg-pull-up {
 321                         bias-pull-up;
 322                 };
 323
 324                 pcfg_pull_down: pcfg-pull-down {
 325                         bias-pull-down;
 326                 };
 327
 328                 pcfg_pull_none: pcfg-pull-none {
 329                         bias-disable;
 330                 };
 331
 332                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 333                         drive-strength = <8>;
 334                 };
 335
 336                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 337                         drive-strength = <12>;
 338                 };
 339
 340                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 341                         bias-pull-up;
 342                         drive-strength = <8>;
 343                 };
 344
 345                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
 346                         drive-strength = <4>;
 347                 };
 348
 349                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
 350                         bias-pull-up;
 351                         drive-strength = <4>;
 352                 };
 353
 354                 pcfg_output_high: pcfg-output-high {
 355                         output-high;
 356                 };
 357
 358                 pcfg_output_low: pcfg-output-low {
 359                         output-low;
 360                 };
 361
 362                 pcfg_input_high: pcfg-input-high {
 363                         bias-pull-up;
 364                         input-enable;
 365                 };
 366
 367                 gmac {
 368                         rmii_pins: rmii-pins {
 369                                 rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
 370                                                 <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>,
 371                                                 <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
 372                                                 <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
 373                                                 <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
 374                                                 <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>,
 375                                                 <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>,
 376                                                 <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>,
 377                                                 <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>,
 378                                                 <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>;
 379                         };
 380                 };
 381
 382                 i2c1 {
 383                         i2c1_xfer: i2c1-xfer {
 384                                 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
 385                                                 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
 386                         };
 387                 };
 388
 389                 i2c2m1 {
 390                         i2c2m1_xfer: i2c2m1-xfer {
 391                                 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
 392                                                 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
 393                         };
 394
 395                         i2c2m1_gpio: i2c2m1-gpio {
 396                                 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
 397                                                 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
 398                         };
 399                 };
 400
 401                 i2c2m05v {
 402                         i2c2m05v_xfer: i2c2m05v-xfer {
 403                                 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
 404                                                 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
 405                         };
 406
 407                         i2c2m05v_gpio: i2c2m05v-gpio {
 408                                 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
 409                                                 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
 410                         };
 411                 };
 412
 413                 i2c3 {
 414                         i2c3_xfer: i2c3-xfer {
 415                                 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
 416                                                 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
 417                         };
 418                 };
 419
 420                 sfc {
 421                         sfc_pins: sfc-pins {
 422                                 rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>,
 423                                                 <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>,
 424                                                 <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>,
 425                                                 <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>,
 426                                                 <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>,
 427                                                 <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>;
 428                         };
 429                 };
 430
 431                 sdmmc {
 432                         sdmmc_clk: sdmmc-clk {
 433                                 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
 434                         };
 435
 436                         sdmmc_cmd: sdmmc-cmd {
 437                                 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 438                         };
 439
 440                         sdmmc_cd: sdmmc-cd {
 441                                 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 442                         };
 443
 444                         sdmmc_bus1: sdmmc-bus1 {
 445                                 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 446                         };
 447
 448                         sdmmc_bus4: sdmmc-bus4 {
 449                                 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 450                                                 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 451                                                 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 452                                                 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 453                         };
 454                 };
 455
 456                 uart0 {
 457                         uart0_xfer: uart0-xfer {
 458                                 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
 459                                                 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
 460                         };
 461
 462                         uart0_cts: uart0-cts {
 463                                 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
 464                         };
 465
 466                         uart0_rts: uart0-rts {
 467                                 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
 468                         };
 469
 470                         uart0_rts_gpio: uart0-rts-gpio {
 471                                 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
 472                         };
 473                 };
 474
 475                 uart1 {
 476                         uart1_xfer: uart1-xfer {
 477                                 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
 478                                                 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
 479                         };
 480
 481                         uart1_cts: uart1-cts {
 482                                 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
 483                         };
 484
 485                         uart01rts: uart1-rts {
 486                                 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 487                         };
 488                 };
 489
 490                 uart2m0 {
 491                         uart2m0_xfer: uart2m0-xfer {
 492                                 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
 493                                                 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 494                         };
 495                 };
 496
 497                 uart2m1 {
 498                         uart2m1_xfer: uart2m1-xfer {
 499                                 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
 500                                                 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
 501                         };
 502                 };
 503
 504                 uart2_5v {
 505                         uart2_5v_cts: uart2_5v-cts {
 506                                 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
 507                         };
 508
 509                         uart2_5v_rts: uart2_5v-rts {
 510                                 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
 511                         };
 512                 };
 513         };
 514 };