2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3399-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #define USB_CLASS_HUB 9
15 compatible = "rockchip,rk3399";
17 interrupt-parent = <&gic>;
63 compatible = "arm,cortex-a53", "arm,armv8";
65 enable-method = "psci";
66 #cooling-cells = <2>; /* min followed by max */
67 clocks = <&cru ARMCLKL>;
72 compatible = "arm,cortex-a53", "arm,armv8";
74 enable-method = "psci";
75 clocks = <&cru ARMCLKL>;
80 compatible = "arm,cortex-a53", "arm,armv8";
82 enable-method = "psci";
83 clocks = <&cru ARMCLKL>;
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
91 clocks = <&cru ARMCLKL>;
96 compatible = "arm,cortex-a72", "arm,armv8";
98 enable-method = "psci";
99 #cooling-cells = <2>; /* min followed by max */
100 clocks = <&cru ARMCLKB>;
105 compatible = "arm,cortex-a72", "arm,armv8";
107 enable-method = "psci";
108 clocks = <&cru ARMCLKB>;
113 compatible = "arm,psci-1.0";
118 compatible = "arm,armv8-timer";
119 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
120 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
121 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
122 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
126 compatible = "fixed-clock";
127 clock-frequency = <24000000>;
128 clock-output-names = "xin24m";
133 compatible = "simple-bus";
134 #address-cells = <2>;
138 dmac_bus: dma-controller@ff6d0000 {
139 compatible = "arm,pl330", "arm,primecell";
140 reg = <0x0 0xff6d0000 0x0 0x4000>;
141 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&cru ACLK_DMAC0_PERILP>;
145 clock-names = "apb_pclk";
148 dmac_peri: dma-controller@ff6e0000 {
149 compatible = "arm,pl330", "arm,primecell";
150 reg = <0x0 0xff6e0000 0x0 0x4000>;
151 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&cru ACLK_DMAC1_PERILP>;
155 clock-names = "apb_pclk";
159 sdio0: dwmmc@fe310000 {
160 compatible = "rockchip,rk3399-dw-mshc",
161 "rockchip,rk3288-dw-mshc";
162 reg = <0x0 0xfe310000 0x0 0x4000>;
163 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
164 clock-freq-min-max = <400000 150000000>;
165 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
166 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
167 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
168 fifo-depth = <0x100>;
172 sdmmc: dwmmc@fe320000 {
173 compatible = "rockchip,rk3399-dw-mshc",
174 "rockchip,rk3288-dw-mshc";
175 reg = <0x0 0xfe320000 0x0 0x4000>;
176 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
177 clock-freq-min-max = <400000 150000000>;
178 clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>,
179 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
180 clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
181 pinctrl-names = "default";
182 pinctrl-0 = <&sdmmc_clk>;
183 fifo-depth = <0x100>;
187 sdhci: sdhci@fe330000 {
189 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
190 reg = <0x0 0xfe330000 0x0 0x10000>;
191 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
192 assigned-clocks = <&cru SCLK_EMMC>;
193 assigned-clock-rates = <200000000>;
194 max-frequency = <200000000>;
195 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
196 clock-names = "clk_xin", "clk_ahb";
198 phy-names = "phy_arasan";
202 usb_host0_ehci: usb@fe380000 {
203 compatible = "generic-ehci";
204 reg = <0x0 0xfe380000 0x0 0x20000>;
205 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
207 clock-names = "hclk_host0", "hclk_host0_arb";
211 usb_host0_ohci: usb@fe3a0000 {
212 compatible = "generic-ohci";
213 reg = <0x0 0xfe3a0000 0x0 0x20000>;
214 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
216 clock-names = "hclk_host0", "hclk_host0_arb";
220 usb_host1_ehci: usb@fe3c0000 {
221 compatible = "generic-ehci";
222 reg = <0x0 0xfe3c0000 0x0 0x20000>;
223 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
225 clock-names = "hclk_host1", "hclk_host1_arb";
229 usb_host1_ohci: usb@fe3e0000 {
230 compatible = "generic-ohci";
231 reg = <0x0 0xfe3e0000 0x0 0x20000>;
232 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
234 clock-names = "hclk_host1", "hclk_host1_arb";
238 dwc3_typec0: usb@fe800000 {
239 compatible = "rockchip,rk3399-xhci";
240 reg = <0x0 0xfe800000 0x0 0x100000>;
242 snps,dis-enblslpm-quirk;
243 snps,phyif-utmi-bits = <16>;
244 snps,dis-u2-freeclk-exists-quirk;
245 snps,dis-u2-susphy-quirk;
247 #address-cells = <2>;
250 compatible = "usb-hub";
251 usb,device-class = <USB_CLASS_HUB>;
254 compatible = "rockchip,rk3399-usb3-phy";
255 reg = <0x0 0xff7c0000 0x0 0x40000>;
259 dwc3_typec1: usb@fe900000 {
260 compatible = "rockchip,rk3399-xhci";
261 reg = <0x0 0xfe900000 0x0 0x100000>;
263 snps,dis-enblslpm-quirk;
264 snps,phyif-utmi-bits = <16>;
265 snps,dis-u2-freeclk-exists-quirk;
266 snps,dis-u2-susphy-quirk;
268 #address-cells = <2>;
271 compatible = "usb-hub";
272 usb,device-class = <USB_CLASS_HUB>;
275 compatible = "rockchip,rk3399-usb3-phy";
276 reg = <0x0 0xff800000 0x0 0x40000>;
280 gic: interrupt-controller@fee00000 {
281 compatible = "arm,gic-v3";
282 #interrupt-cells = <3>;
283 #address-cells = <2>;
286 interrupt-controller;
288 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
289 <0x0 0xfef00000 0 0xc0000>, /* GICR */
290 <0x0 0xfff00000 0 0x10000>, /* GICC */
291 <0x0 0xfff10000 0 0x10000>, /* GICH */
292 <0x0 0xfff20000 0 0x10000>; /* GICV */
293 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
294 its: interrupt-controller@fee20000 {
295 compatible = "arm,gic-v3-its";
297 reg = <0x0 0xfee20000 0x0 0x20000>;
301 uart0: serial@ff180000 {
302 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
303 reg = <0x0 0xff180000 0x0 0x100>;
304 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
305 clock-names = "baudclk", "apb_pclk";
306 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&uart0_xfer>;
314 uart1: serial@ff190000 {
315 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
316 reg = <0x0 0xff190000 0x0 0x100>;
317 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
318 clock-names = "baudclk", "apb_pclk";
319 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&uart1_xfer>;
327 uart2: serial@ff1a0000 {
328 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
329 reg = <0x0 0xff1a0000 0x0 0x100>;
330 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
331 clock-names = "baudclk", "apb_pclk";
332 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
333 clock-frequency = <24000000>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&uart2c_xfer>;
341 uart3: serial@ff1b0000 {
342 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
343 reg = <0x0 0xff1b0000 0x0 0x100>;
344 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
345 clock-names = "baudclk", "apb_pclk";
346 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
349 pinctrl-names = "default";
350 pinctrl-0 = <&uart3_xfer>;
355 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
356 reg = <0x0 0xff1c0000 0x0 0x1000>;
357 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
358 clock-names = "spiclk", "apb_pclk";
359 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
362 #address-cells = <1>;
368 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
369 reg = <0x0 0xff1d0000 0x0 0x1000>;
370 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
371 clock-names = "spiclk", "apb_pclk";
372 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
375 #address-cells = <1>;
381 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
382 reg = <0x0 0xff1e0000 0x0 0x1000>;
383 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
384 clock-names = "spiclk", "apb_pclk";
385 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
386 pinctrl-names = "default";
387 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
388 #address-cells = <1>;
394 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
395 reg = <0x0 0xff1f0000 0x0 0x1000>;
396 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
397 clock-names = "spiclk", "apb_pclk";
398 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
401 #address-cells = <1>;
407 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
408 reg = <0x0 0xff200000 0x0 0x1000>;
409 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
410 clock-names = "spiclk", "apb_pclk";
411 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
414 #address-cells = <1>;
419 pmugrf: syscon@ff320000 {
421 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
422 reg = <0x0 0xff320000 0x0 0x1000>;
423 #address-cells = <1>;
426 pmu_io_domains: io-domains {
427 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
432 pmusgrf: syscon@ff330000 {
434 compatible = "rockchip,rk3399-pmusgrf", "syscon";
435 reg = <0x0 0xff330000 0x0 0xe3d4>;
439 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
440 reg = <0x0 0xff350000 0x0 0x1000>;
441 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
442 clock-names = "spiclk", "apb_pclk";
443 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
444 pinctrl-names = "default";
445 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
446 #address-cells = <1>;
451 uart4: serial@ff370000 {
452 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
453 reg = <0x0 0xff370000 0x0 0x100>;
454 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
455 clock-names = "baudclk", "apb_pclk";
456 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&uart4_xfer>;
465 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
466 reg = <0x0 0xff420000 0x0 0x10>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&pwm0_pin>;
470 clocks = <&pmucru PCLK_RKPWM_PMU>;
476 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
477 reg = <0x0 0xff420010 0x0 0x10>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&pwm1_pin>;
481 clocks = <&pmucru PCLK_RKPWM_PMU>;
487 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
488 reg = <0x0 0xff420020 0x0 0x10>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&pwm2_pin>;
492 clocks = <&pmucru PCLK_RKPWM_PMU>;
498 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
499 reg = <0x0 0xff420030 0x0 0x10>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&pwm3a_pin>;
503 clocks = <&pmucru PCLK_RKPWM_PMU>;
508 cic: syscon@ff620000 {
510 compatible = "rockchip,rk3399-cic", "syscon";
511 reg = <0x0 0xff620000 0x0 0x100>;
515 reg = <0x00 0xff630000 0x00 0x4000>;
516 compatible = "rockchip,rk3399-dfi";
517 rockchip,pmu = <&pmugrf>;
518 clocks = <&cru PCLK_DDR_MON>;
519 clock-names = "pclk_ddr_mon";
525 compatible = "rockchip,rk3399-dmc";
526 devfreq-events = <&dfi>;
527 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
528 clocks = <&cru SCLK_DDRCLK>;
529 clock-names = "dmc_clk";
530 reg = <0x0 0xffa80000 0x0 0x0800
531 0x0 0xffa80800 0x0 0x1800
532 0x0 0xffa82000 0x0 0x2000
533 0x0 0xffa84000 0x0 0x1000
534 0x0 0xffa88000 0x0 0x0800
535 0x0 0xffa88800 0x0 0x1800
536 0x0 0xffa8a000 0x0 0x2000
537 0x0 0xffa8c000 0x0 0x1000>;
540 pmucru: pmu-clock-controller@ff750000 {
542 compatible = "rockchip,rk3399-pmucru";
543 reg = <0x0 0xff750000 0x0 0x1000>;
546 assigned-clocks = <&pmucru PLL_PPLL>;
547 assigned-clock-rates = <676000000>;
550 cru: clock-controller@ff760000 {
552 compatible = "rockchip,rk3399-cru";
553 reg = <0x0 0xff760000 0x0 0x1000>;
557 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
559 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
561 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
563 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
564 assigned-clock-rates =
565 <594000000>, <800000000>,
567 <150000000>, <75000000>,
569 <100000000>, <100000000>,
571 <100000000>, <50000000>;
574 grf: syscon@ff770000 {
576 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
577 reg = <0x0 0xff770000 0x0 0x10000>;
578 #address-cells = <1>;
581 io_domains: io-domains {
582 compatible = "rockchip,rk3399-io-voltage-domain";
587 compatible = "rockchip,rk3399-emmc-phy";
595 compatible = "snps,dw-wdt";
596 reg = <0x0 0xff840000 0x0 0x100>;
597 clocks = <&cru PCLK_WDT>;
598 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
602 compatible = "rockchip,rk3399-gmac";
603 reg = <0x0 0xfe300000 0x0 0x10000>;
604 rockchip,grf = <&grf>;
605 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
606 interrupt-names = "macirq";
607 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
608 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
609 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
611 clock-names = "stmmaceth", "mac_clk_rx",
612 "mac_clk_tx", "clk_mac_ref",
613 "clk_mac_refout", "aclk_mac",
615 resets = <&cru SRST_A_GMAC>;
616 reset-names = "stmmaceth";
620 spdif: spdif@ff870000 {
621 compatible = "rockchip,rk3399-spdif";
622 reg = <0x0 0xff870000 0x0 0x1000>;
623 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
624 dmas = <&dmac_bus 7>;
626 clock-names = "mclk", "hclk";
627 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&spdif_bus>;
634 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
635 reg = <0x0 0xff880000 0x0 0x1000>;
636 rockchip,grf = <&grf>;
637 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
638 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
639 dma-names = "tx", "rx";
640 clock-names = "i2s_clk", "i2s_hclk";
641 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&i2s0_8ch_bus>;
648 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
649 reg = <0x0 0xff890000 0x0 0x1000>;
650 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
651 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
652 dma-names = "tx", "rx";
653 clock-names = "i2s_clk", "i2s_hclk";
654 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&i2s1_2ch_bus>;
661 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
662 reg = <0x0 0xff8a0000 0x0 0x1000>;
663 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
664 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
665 dma-names = "tx", "rx";
666 clock-names = "i2s_clk", "i2s_hclk";
667 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
673 compatible = "rockchip,rk3399-pinctrl";
674 rockchip,grf = <&grf>;
675 rockchip,pmu = <&pmugrf>;
676 #address-cells = <2>;
680 gpio0: gpio0@ff720000 {
681 compatible = "rockchip,gpio-bank";
682 reg = <0x0 0xff720000 0x0 0x100>;
683 clocks = <&pmucru PCLK_GPIO0_PMU>;
684 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
689 interrupt-controller;
690 #interrupt-cells = <0x2>;
693 gpio1: gpio1@ff730000 {
694 compatible = "rockchip,gpio-bank";
695 reg = <0x0 0xff730000 0x0 0x100>;
696 clocks = <&pmucru PCLK_GPIO1_PMU>;
697 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
702 interrupt-controller;
703 #interrupt-cells = <0x2>;
706 gpio2: gpio2@ff780000 {
707 compatible = "rockchip,gpio-bank";
708 reg = <0x0 0xff780000 0x0 0x100>;
709 clocks = <&cru PCLK_GPIO2>;
710 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
715 interrupt-controller;
716 #interrupt-cells = <0x2>;
719 gpio3: gpio3@ff788000 {
720 compatible = "rockchip,gpio-bank";
721 reg = <0x0 0xff788000 0x0 0x100>;
722 clocks = <&cru PCLK_GPIO3>;
723 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
728 interrupt-controller;
729 #interrupt-cells = <0x2>;
732 gpio4: gpio4@ff790000 {
733 compatible = "rockchip,gpio-bank";
734 reg = <0x0 0xff790000 0x0 0x100>;
735 clocks = <&cru PCLK_GPIO4>;
736 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
741 interrupt-controller;
742 #interrupt-cells = <0x2>;
745 pcfg_pull_up: pcfg-pull-up {
749 pcfg_pull_down: pcfg-pull-down {
753 pcfg_pull_none: pcfg-pull-none {
757 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
759 drive-strength = <12>;
762 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
764 drive-strength = <8>;
767 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
769 drive-strength = <4>;
772 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
774 drive-strength = <2>;
777 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
779 drive-strength = <12>;
782 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
784 drive-strength = <13>;
788 i2c0_xfer: i2c0-xfer {
790 <1 15 RK_FUNC_2 &pcfg_pull_none>,
791 <1 16 RK_FUNC_2 &pcfg_pull_none>;
796 i2c1_xfer: i2c1-xfer {
798 <4 2 RK_FUNC_1 &pcfg_pull_none>,
799 <4 1 RK_FUNC_1 &pcfg_pull_none>;
804 i2c2_xfer: i2c2-xfer {
806 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
807 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
812 i2c3_xfer: i2c3-xfer {
814 <4 17 RK_FUNC_1 &pcfg_pull_none>,
815 <4 16 RK_FUNC_1 &pcfg_pull_none>;
820 i2c4_xfer: i2c4-xfer {
822 <1 12 RK_FUNC_1 &pcfg_pull_none>,
823 <1 11 RK_FUNC_1 &pcfg_pull_none>;
828 i2c5_xfer: i2c5-xfer {
830 <3 11 RK_FUNC_2 &pcfg_pull_none>,
831 <3 10 RK_FUNC_2 &pcfg_pull_none>;
836 i2c6_xfer: i2c6-xfer {
838 <2 10 RK_FUNC_2 &pcfg_pull_none>,
839 <2 9 RK_FUNC_2 &pcfg_pull_none>;
844 i2c7_xfer: i2c7-xfer {
846 <2 8 RK_FUNC_2 &pcfg_pull_none>,
847 <2 7 RK_FUNC_2 &pcfg_pull_none>;
852 i2c8_xfer: i2c8-xfer {
854 <1 21 RK_FUNC_1 &pcfg_pull_none>,
855 <1 20 RK_FUNC_1 &pcfg_pull_none>;
860 i2s0_8ch_bus: i2s0-8ch-bus {
862 <3 24 RK_FUNC_1 &pcfg_pull_none>,
863 <3 25 RK_FUNC_1 &pcfg_pull_none>,
864 <3 26 RK_FUNC_1 &pcfg_pull_none>,
865 <3 27 RK_FUNC_1 &pcfg_pull_none>,
866 <3 28 RK_FUNC_1 &pcfg_pull_none>,
867 <3 29 RK_FUNC_1 &pcfg_pull_none>,
868 <3 30 RK_FUNC_1 &pcfg_pull_none>,
869 <3 31 RK_FUNC_1 &pcfg_pull_none>,
870 <4 0 RK_FUNC_1 &pcfg_pull_none>;
875 i2s1_2ch_bus: i2s1-2ch-bus {
877 <4 3 RK_FUNC_1 &pcfg_pull_none>,
878 <4 4 RK_FUNC_1 &pcfg_pull_none>,
879 <4 5 RK_FUNC_1 &pcfg_pull_none>,
880 <4 6 RK_FUNC_1 &pcfg_pull_none>,
881 <4 7 RK_FUNC_1 &pcfg_pull_none>;
886 rgmii_pins: rgmii-pins {
889 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
891 <3 14 RK_FUNC_1 &pcfg_pull_none>,
893 <3 13 RK_FUNC_1 &pcfg_pull_none>,
895 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
897 <3 11 RK_FUNC_1 &pcfg_pull_none>,
899 <3 9 RK_FUNC_1 &pcfg_pull_none>,
901 <3 8 RK_FUNC_1 &pcfg_pull_none>,
903 <3 7 RK_FUNC_1 &pcfg_pull_none>,
905 <3 6 RK_FUNC_1 &pcfg_pull_none>,
907 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
909 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
911 <3 3 RK_FUNC_1 &pcfg_pull_none>,
913 <3 2 RK_FUNC_1 &pcfg_pull_none>,
915 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
917 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
922 sdmmc_bus1: sdmmc-bus1 {
924 <4 8 RK_FUNC_1 &pcfg_pull_up>;
927 sdmmc_bus4: sdmmc-bus4 {
929 <4 8 RK_FUNC_1 &pcfg_pull_up>,
930 <4 9 RK_FUNC_1 &pcfg_pull_up>,
931 <4 10 RK_FUNC_1 &pcfg_pull_up>,
932 <4 11 RK_FUNC_1 &pcfg_pull_up>;
935 sdmmc_clk: sdmmc-clk {
937 <4 12 RK_FUNC_1 &pcfg_pull_none>;
940 sdmmc_cmd: sdmmc-cmd {
942 <4 13 RK_FUNC_1 &pcfg_pull_up>;
947 <0 7 RK_FUNC_1 &pcfg_pull_up>;
952 <0 8 RK_FUNC_1 &pcfg_pull_up>;
957 spdif_bus: spdif-bus {
959 <4 21 RK_FUNC_1 &pcfg_pull_none>;
966 <3 6 RK_FUNC_2 &pcfg_pull_up>;
970 <3 7 RK_FUNC_2 &pcfg_pull_up>;
974 <3 8 RK_FUNC_2 &pcfg_pull_up>;
978 <3 5 RK_FUNC_2 &pcfg_pull_up>;
982 <3 4 RK_FUNC_2 &pcfg_pull_up>;
989 <1 9 RK_FUNC_2 &pcfg_pull_up>;
993 <1 10 RK_FUNC_2 &pcfg_pull_up>;
997 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1001 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1006 spi2_clk: spi2-clk {
1008 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1010 spi2_cs0: spi2-cs0 {
1012 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1016 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1020 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1025 spi3_clk: spi3-clk {
1027 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1029 spi3_cs0: spi3-cs0 {
1031 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1035 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1039 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1044 spi4_clk: spi4-clk {
1046 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1048 spi4_cs0: spi4-cs0 {
1050 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1054 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1058 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1063 spi5_clk: spi5-clk {
1065 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1067 spi5_cs0: spi5-cs0 {
1069 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1073 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1077 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1082 uart0_xfer: uart0-xfer {
1084 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1085 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1088 uart0_cts: uart0-cts {
1090 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1093 uart0_rts: uart0-rts {
1095 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1100 uart1_xfer: uart1-xfer {
1102 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1103 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1108 uart2a_xfer: uart2a-xfer {
1110 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1111 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1116 uart2b_xfer: uart2b-xfer {
1118 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1119 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1124 uart2c_xfer: uart2c-xfer {
1126 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1127 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1132 uart3_xfer: uart3-xfer {
1134 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1135 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1138 uart3_cts: uart3-cts {
1140 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1143 uart3_rts: uart3-rts {
1145 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1150 uart4_xfer: uart4-xfer {
1152 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1153 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1158 uarthdcp_xfer: uarthdcp-xfer {
1160 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1161 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1166 pwm0_pin: pwm0-pin {
1168 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1171 vop0_pwm_pin: vop0-pwm-pin {
1173 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1178 pwm1_pin: pwm1-pin {
1180 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1183 vop1_pwm_pin: vop1-pwm-pin {
1185 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1190 pwm2_pin: pwm2-pin {
1192 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1197 pwm3a_pin: pwm3a-pin {
1199 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1204 pwm3b_pin: pwm3b-pin {
1206 <1 14 RK_FUNC_1 &pcfg_pull_none>;