1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
4 * Copyright (c) 2019 Markus Reichl <m.reichl@fivetechno.de>
8 #include "rk3399-roc-pc.dtsi"
11 model = "Firefly ROC-RK3399-PC Mezzanine Board";
12 compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
14 vcc3v3_ngff: vcc3v3-ngff {
15 compatible = "regulator-fixed";
16 regulator-name = "vcc3v3_ngff";
18 gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&vcc3v3_ngff_en>;
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
25 vin-supply = <&dc_12v>;
28 vcc3v3_pcie: vcc3v3-pcie {
29 compatible = "regulator-fixed";
30 regulator-name = "vcc3v3_pcie";
32 gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
33 pinctrl-names = "default";
34 pinctrl-0 = <&vcc3v3_pcie_en>;
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 vin-supply = <&dc_12v>;
46 ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&pcie_perst>;
50 vpcie3v3-supply = <&vcc3v3_pcie>;
51 vpcie1v8-supply = <&vcc1v8_pmu>;
52 vpcie0v9-supply = <&vcca_0v9>;
58 vcc3v3_ngff_en: vcc3v3-ngff-en {
59 rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
64 vcc3v3_pcie_en: vcc3v3-pcie-en {
65 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
68 pcie_perst: pcie-perst {
69 rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
78 keep-power-in-suspend;
79 mmc-pwrseq = <&sdio_pwrseq>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
84 vmmc-supply = <&vcc3v3_ngff>;
85 vqmmc-supply = <&vcc_1v8>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;