arm64: zynqmp: Add reset-controller support in serdes driver
[oweals/u-boot.git] / arch / arm / dts / rk3368.dtsi
1 /*
2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
3  *
4  * This file is dual-licensed: you can use it either under the terms
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8  *
9  *  a) This library is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
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12  *     License, or (at your option) any later version.
13  *
14  *     This library is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
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20  *
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34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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41  */
42
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/thermal/thermal.h>
49 #include <dt-bindings/memory/rk3368-dmc.h>
50
51 / {
52         compatible = "rockchip,rk3368";
53         interrupt-parent = <&gic>;
54         #address-cells = <2>;
55         #size-cells = <2>;
56
57         aliases {
58                 ethernet0 = &gmac;
59                 i2c0 = &i2c0;
60                 i2c1 = &i2c1;
61                 i2c2 = &i2c2;
62                 i2c3 = &i2c3;
63                 i2c4 = &i2c4;
64                 i2c5 = &i2c5;
65                 serial0 = &uart0;
66                 serial1 = &uart1;
67                 serial2 = &uart2;
68                 serial3 = &uart3;
69                 serial4 = &uart4;
70                 spi0 = &spi0;
71                 spi1 = &spi1;
72                 spi2 = &spi2;
73         };
74
75         cpus {
76                 #address-cells = <0x2>;
77                 #size-cells = <0x0>;
78
79                 cpu-map {
80                         cluster0 {
81                                 core0 {
82                                         cpu = <&cpu_b0>;
83                                 };
84                                 core1 {
85                                         cpu = <&cpu_b1>;
86                                 };
87                                 core2 {
88                                         cpu = <&cpu_b2>;
89                                 };
90                                 core3 {
91                                         cpu = <&cpu_b3>;
92                                 };
93                         };
94
95                         cluster1 {
96                                 core0 {
97                                         cpu = <&cpu_l0>;
98                                 };
99                                 core1 {
100                                         cpu = <&cpu_l1>;
101                                 };
102                                 core2 {
103                                         cpu = <&cpu_l2>;
104                                 };
105                                 core3 {
106                                         cpu = <&cpu_l3>;
107                                 };
108                         };
109                 };
110
111                 idle-states {
112                         entry-method = "psci";
113
114                         cpu_sleep: cpu-sleep-0 {
115                                 compatible = "arm,idle-state";
116                                 arm,psci-suspend-param = <0x1010000>;
117                                 entry-latency-us = <0x3fffffff>;
118                                 exit-latency-us = <0x40000000>;
119                                 min-residency-us = <0xffffffff>;
120                         };
121                 };
122
123                 cpu_l0: cpu@0 {
124                         device_type = "cpu";
125                         compatible = "arm,cortex-a53", "arm,armv8";
126                         reg = <0x0 0x0>;
127                         cpu-idle-states = <&cpu_sleep>;
128                         enable-method = "psci";
129
130                         #cooling-cells = <2>; /* min followed by max */
131                 };
132
133                 cpu_l1: cpu@1 {
134                         device_type = "cpu";
135                         compatible = "arm,cortex-a53", "arm,armv8";
136                         reg = <0x0 0x1>;
137                         cpu-idle-states = <&cpu_sleep>;
138                         enable-method = "psci";
139                 };
140
141                 cpu_l2: cpu@2 {
142                         device_type = "cpu";
143                         compatible = "arm,cortex-a53", "arm,armv8";
144                         reg = <0x0 0x2>;
145                         cpu-idle-states = <&cpu_sleep>;
146                         enable-method = "psci";
147                 };
148
149                 cpu_l3: cpu@3 {
150                         device_type = "cpu";
151                         compatible = "arm,cortex-a53", "arm,armv8";
152                         reg = <0x0 0x3>;
153                         cpu-idle-states = <&cpu_sleep>;
154                         enable-method = "psci";
155                 };
156
157                 cpu_b0: cpu@100 {
158                         device_type = "cpu";
159                         compatible = "arm,cortex-a53", "arm,armv8";
160                         reg = <0x0 0x100>;
161                         cpu-idle-states = <&cpu_sleep>;
162                         enable-method = "psci";
163
164                         #cooling-cells = <2>; /* min followed by max */
165                 };
166
167                 cpu_b1: cpu@101 {
168                         device_type = "cpu";
169                         compatible = "arm,cortex-a53", "arm,armv8";
170                         reg = <0x0 0x101>;
171                         cpu-idle-states = <&cpu_sleep>;
172                         enable-method = "psci";
173                 };
174
175                 cpu_b2: cpu@102 {
176                         device_type = "cpu";
177                         compatible = "arm,cortex-a53", "arm,armv8";
178                         reg = <0x0 0x102>;
179                         cpu-idle-states = <&cpu_sleep>;
180                         enable-method = "psci";
181                 };
182
183                 cpu_b3: cpu@103 {
184                         device_type = "cpu";
185                         compatible = "arm,cortex-a53", "arm,armv8";
186                         reg = <0x0 0x103>;
187                         cpu-idle-states = <&cpu_sleep>;
188                         enable-method = "psci";
189                 };
190         };
191
192         arm-pmu {
193                 compatible = "arm,armv8-pmuv3";
194                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
195                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
196                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
197                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
198                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
199                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
200                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
201                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
202                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
203                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
204                                      <&cpu_b2>, <&cpu_b3>;
205         };
206
207         psci {
208                 compatible = "arm,psci-0.2";
209                 method = "smc";
210         };
211
212         timer {
213                 compatible = "arm,armv8-timer";
214                 interrupts = <GIC_PPI 13
215                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
216                              <GIC_PPI 14
217                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
218                              <GIC_PPI 11
219                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
220                              <GIC_PPI 10
221                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
222         };
223
224         xin24m: oscillator {
225                 compatible = "fixed-clock";
226                 clock-frequency = <24000000>;
227                 clock-output-names = "xin24m";
228                 #clock-cells = <0>;
229         };
230
231         dmc: dmc@ff610000 {
232                 compatible = "rockchip,rk3368-dmc", "syscon";
233                 rockchip,cru = <&cru>;
234                 rockchip,grf = <&grf>;
235                 rockchip,msch = <&service_msch>;
236                 reg = <0 0xff610000 0 0x400
237                        0 0xff620000 0 0x400>;
238         };
239
240         service_msch: syscon@ffac0000 {
241                 compatible = "rockchip,rk3368-msch", "syscon";
242                 reg = <0x0 0xffac0000 0x0 0x2000>;
243                 status = "okay";
244         };
245
246         sdmmc: dwmmc@ff0c0000 {
247                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
248                 reg = <0x0 0xff0c0000 0x0 0x4000>;
249                 clock-freq-min-max = <400000 150000000>;
250                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
251                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
252                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
253                 fifo-depth = <0x100>;
254                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
255                 status = "disabled";
256         };
257
258         sdio0: dwmmc@ff0d0000 {
259                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
260                 reg = <0x0 0xff0d0000 0x0 0x4000>;
261                 clock-freq-min-max = <400000 150000000>;
262                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
263                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
264                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
265                 fifo-depth = <0x100>;
266                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
267                 status = "disabled";
268         };
269
270         emmc: dwmmc@ff0f0000 {
271                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
272                 reg = <0x0 0xff0f0000 0x0 0x4000>;
273                 clock-freq-min-max = <400000 150000000>;
274                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
275                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
276                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
277                 fifo-depth = <0x100>;
278                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
279                 status = "disabled";
280         };
281
282         saradc: saradc@ff100000 {
283                 compatible = "rockchip,saradc";
284                 reg = <0x0 0xff100000 0x0 0x100>;
285                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
286                 #io-channel-cells = <1>;
287                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
288                 clock-names = "saradc", "apb_pclk";
289                 status = "disabled";
290         };
291
292         spi0: spi@ff110000 {
293                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
294                 reg = <0x0 0xff110000 0x0 0x1000>;
295                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
296                 clock-names = "spiclk", "apb_pclk";
297                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
298                 pinctrl-names = "default";
299                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
300                 #address-cells = <1>;
301                 #size-cells = <0>;
302                 status = "disabled";
303         };
304
305         spi1: spi@ff120000 {
306                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
307                 reg = <0x0 0xff120000 0x0 0x1000>;
308                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
309                 clock-names = "spiclk", "apb_pclk";
310                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
311                 pinctrl-names = "default";
312                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
313                 #address-cells = <1>;
314                 #size-cells = <0>;
315                 status = "disabled";
316         };
317
318         spi2: spi@ff130000 {
319                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
320                 reg = <0x0 0xff130000 0x0 0x1000>;
321                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
322                 clock-names = "spiclk", "apb_pclk";
323                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
324                 pinctrl-names = "default";
325                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
326                 #address-cells = <1>;
327                 #size-cells = <0>;
328                 status = "disabled";
329         };
330
331         i2c1: i2c@ff140000 {
332                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
333                 reg = <0x0 0xff140000 0x0 0x1000>;
334                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
335                 #address-cells = <1>;
336                 #size-cells = <0>;
337                 clock-names = "i2c";
338                 clocks = <&cru PCLK_I2C1>;
339                 pinctrl-names = "default";
340                 pinctrl-0 = <&i2c1_xfer>;
341                 status = "disabled";
342         };
343
344         i2c3: i2c@ff150000 {
345                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
346                 reg = <0x0 0xff150000 0x0 0x1000>;
347                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
348                 #address-cells = <1>;
349                 #size-cells = <0>;
350                 clock-names = "i2c";
351                 clocks = <&cru PCLK_I2C3>;
352                 pinctrl-names = "default";
353                 pinctrl-0 = <&i2c3_xfer>;
354                 status = "disabled";
355         };
356
357         i2c4: i2c@ff160000 {
358                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
359                 reg = <0x0 0xff160000 0x0 0x1000>;
360                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
361                 #address-cells = <1>;
362                 #size-cells = <0>;
363                 clock-names = "i2c";
364                 clocks = <&cru PCLK_I2C4>;
365                 pinctrl-names = "default";
366                 pinctrl-0 = <&i2c4_xfer>;
367                 status = "disabled";
368         };
369
370         i2c5: i2c@ff170000 {
371                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
372                 reg = <0x0 0xff170000 0x0 0x1000>;
373                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
374                 #address-cells = <1>;
375                 #size-cells = <0>;
376                 clock-names = "i2c";
377                 clocks = <&cru PCLK_I2C5>;
378                 pinctrl-names = "default";
379                 pinctrl-0 = <&i2c5_xfer>;
380                 status = "disabled";
381         };
382
383         uart0: serial@ff180000 {
384                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
385                 reg = <0x0 0xff180000 0x0 0x100>;
386                 clock-frequency = <24000000>;
387                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
388                 clock-names = "baudclk", "apb_pclk";
389                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
390                 reg-shift = <2>;
391                 reg-io-width = <4>;
392                 pinctrl-names = "default";
393                 pinctrl-0 = <&uart0_xfer>;
394                 status = "disabled";
395         };
396
397         uart1: serial@ff190000 {
398                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
399                 reg = <0x0 0xff190000 0x0 0x100>;
400                 clock-frequency = <24000000>;
401                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
402                 clock-names = "baudclk", "apb_pclk";
403                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
404                 reg-shift = <2>;
405                 reg-io-width = <4>;
406                 pinctrl-names = "default";
407                 pinctrl-1 = <&uart0_xfer>;
408                 status = "disabled";
409         };
410
411         uart3: serial@ff1b0000 {
412                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
413                 reg = <0x0 0xff1b0000 0x0 0x100>;
414                 clock-frequency = <24000000>;
415                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
416                 clock-names = "baudclk", "apb_pclk";
417                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
418                 reg-shift = <2>;
419                 reg-io-width = <4>;
420                 pinctrl-names = "default";
421                 pinctrl-0 = <&uart3_xfer>;
422                 status = "disabled";
423         };
424
425         uart4: serial@ff1c0000 {
426                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
427                 reg = <0x0 0xff1c0000 0x0 0x100>;
428                 clock-frequency = <24000000>;
429                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
430                 clock-names = "baudclk", "apb_pclk";
431                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
432                 reg-shift = <2>;
433                 reg-io-width = <4>;
434                 pinctrl-names = "default";
435                 pinctrl-0 = <&uart4_xfer>;
436                 status = "disabled";
437         };
438
439         thermal-zones {
440                 cpu {
441                         polling-delay-passive = <100>; /* milliseconds */
442                         polling-delay = <5000>; /* milliseconds */
443
444                         thermal-sensors = <&tsadc 0>;
445
446                         trips {
447                                 cpu_alert0: cpu_alert0 {
448                                         temperature = <75000>; /* millicelsius */
449                                         hysteresis = <2000>; /* millicelsius */
450                                         type = "passive";
451                                 };
452                                 cpu_alert1: cpu_alert1 {
453                                         temperature = <80000>; /* millicelsius */
454                                         hysteresis = <2000>; /* millicelsius */
455                                         type = "passive";
456                                 };
457                                 cpu_crit: cpu_crit {
458                                         temperature = <95000>; /* millicelsius */
459                                         hysteresis = <2000>; /* millicelsius */
460                                         type = "critical";
461                                 };
462                         };
463
464                         cooling-maps {
465                                 map0 {
466                                         trip = <&cpu_alert0>;
467                                         cooling-device =
468                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
469                                 };
470                                 map1 {
471                                         trip = <&cpu_alert1>;
472                                         cooling-device =
473                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
474                                 };
475                         };
476                 };
477
478                 gpu {
479                         polling-delay-passive = <100>; /* milliseconds */
480                         polling-delay = <5000>; /* milliseconds */
481
482                         thermal-sensors = <&tsadc 1>;
483
484                         trips {
485                                 gpu_alert0: gpu_alert0 {
486                                         temperature = <80000>; /* millicelsius */
487                                         hysteresis = <2000>; /* millicelsius */
488                                         type = "passive";
489                                 };
490                                 gpu_crit: gpu_crit {
491                                         temperature = <115000>; /* millicelsius */
492                                         hysteresis = <2000>; /* millicelsius */
493                                         type = "critical";
494                                 };
495                         };
496
497                         cooling-maps {
498                                 map0 {
499                                         trip = <&gpu_alert0>;
500                                         cooling-device =
501                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
502                                 };
503                         };
504                 };
505         };
506
507         tsadc: tsadc@ff280000 {
508                 compatible = "rockchip,rk3368-tsadc";
509                 reg = <0x0 0xff280000 0x0 0x100>;
510                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
511                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
512                 clock-names = "tsadc", "apb_pclk";
513                 resets = <&cru SRST_TSADC>;
514                 reset-names = "tsadc-apb";
515                 pinctrl-names = "init", "default", "sleep";
516                 pinctrl-0 = <&otp_gpio>;
517                 pinctrl-1 = <&otp_out>;
518                 pinctrl-2 = <&otp_gpio>;
519                 #thermal-sensor-cells = <1>;
520                 rockchip,hw-tshut-temp = <95000>;
521                 status = "disabled";
522         };
523
524         gmac: ethernet@ff290000 {
525                 compatible = "rockchip,rk3368-gmac";
526                 reg = <0x0 0xff290000 0x0 0x10000>;
527                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
528                 interrupt-names = "macirq";
529                 rockchip,grf = <&grf>;
530                 clocks = <&cru SCLK_MAC>,
531                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
532                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
533                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
534                 clock-names = "stmmaceth",
535                         "mac_clk_rx", "mac_clk_tx",
536                         "clk_mac_ref", "clk_mac_refout",
537                         "aclk_mac", "pclk_mac";
538                 status = "disabled";
539         };
540
541         usb_host0_ehci: usb@ff500000 {
542                 compatible = "generic-ehci";
543                 reg = <0x0 0xff500000 0x0 0x100>;
544                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
545                 clocks = <&cru HCLK_HOST0>;
546                 clock-names = "usbhost";
547                 status = "disabled";
548         };
549
550         usb_otg: usb@ff580000 {
551                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
552                                 "snps,dwc2";
553                 reg = <0x0 0xff580000 0x0 0x40000>;
554                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
555                 clocks = <&cru HCLK_OTG0>;
556                 clock-names = "otg";
557                 dr_mode = "otg";
558                 g-np-tx-fifo-size = <16>;
559                 g-rx-fifo-size = <275>;
560                 g-tx-fifo-size = <256 128 128 64 64 32>;
561                 g-use-dma;
562                 status = "disabled";
563         };
564
565         i2c0: i2c@ff650000 {
566                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
567                 reg = <0x0 0xff650000 0x0 0x1000>;
568                 clocks = <&cru PCLK_I2C0>;
569                 clock-names = "i2c";
570                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
571                 pinctrl-names = "default";
572                 pinctrl-0 = <&i2c0_xfer>;
573                 #address-cells = <1>;
574                 #size-cells = <0>;
575                 status = "disabled";
576         };
577
578         i2c2: i2c@ff660000 {
579                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
580                 reg = <0x0 0xff660000 0x0 0x1000>;
581                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
582                 #address-cells = <1>;
583                 #size-cells = <0>;
584                 clock-names = "i2c";
585                 clocks = <&cru PCLK_I2C2>;
586                 pinctrl-names = "default";
587                 pinctrl-0 = <&i2c2_xfer>;
588                 status = "disabled";
589         };
590
591         pwm0: pwm@ff680000 {
592                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
593                 reg = <0x0 0xff680000 0x0 0x10>;
594                 #pwm-cells = <3>;
595                 pinctrl-names = "default";
596                 pinctrl-0 = <&pwm0_pin>;
597                 clocks = <&cru PCLK_PWM1>;
598                 clock-names = "pwm";
599                 status = "disabled";
600         };
601
602         pwm1: pwm@ff680010 {
603                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
604                 reg = <0x0 0xff680010 0x0 0x10>;
605                 #pwm-cells = <3>;
606                 pinctrl-names = "default";
607                 pinctrl-0 = <&pwm1_pin>;
608                 clocks = <&cru PCLK_PWM1>;
609                 clock-names = "pwm";
610                 status = "disabled";
611         };
612
613         pwm2: pwm@ff680020 {
614                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
615                 reg = <0x0 0xff680020 0x0 0x10>;
616                 #pwm-cells = <3>;
617                 clocks = <&cru PCLK_PWM1>;
618                 clock-names = "pwm";
619                 status = "disabled";
620         };
621
622         pwm3: pwm@ff680030 {
623                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
624                 reg = <0x0 0xff680030 0x0 0x10>;
625                 #pwm-cells = <3>;
626                 pinctrl-names = "default";
627                 pinctrl-0 = <&pwm3_pin>;
628                 clocks = <&cru PCLK_PWM1>;
629                 clock-names = "pwm";
630                 status = "disabled";
631         };
632
633         uart2: serial@ff690000 {
634                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
635                 reg = <0x0 0xff690000 0x0 0x100>;
636                 clock-frequency = <24000000>;
637                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
638                 clock-names = "baudclk", "apb_pclk";
639                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
640                 pinctrl-names = "default";
641                 pinctrl-0 = <&uart2_xfer>;
642                 reg-shift = <2>;
643                 reg-io-width = <4>;
644                 status = "disabled";
645         };
646
647         mbox: mbox@ff6b0000 {
648                 compatible = "rockchip,rk3368-mailbox";
649                 reg = <0x0 0xff6b0000 0x0 0x1000>;
650                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
651                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
652                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
653                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
654                 clocks = <&cru PCLK_MAILBOX>;
655                 clock-names = "pclk_mailbox";
656                 #mbox-cells = <1>;
657         };
658
659         pmugrf: syscon@ff738000 {
660                 compatible = "rockchip,rk3368-pmugrf", "syscon";
661                 reg = <0x0 0xff738000 0x0 0x1000>;
662         };
663
664         sgrf: syscon@ff740000 {
665                 compatible = "rockchip,rk3368-sgrf", "syscon";
666                 reg = <0x0 0xff740000 0x0 0x1000>;
667         };
668
669         cru: clock-controller@ff760000 {
670                 compatible = "rockchip,rk3368-cru";
671                 reg = <0x0 0xff760000 0x0 0x1000>;
672                 rockchip,grf = <&grf>;
673                 #clock-cells = <1>;
674                 #reset-cells = <1>;
675         };
676
677         grf: syscon@ff770000 {
678                 compatible = "rockchip,rk3368-grf", "syscon";
679                 reg = <0x0 0xff770000 0x0 0x1000>;
680         };
681
682         wdt: watchdog@ff800000 {
683                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
684                 reg = <0x0 0xff800000 0x0 0x100>;
685                 clocks = <&cru PCLK_WDT>;
686                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
687                 status = "disabled";
688         };
689
690         timer0: timer@ff810000 {
691                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
692                 reg = <0x0 0xff810000 0x0 0x20>;
693                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
694         };
695
696         gic: interrupt-controller@ffb71000 {
697                 compatible = "arm,gic-400";
698                 interrupt-controller;
699                 #interrupt-cells = <3>;
700                 #address-cells = <0>;
701
702                 reg = <0x0 0xffb71000 0x0 0x1000>,
703                       <0x0 0xffb72000 0x0 0x1000>,
704                       <0x0 0xffb74000 0x0 0x2000>,
705                       <0x0 0xffb76000 0x0 0x2000>;
706                 interrupts = <GIC_PPI 9
707                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
708         };
709
710         pinctrl: pinctrl {
711                 compatible = "rockchip,rk3368-pinctrl";
712                 rockchip,grf = <&grf>;
713                 rockchip,pmu = <&pmugrf>;
714                 #address-cells = <0x2>;
715                 #size-cells = <0x2>;
716                 ranges;
717
718                 gpio0: gpio0@ff750000 {
719                         compatible = "rockchip,gpio-bank";
720                         reg = <0x0 0xff750000 0x0 0x100>;
721                         clocks = <&cru PCLK_GPIO0>;
722                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
723
724                         gpio-controller;
725                         #gpio-cells = <0x2>;
726
727                         interrupt-controller;
728                         #interrupt-cells = <0x2>;
729                 };
730
731                 gpio1: gpio1@ff780000 {
732                         compatible = "rockchip,gpio-bank";
733                         reg = <0x0 0xff780000 0x0 0x100>;
734                         clocks = <&cru PCLK_GPIO1>;
735                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
736
737                         gpio-controller;
738                         #gpio-cells = <0x2>;
739
740                         interrupt-controller;
741                         #interrupt-cells = <0x2>;
742                 };
743
744                 gpio2: gpio2@ff790000 {
745                         compatible = "rockchip,gpio-bank";
746                         reg = <0x0 0xff790000 0x0 0x100>;
747                         clocks = <&cru PCLK_GPIO2>;
748                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
749
750                         gpio-controller;
751                         #gpio-cells = <0x2>;
752
753                         interrupt-controller;
754                         #interrupt-cells = <0x2>;
755                 };
756
757                 gpio3: gpio3@ff7a0000 {
758                         compatible = "rockchip,gpio-bank";
759                         reg = <0x0 0xff7a0000 0x0 0x100>;
760                         clocks = <&cru PCLK_GPIO3>;
761                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
762
763                         gpio-controller;
764                         #gpio-cells = <0x2>;
765
766                         interrupt-controller;
767                         #interrupt-cells = <0x2>;
768                 };
769
770                 pcfg_pull_up: pcfg-pull-up {
771                         bias-pull-up;
772                 };
773
774                 pcfg_pull_down: pcfg-pull-down {
775                         bias-pull-down;
776                 };
777
778                 pcfg_pull_none: pcfg-pull-none {
779                         bias-disable;
780                 };
781
782                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
783                         bias-disable;
784                         drive-strength = <12>;
785                 };
786
787                 emmc {
788                         emmc_clk: emmc-clk {
789                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
790                         };
791
792                         emmc_cmd: emmc-cmd {
793                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
794                         };
795
796                         emmc_pwr: emmc-pwr {
797                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
798                         };
799
800                         emmc_bus1: emmc-bus1 {
801                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
802                         };
803
804                         emmc_bus4: emmc-bus4 {
805                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
806                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
807                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
808                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
809                         };
810
811                         emmc_bus8: emmc-bus8 {
812                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
813                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
814                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
815                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
816                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
817                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
818                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
819                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
820                         };
821                 };
822
823                 gmac {
824                         rgmii_pins: rgmii-pins {
825                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
826                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
827                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
828                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
829                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
830                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
831                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
832                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
833                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
834                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
835                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
836                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
837                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
838                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
839                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
840                         };
841
842                         rmii_pins: rmii-pins {
843                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
844                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
845                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
846                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
847                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
848                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
849                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
850                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
851                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
852                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
853                         };
854                 };
855
856                 i2c0 {
857                         i2c0_xfer: i2c0-xfer {
858                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
859                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
860                         };
861                 };
862
863                 i2c1 {
864                         i2c1_xfer: i2c1-xfer {
865                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
866                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
867                         };
868                 };
869
870                 i2c2 {
871                         i2c2_xfer: i2c2-xfer {
872                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
873                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
874                         };
875                 };
876
877                 i2c3 {
878                         i2c3_xfer: i2c3-xfer {
879                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
880                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
881                         };
882                 };
883
884                 i2c4 {
885                         i2c4_xfer: i2c4-xfer {
886                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
887                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
888                         };
889                 };
890
891                 i2c5 {
892                         i2c5_xfer: i2c5-xfer {
893                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
894                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
895                         };
896                 };
897
898                 pwm0 {
899                         pwm0_pin: pwm0-pin {
900                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
901                         };
902                 };
903
904                 pwm1 {
905                         pwm1_pin: pwm1-pin {
906                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
907                         };
908                 };
909
910                 pwm3 {
911                         pwm3_pin: pwm3-pin {
912                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
913                         };
914                 };
915
916                 sdio0 {
917                         sdio0_bus1: sdio0-bus1 {
918                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
919                         };
920
921                         sdio0_bus4: sdio0-bus4 {
922                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
923                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
924                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
925                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
926                         };
927
928                         sdio0_cmd: sdio0-cmd {
929                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
930                         };
931
932                         sdio0_clk: sdio0-clk {
933                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
934                         };
935
936                         sdio0_cd: sdio0-cd {
937                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
938                         };
939
940                         sdio0_wp: sdio0-wp {
941                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
942                         };
943
944                         sdio0_pwr: sdio0-pwr {
945                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
946                         };
947
948                         sdio0_bkpwr: sdio0-bkpwr {
949                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
950                         };
951
952                         sdio0_int: sdio0-int {
953                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
954                         };
955                 };
956
957                 sdmmc {
958                         sdmmc_clk: sdmmc-clk {
959                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
960                         };
961
962                         sdmmc_cmd: sdmmc-cmd {
963                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
964                         };
965
966                         sdmmc_cd: sdmmc-cd {
967                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
968                         };
969
970                         sdmmc_bus1: sdmmc-bus1 {
971                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
972                         };
973
974                         sdmmc_bus4: sdmmc-bus4 {
975                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
976                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
977                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
978                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
979                         };
980                 };
981
982                 spi0 {
983                         spi0_clk: spi0-clk {
984                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
985                         };
986                         spi0_cs0: spi0-cs0 {
987                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
988                         };
989                         spi0_cs1: spi0-cs1 {
990                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
991                         };
992                         spi0_tx: spi0-tx {
993                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
994                         };
995                         spi0_rx: spi0-rx {
996                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
997                         };
998                 };
999
1000                 spi1 {
1001                         spi1_clk: spi1-clk {
1002                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1003                         };
1004                         spi1_cs0: spi1-cs0 {
1005                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1006                         };
1007                         spi1_cs1: spi1-cs1 {
1008                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1009                         };
1010                         spi1_rx: spi1-rx {
1011                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1012                         };
1013                         spi1_tx: spi1-tx {
1014                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1015                         };
1016                 };
1017
1018                 spi2 {
1019                         spi2_clk: spi2-clk {
1020                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1021                         };
1022                         spi2_cs0: spi2-cs0 {
1023                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1024                         };
1025                         spi2_rx: spi2-rx {
1026                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1027                         };
1028                         spi2_tx: spi2-tx {
1029                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1030                         };
1031                 };
1032
1033                 tsadc {
1034                         otp_gpio: otp-gpio {
1035                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1036                         };
1037
1038                         otp_out: otp-out {
1039                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1040                         };
1041                 };
1042
1043                 uart0 {
1044                         uart0_xfer: uart0-xfer {
1045                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1046                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1047                         };
1048
1049                         uart0_cts: uart0-cts {
1050                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1051                         };
1052
1053                         uart0_rts: uart0-rts {
1054                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1055                         };
1056                 };
1057
1058                 uart1 {
1059                         uart1_xfer: uart1-xfer {
1060                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1061                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1062                         };
1063
1064                         uart1_cts: uart1-cts {
1065                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1066                         };
1067
1068                         uart1_rts: uart1-rts {
1069                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1070                         };
1071                 };
1072
1073                 uart2 {
1074                         uart2_xfer: uart2-xfer {
1075                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1076                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1077                         };
1078                         /* no rts / cts for uart2 */
1079                 };
1080
1081                 uart3 {
1082                         uart3_xfer: uart3-xfer {
1083                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1084                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1085                         };
1086
1087                         uart3_cts: uart3-cts {
1088                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1089                         };
1090
1091                         uart3_rts: uart3-rts {
1092                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1093                         };
1094                 };
1095
1096                 uart4 {
1097                         uart4_xfer: uart4-xfer {
1098                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1099                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1100                         };
1101
1102                         uart4_cts: uart4-cts {
1103                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1104                         };
1105
1106                         uart4_rts: uart4-rts {
1107                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1108                         };
1109                 };
1110         };
1111 };