arch/arm/dts/rk3368-px5-evb-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
   4  */
   5 / {
   6         chosen {
   7                 u-boot,spl-boot-order = &emmc;
   8                 tick-timer = "/timer@ff810000";
   9         };
  10 };
  11
  12 &dmc {
  13         u-boot,dm-pre-reloc;
  14
  15         /*
  16          * PX5-evb(2GB) need to use CBRD mode, or else the dram is not correct
  17          * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
  18          * details on the 'rockchip,memory-schedule' property and how it
  19          * affects the physical-address to device-address mapping.
  20          */
  21         rockchip,memory-schedule = <DMC_MSCH_CBRD>;
  22         rockchip,ddr-frequency = <800000000>;
  23         rockchip,ddr-speed-bin = <DDR3_1600K>;
  24
  25         status = "okay";
  26 };
  27
  28 &pinctrl {
  29         u-boot,dm-pre-reloc;
  30 };
  31
  32 &service_msch {
  33         u-boot,dm-pre-reloc;
  34 };
  35
  36 &dmc {
  37         u-boot,dm-pre-reloc;
  38         status = "okay";
  39 };
  40
  41 &pmugrf {
  42         u-boot,dm-pre-reloc;
  43 };
  44
  45 &sgrf {
  46         u-boot,dm-pre-reloc;
  47 };
  48
  49 &cru {
  50         u-boot,dm-pre-reloc;
  51 };
  52
  53 &grf {
  54         u-boot,dm-pre-reloc;
  55 };
  56
  57 &uart4 {
  58         u-boot,dm-pre-reloc;
  59 };
  60
  61 &emmc {
  62         u-boot,dm-pre-reloc;
  63 };
  64
  65 &timer0 {
  66         u-boot,dm-pre-reloc;
  67         clock-frequency = <24000000>;
  68         status = "okay";
  69 };