1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3328";
18 interrupt-parent = <&gic>;
31 ethernet1 = &gmac2phy;
40 compatible = "arm,cortex-a53";
42 clocks = <&cru ARMCLK>;
44 cpu-idle-states = <&CPU_SLEEP>;
45 dynamic-power-coefficient = <120>;
46 enable-method = "psci";
47 next-level-cache = <&l2>;
48 operating-points-v2 = <&cpu0_opp_table>;
53 compatible = "arm,cortex-a53";
55 clocks = <&cru ARMCLK>;
57 cpu-idle-states = <&CPU_SLEEP>;
58 dynamic-power-coefficient = <120>;
59 enable-method = "psci";
60 next-level-cache = <&l2>;
61 operating-points-v2 = <&cpu0_opp_table>;
66 compatible = "arm,cortex-a53";
68 clocks = <&cru ARMCLK>;
70 cpu-idle-states = <&CPU_SLEEP>;
71 dynamic-power-coefficient = <120>;
72 enable-method = "psci";
73 next-level-cache = <&l2>;
74 operating-points-v2 = <&cpu0_opp_table>;
79 compatible = "arm,cortex-a53";
81 clocks = <&cru ARMCLK>;
83 cpu-idle-states = <&CPU_SLEEP>;
84 dynamic-power-coefficient = <120>;
85 enable-method = "psci";
86 next-level-cache = <&l2>;
87 operating-points-v2 = <&cpu0_opp_table>;
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
104 compatible = "cache";
108 cpu0_opp_table: opp_table0 {
109 compatible = "operating-points-v2";
113 opp-hz = /bits/ 64 <408000000>;
114 opp-microvolt = <950000>;
115 clock-latency-ns = <40000>;
119 opp-hz = /bits/ 64 <600000000>;
120 opp-microvolt = <950000>;
121 clock-latency-ns = <40000>;
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1000000>;
126 clock-latency-ns = <40000>;
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1100000>;
131 clock-latency-ns = <40000>;
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1225000>;
136 clock-latency-ns = <40000>;
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1300000>;
141 clock-latency-ns = <40000>;
146 compatible = "simple-bus";
147 #address-cells = <2>;
151 dmac: dmac@ff1f0000 {
152 compatible = "arm,pl330", "arm,primecell";
153 reg = <0x0 0xff1f0000 0x0 0x4000>;
154 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&cru ACLK_DMAC>;
157 clock-names = "apb_pclk";
162 analog_sound: analog-sound {
163 compatible = "simple-audio-card";
164 simple-audio-card,format = "i2s";
165 simple-audio-card,mclk-fs = <256>;
166 simple-audio-card,name = "Analog";
169 simple-audio-card,cpu {
173 simple-audio-card,codec {
174 sound-dai = <&codec>;
179 compatible = "arm,cortex-a53-pmu";
180 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
187 display_subsystem: display-subsystem {
188 compatible = "rockchip,display-subsystem";
192 hdmi_sound: hdmi-sound {
193 compatible = "simple-audio-card";
194 simple-audio-card,format = "i2s";
195 simple-audio-card,mclk-fs = <128>;
196 simple-audio-card,name = "HDMI";
199 simple-audio-card,cpu {
203 simple-audio-card,codec {
209 compatible = "arm,psci-1.0", "arm,psci-0.2";
214 compatible = "arm,armv8-timer";
215 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
216 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
217 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
218 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
222 compatible = "fixed-clock";
224 clock-frequency = <24000000>;
225 clock-output-names = "xin24m";
229 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
230 reg = <0x0 0xff000000 0x0 0x1000>;
231 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
233 clock-names = "i2s_clk", "i2s_hclk";
234 dmas = <&dmac 11>, <&dmac 12>;
235 dma-names = "tx", "rx";
236 #sound-dai-cells = <0>;
241 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
242 reg = <0x0 0xff010000 0x0 0x1000>;
243 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
245 clock-names = "i2s_clk", "i2s_hclk";
246 dmas = <&dmac 14>, <&dmac 15>;
247 dma-names = "tx", "rx";
248 #sound-dai-cells = <0>;
253 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
254 reg = <0x0 0xff020000 0x0 0x1000>;
255 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
257 clock-names = "i2s_clk", "i2s_hclk";
258 dmas = <&dmac 0>, <&dmac 1>;
259 dma-names = "tx", "rx";
260 #sound-dai-cells = <0>;
264 spdif: spdif@ff030000 {
265 compatible = "rockchip,rk3328-spdif";
266 reg = <0x0 0xff030000 0x0 0x1000>;
267 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
269 clock-names = "mclk", "hclk";
272 pinctrl-names = "default";
273 pinctrl-0 = <&spdifm2_tx>;
274 #sound-dai-cells = <0>;
279 compatible = "rockchip,pdm";
280 reg = <0x0 0xff040000 0x0 0x1000>;
281 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
282 clock-names = "pdm_clk", "pdm_hclk";
285 pinctrl-names = "default", "sleep";
286 pinctrl-0 = <&pdmm0_clk
291 pinctrl-1 = <&pdmm0_clk_sleep
299 grf: syscon@ff100000 {
300 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
301 reg = <0x0 0xff100000 0x0 0x1000>;
303 io_domains: io-domains {
304 compatible = "rockchip,rk3328-io-voltage-domain";
309 compatible = "rockchip,rk3328-grf-gpio";
314 power: power-controller {
315 compatible = "rockchip,rk3328-power-controller";
316 #power-domain-cells = <1>;
317 #address-cells = <1>;
320 pd_hevc@RK3328_PD_HEVC {
321 reg = <RK3328_PD_HEVC>;
323 pd_video@RK3328_PD_VIDEO {
324 reg = <RK3328_PD_VIDEO>;
326 pd_vpu@RK3328_PD_VPU {
327 reg = <RK3328_PD_VPU>;
328 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
333 compatible = "syscon-reboot-mode";
335 mode-normal = <BOOT_NORMAL>;
336 mode-recovery = <BOOT_RECOVERY>;
337 mode-bootloader = <BOOT_FASTBOOT>;
338 mode-loader = <BOOT_BL_DOWNLOAD>;
342 uart0: serial@ff110000 {
343 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
344 reg = <0x0 0xff110000 0x0 0x100>;
345 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
347 clock-names = "baudclk", "apb_pclk";
348 dmas = <&dmac 2>, <&dmac 3>;
349 dma-names = "tx", "rx";
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
357 uart1: serial@ff120000 {
358 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
359 reg = <0x0 0xff120000 0x0 0x100>;
360 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
362 clock-names = "baudclk", "apb_pclk";
363 dmas = <&dmac 4>, <&dmac 5>;
364 dma-names = "tx", "rx";
365 pinctrl-names = "default";
366 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
372 uart2: serial@ff130000 {
373 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
374 reg = <0x0 0xff130000 0x0 0x100>;
375 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
377 clock-names = "baudclk", "apb_pclk";
378 dmas = <&dmac 6>, <&dmac 7>;
379 dma-names = "tx", "rx";
380 pinctrl-names = "default";
381 pinctrl-0 = <&uart2m1_xfer>;
388 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
389 reg = <0x0 0xff150000 0x0 0x1000>;
390 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
391 #address-cells = <1>;
393 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
394 clock-names = "i2c", "pclk";
395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c0_xfer>;
401 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
402 reg = <0x0 0xff160000 0x0 0x1000>;
403 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
406 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
407 clock-names = "i2c", "pclk";
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c1_xfer>;
414 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
415 reg = <0x0 0xff170000 0x0 0x1000>;
416 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
417 #address-cells = <1>;
419 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
420 clock-names = "i2c", "pclk";
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c2_xfer>;
427 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
428 reg = <0x0 0xff180000 0x0 0x1000>;
429 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
430 #address-cells = <1>;
432 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
433 clock-names = "i2c", "pclk";
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c3_xfer>;
440 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
441 reg = <0x0 0xff190000 0x0 0x1000>;
442 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
445 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
446 clock-names = "spiclk", "apb_pclk";
447 dmas = <&dmac 8>, <&dmac 9>;
448 dma-names = "tx", "rx";
449 pinctrl-names = "default";
450 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
454 wdt: watchdog@ff1a0000 {
455 compatible = "snps,dw-wdt";
456 reg = <0x0 0xff1a0000 0x0 0x100>;
457 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&cru PCLK_WDT>;
462 compatible = "rockchip,rk3328-pwm";
463 reg = <0x0 0xff1b0000 0x0 0x10>;
464 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
465 clock-names = "pwm", "pclk";
466 pinctrl-names = "default";
467 pinctrl-0 = <&pwm0_pin>;
473 compatible = "rockchip,rk3328-pwm";
474 reg = <0x0 0xff1b0010 0x0 0x10>;
475 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
476 clock-names = "pwm", "pclk";
477 pinctrl-names = "default";
478 pinctrl-0 = <&pwm1_pin>;
484 compatible = "rockchip,rk3328-pwm";
485 reg = <0x0 0xff1b0020 0x0 0x10>;
486 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
487 clock-names = "pwm", "pclk";
488 pinctrl-names = "default";
489 pinctrl-0 = <&pwm2_pin>;
495 compatible = "rockchip,rk3328-pwm";
496 reg = <0x0 0xff1b0030 0x0 0x10>;
497 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
499 clock-names = "pwm", "pclk";
500 pinctrl-names = "default";
501 pinctrl-0 = <&pwmir_pin>;
507 soc_thermal: soc-thermal {
508 polling-delay-passive = <20>;
509 polling-delay = <1000>;
510 sustainable-power = <1000>;
512 thermal-sensors = <&tsadc 0>;
515 threshold: trip-point0 {
516 temperature = <70000>;
520 target: trip-point1 {
521 temperature = <85000>;
526 temperature = <95000>;
535 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
536 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
537 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
538 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
539 contribution = <4096>;
546 tsadc: tsadc@ff250000 {
547 compatible = "rockchip,rk3328-tsadc";
548 reg = <0x0 0xff250000 0x0 0x100>;
549 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
550 assigned-clocks = <&cru SCLK_TSADC>;
551 assigned-clock-rates = <50000>;
552 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
553 clock-names = "tsadc", "apb_pclk";
554 pinctrl-names = "init", "default", "sleep";
555 pinctrl-0 = <&otp_gpio>;
556 pinctrl-1 = <&otp_out>;
557 pinctrl-2 = <&otp_gpio>;
558 resets = <&cru SRST_TSADC>;
559 reset-names = "tsadc-apb";
560 rockchip,grf = <&grf>;
561 rockchip,hw-tshut-temp = <100000>;
562 #thermal-sensor-cells = <1>;
566 efuse: efuse@ff260000 {
567 compatible = "rockchip,rk3328-efuse";
568 reg = <0x0 0xff260000 0x0 0x50>;
569 #address-cells = <1>;
571 clocks = <&cru SCLK_EFUSE>;
572 clock-names = "pclk_efuse";
573 rockchip,efuse-size = <0x20>;
579 cpu_leakage: cpu-leakage@17 {
582 logic_leakage: logic-leakage@19 {
585 efuse_cpu_version: cpu-version@1a {
591 saradc: adc@ff280000 {
592 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
593 reg = <0x0 0xff280000 0x0 0x100>;
594 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
595 #io-channel-cells = <1>;
596 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
597 clock-names = "saradc", "apb_pclk";
598 resets = <&cru SRST_SARADC_P>;
599 reset-names = "saradc-apb";
604 compatible = "rockchip,rk3328-mali", "arm,mali-450";
605 reg = <0x0 0xff300000 0x0 0x40000>;
606 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "gp",
620 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
621 clock-names = "bus", "core";
622 resets = <&cru SRST_GPU_A>;
625 h265e_mmu: iommu@ff330200 {
626 compatible = "rockchip,iommu";
627 reg = <0x0 0xff330200 0 0x100>;
628 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
629 interrupt-names = "h265e_mmu";
630 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
631 clock-names = "aclk", "iface";
636 vepu_mmu: iommu@ff340800 {
637 compatible = "rockchip,iommu";
638 reg = <0x0 0xff340800 0x0 0x40>;
639 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
640 interrupt-names = "vepu_mmu";
641 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
642 clock-names = "aclk", "iface";
647 vpu: video-codec@ff350000 {
648 compatible = "rockchip,rk3328-vpu";
649 reg = <0x0 0xff350000 0x0 0x800>;
650 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
651 interrupt-names = "vdpu";
652 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
653 clock-names = "aclk", "hclk";
655 power-domains = <&power RK3328_PD_VPU>;
658 vpu_mmu: iommu@ff350800 {
659 compatible = "rockchip,iommu";
660 reg = <0x0 0xff350800 0x0 0x40>;
661 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
662 interrupt-names = "vpu_mmu";
663 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
664 clock-names = "aclk", "iface";
666 power-domains = <&power RK3328_PD_VPU>;
669 rkvdec_mmu: iommu@ff360480 {
670 compatible = "rockchip,iommu";
671 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
672 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
673 interrupt-names = "rkvdec_mmu";
674 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
675 clock-names = "aclk", "iface";
681 compatible = "rockchip,rk3328-vop";
682 reg = <0x0 0xff370000 0x0 0x3efc>;
683 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
684 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
685 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
686 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
687 reset-names = "axi", "ahb", "dclk";
692 #address-cells = <1>;
695 vop_out_hdmi: endpoint@0 {
697 remote-endpoint = <&hdmi_in_vop>;
702 vop_mmu: iommu@ff373f00 {
703 compatible = "rockchip,iommu";
704 reg = <0x0 0xff373f00 0x0 0x100>;
705 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
706 interrupt-names = "vop_mmu";
707 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
708 clock-names = "aclk", "iface";
713 hdmi: hdmi@ff3c0000 {
714 compatible = "rockchip,rk3328-dw-hdmi";
715 reg = <0x0 0xff3c0000 0x0 0x20000>;
717 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&cru PCLK_HDMI>,
720 <&cru SCLK_HDMI_SFC>,
722 clock-names = "iahb",
727 pinctrl-names = "default";
728 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
729 rockchip,grf = <&grf>;
730 #sound-dai-cells = <0>;
735 hdmi_in_vop: endpoint {
736 remote-endpoint = <&vop_out_hdmi>;
742 codec: codec@ff410000 {
743 compatible = "rockchip,rk3328-codec";
744 reg = <0x0 0xff410000 0x0 0x1000>;
745 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
746 clock-names = "pclk", "mclk";
747 rockchip,grf = <&grf>;
748 #sound-dai-cells = <0>;
752 hdmiphy: phy@ff430000 {
753 compatible = "rockchip,rk3328-hdmi-phy";
754 reg = <0x0 0xff430000 0x0 0x10000>;
755 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
757 clock-names = "sysclk", "refoclk", "refpclk";
758 clock-output-names = "hdmi_phy";
760 nvmem-cells = <&efuse_cpu_version>;
761 nvmem-cell-names = "cpu-version";
766 cru: clock-controller@ff440000 {
767 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
768 reg = <0x0 0xff440000 0x0 0x1000>;
769 rockchip,grf = <&grf>;
774 * CPLL should run at 1200, but that is to high for
775 * the initial dividers of most of its children.
776 * We need set cpll child clk div first,
777 * and then set the cpll frequency.
779 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
780 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
781 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
782 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
783 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
784 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
785 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
786 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
787 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
788 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
789 <&cru SCLK_WIFI>, <&cru ARMCLK>,
790 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
791 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
792 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
793 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
795 assigned-clock-parents =
796 <&cru HDMIPHY>, <&cru PLL_APLL>,
797 <&cru PLL_GPLL>, <&xin24m>,
798 <&xin24m>, <&xin24m>;
799 assigned-clock-rates =
802 <24000000>, <24000000>,
803 <15000000>, <15000000>,
804 <100000000>, <100000000>,
805 <100000000>, <100000000>,
806 <50000000>, <100000000>,
807 <100000000>, <100000000>,
808 <50000000>, <50000000>,
809 <50000000>, <50000000>,
810 <24000000>, <600000000>,
811 <491520000>, <1200000000>,
812 <150000000>, <75000000>,
813 <75000000>, <150000000>,
814 <75000000>, <75000000>,
818 usb2phy_grf: syscon@ff450000 {
819 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
821 reg = <0x0 0xff450000 0x0 0x10000>;
822 #address-cells = <1>;
825 u2phy: usb2-phy@100 {
826 compatible = "rockchip,rk3328-usb2phy";
829 clock-names = "phyclk";
830 clock-output-names = "usb480m_phy";
832 assigned-clocks = <&cru USB480M>;
833 assigned-clock-parents = <&u2phy>;
836 u2phy_otg: otg-port {
838 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
839 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
841 interrupt-names = "otg-bvalid", "otg-id",
846 u2phy_host: host-port {
848 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
849 interrupt-names = "linestate";
855 sdmmc: mmc@ff500000 {
856 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
857 reg = <0x0 0xff500000 0x0 0x4000>;
858 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
860 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
861 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
862 fifo-depth = <0x100>;
863 max-frequency = <150000000>;
868 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
869 reg = <0x0 0xff510000 0x0 0x4000>;
870 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
872 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
873 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
874 fifo-depth = <0x100>;
875 max-frequency = <150000000>;
880 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
881 reg = <0x0 0xff520000 0x0 0x4000>;
882 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
884 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
885 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
886 fifo-depth = <0x100>;
887 max-frequency = <150000000>;
891 gmac2io: ethernet@ff540000 {
892 compatible = "rockchip,rk3328-gmac";
893 reg = <0x0 0xff540000 0x0 0x10000>;
894 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
895 interrupt-names = "macirq";
896 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
897 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
898 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
900 clock-names = "stmmaceth", "mac_clk_rx",
901 "mac_clk_tx", "clk_mac_ref",
902 "clk_mac_refout", "aclk_mac",
904 resets = <&cru SRST_GMAC2IO_A>;
905 reset-names = "stmmaceth";
906 rockchip,grf = <&grf>;
911 gmac2phy: ethernet@ff550000 {
912 compatible = "rockchip,rk3328-gmac";
913 reg = <0x0 0xff550000 0x0 0x10000>;
914 rockchip,grf = <&grf>;
915 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
916 interrupt-names = "macirq";
917 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
918 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
919 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
920 <&cru SCLK_MAC2PHY_OUT>;
921 clock-names = "stmmaceth", "mac_clk_rx",
922 "mac_clk_tx", "clk_mac_ref",
923 "aclk_mac", "pclk_mac",
925 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
926 reset-names = "stmmaceth", "mac-phy";
933 compatible = "snps,dwmac-mdio";
934 #address-cells = <1>;
938 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
940 clocks = <&cru SCLK_MAC2PHY_OUT>;
941 resets = <&cru SRST_MACPHY>;
942 pinctrl-names = "default";
943 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
949 usb_host0_ehci: usb@ff5c0000 {
950 compatible = "generic-ehci";
951 reg = <0x0 0xff5c0000 0x0 0x10000>;
952 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&cru HCLK_HOST0>, <&u2phy>;
954 phys = <&u2phy_host>;
959 usb_host0_ohci: usb@ff5d0000 {
960 compatible = "generic-ohci";
961 reg = <0x0 0xff5d0000 0x0 0x10000>;
962 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&cru HCLK_HOST0>, <&u2phy>;
964 phys = <&u2phy_host>;
970 * U-boot Specific Change
972 * The OTG controller must come after the USB host pair for it
973 * to work. This is likely due to lack of support for the USB
974 * PHYs. This must be manually changed after each device tree
975 * sync. There is no clean way to handle this in -u-boot.dtsi
978 usb20_otg: usb@ff580000 {
979 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
981 reg = <0x0 0xff580000 0x0 0x40000>;
982 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&cru HCLK_OTG>;
986 g-np-tx-fifo-size = <16>;
987 g-rx-fifo-size = <280>;
988 g-tx-fifo-size = <256 128 128 64 32 16>;
990 phy-names = "usb2-phy";
994 gic: interrupt-controller@ff811000 {
995 compatible = "arm,gic-400";
996 #interrupt-cells = <3>;
997 #address-cells = <0>;
998 interrupt-controller;
999 reg = <0x0 0xff811000 0 0x1000>,
1000 <0x0 0xff812000 0 0x2000>,
1001 <0x0 0xff814000 0 0x2000>,
1002 <0x0 0xff816000 0 0x2000>;
1003 interrupts = <GIC_PPI 9
1004 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1008 compatible = "rockchip,rk3328-pinctrl";
1009 rockchip,grf = <&grf>;
1010 #address-cells = <2>;
1014 gpio0: gpio0@ff210000 {
1015 compatible = "rockchip,gpio-bank";
1016 reg = <0x0 0xff210000 0x0 0x100>;
1017 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&cru PCLK_GPIO0>;
1023 interrupt-controller;
1024 #interrupt-cells = <2>;
1027 gpio1: gpio1@ff220000 {
1028 compatible = "rockchip,gpio-bank";
1029 reg = <0x0 0xff220000 0x0 0x100>;
1030 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&cru PCLK_GPIO1>;
1036 interrupt-controller;
1037 #interrupt-cells = <2>;
1040 gpio2: gpio2@ff230000 {
1041 compatible = "rockchip,gpio-bank";
1042 reg = <0x0 0xff230000 0x0 0x100>;
1043 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&cru PCLK_GPIO2>;
1049 interrupt-controller;
1050 #interrupt-cells = <2>;
1053 gpio3: gpio3@ff240000 {
1054 compatible = "rockchip,gpio-bank";
1055 reg = <0x0 0xff240000 0x0 0x100>;
1056 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&cru PCLK_GPIO3>;
1062 interrupt-controller;
1063 #interrupt-cells = <2>;
1066 pcfg_pull_up: pcfg-pull-up {
1070 pcfg_pull_down: pcfg-pull-down {
1074 pcfg_pull_none: pcfg-pull-none {
1078 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1080 drive-strength = <2>;
1083 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1085 drive-strength = <2>;
1088 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1090 drive-strength = <4>;
1093 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1095 drive-strength = <4>;
1098 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1100 drive-strength = <4>;
1103 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1105 drive-strength = <8>;
1108 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1110 drive-strength = <8>;
1113 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1115 drive-strength = <12>;
1118 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1120 drive-strength = <12>;
1123 pcfg_output_high: pcfg-output-high {
1127 pcfg_output_low: pcfg-output-low {
1131 pcfg_input_high: pcfg-input-high {
1136 pcfg_input: pcfg-input {
1141 i2c0_xfer: i2c0-xfer {
1142 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1143 <2 RK_PD1 1 &pcfg_pull_none>;
1148 i2c1_xfer: i2c1-xfer {
1149 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1150 <2 RK_PA5 2 &pcfg_pull_none>;
1155 i2c2_xfer: i2c2-xfer {
1156 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1157 <2 RK_PB6 1 &pcfg_pull_none>;
1162 i2c3_xfer: i2c3-xfer {
1163 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1164 <0 RK_PA6 2 &pcfg_pull_none>;
1166 i2c3_gpio: i2c3-gpio {
1168 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1169 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1174 hdmii2c_xfer: hdmii2c-xfer {
1175 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1176 <0 RK_PA6 1 &pcfg_pull_none>;
1181 pdmm0_clk: pdmm0-clk {
1182 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1185 pdmm0_fsync: pdmm0-fsync {
1186 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1189 pdmm0_sdi0: pdmm0-sdi0 {
1190 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1193 pdmm0_sdi1: pdmm0-sdi1 {
1194 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1197 pdmm0_sdi2: pdmm0-sdi2 {
1198 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1201 pdmm0_sdi3: pdmm0-sdi3 {
1202 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1205 pdmm0_clk_sleep: pdmm0-clk-sleep {
1207 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1210 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1212 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1215 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1217 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1220 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1222 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1225 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1227 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1230 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1232 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1237 otp_gpio: otp-gpio {
1238 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1242 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1247 uart0_xfer: uart0-xfer {
1248 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1249 <1 RK_PB0 1 &pcfg_pull_none>;
1252 uart0_cts: uart0-cts {
1253 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1256 uart0_rts: uart0-rts {
1257 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1260 uart0_rts_gpio: uart0-rts-gpio {
1261 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1266 uart1_xfer: uart1-xfer {
1267 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1268 <3 RK_PA6 4 &pcfg_pull_none>;
1271 uart1_cts: uart1-cts {
1272 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1275 uart1_rts: uart1-rts {
1276 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1279 uart1_rts_gpio: uart1-rts-gpio {
1280 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1285 uart2m0_xfer: uart2m0-xfer {
1286 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1287 <1 RK_PA1 2 &pcfg_pull_none>;
1292 uart2m1_xfer: uart2m1-xfer {
1293 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1294 <2 RK_PA1 1 &pcfg_pull_none>;
1299 spi0m0_clk: spi0m0-clk {
1300 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1303 spi0m0_cs0: spi0m0-cs0 {
1304 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1307 spi0m0_tx: spi0m0-tx {
1308 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1311 spi0m0_rx: spi0m0-rx {
1312 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1315 spi0m0_cs1: spi0m0-cs1 {
1316 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1321 spi0m1_clk: spi0m1-clk {
1322 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1325 spi0m1_cs0: spi0m1-cs0 {
1326 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1329 spi0m1_tx: spi0m1-tx {
1330 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1333 spi0m1_rx: spi0m1-rx {
1334 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1337 spi0m1_cs1: spi0m1-cs1 {
1338 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1343 spi0m2_clk: spi0m2-clk {
1344 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1347 spi0m2_cs0: spi0m2-cs0 {
1348 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1351 spi0m2_tx: spi0m2-tx {
1352 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1355 spi0m2_rx: spi0m2-rx {
1356 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1361 i2s1_mclk: i2s1-mclk {
1362 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1365 i2s1_sclk: i2s1-sclk {
1366 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1369 i2s1_lrckrx: i2s1-lrckrx {
1370 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1373 i2s1_lrcktx: i2s1-lrcktx {
1374 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1377 i2s1_sdi: i2s1-sdi {
1378 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1381 i2s1_sdo: i2s1-sdo {
1382 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1385 i2s1_sdio1: i2s1-sdio1 {
1386 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1389 i2s1_sdio2: i2s1-sdio2 {
1390 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1393 i2s1_sdio3: i2s1-sdio3 {
1394 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1397 i2s1_sleep: i2s1-sleep {
1399 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1400 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1401 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1402 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1403 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1404 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1405 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1406 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1407 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1412 i2s2m0_mclk: i2s2m0-mclk {
1413 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1416 i2s2m0_sclk: i2s2m0-sclk {
1417 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1420 i2s2m0_lrckrx: i2s2m0-lrckrx {
1421 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1424 i2s2m0_lrcktx: i2s2m0-lrcktx {
1425 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1428 i2s2m0_sdi: i2s2m0-sdi {
1429 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1432 i2s2m0_sdo: i2s2m0-sdo {
1433 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1436 i2s2m0_sleep: i2s2m0-sleep {
1438 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1439 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1440 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1441 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1442 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1443 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1448 i2s2m1_mclk: i2s2m1-mclk {
1449 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1452 i2s2m1_sclk: i2s2m1-sclk {
1453 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1456 i2s2m1_lrckrx: i2sm1-lrckrx {
1457 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1460 i2s2m1_lrcktx: i2s2m1-lrcktx {
1461 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1464 i2s2m1_sdi: i2s2m1-sdi {
1465 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1468 i2s2m1_sdo: i2s2m1-sdo {
1469 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1472 i2s2m1_sleep: i2s2m1-sleep {
1474 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1475 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1476 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1477 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1478 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1483 spdifm0_tx: spdifm0-tx {
1484 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1489 spdifm1_tx: spdifm1-tx {
1490 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1495 spdifm2_tx: spdifm2-tx {
1496 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1501 sdmmc0m0_pwren: sdmmc0m0-pwren {
1502 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1505 sdmmc0m0_gpio: sdmmc0m0-gpio {
1506 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1511 sdmmc0m1_pwren: sdmmc0m1-pwren {
1512 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1515 sdmmc0m1_gpio: sdmmc0m1-gpio {
1516 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1521 sdmmc0_clk: sdmmc0-clk {
1522 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1525 sdmmc0_cmd: sdmmc0-cmd {
1526 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1529 sdmmc0_dectn: sdmmc0-dectn {
1530 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1533 sdmmc0_wrprt: sdmmc0-wrprt {
1534 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1537 sdmmc0_bus1: sdmmc0-bus1 {
1538 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1541 sdmmc0_bus4: sdmmc0-bus4 {
1542 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1543 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1544 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1545 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1548 sdmmc0_gpio: sdmmc0-gpio {
1550 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1551 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1552 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1553 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1554 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1555 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1556 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1557 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1562 sdmmc0ext_clk: sdmmc0ext-clk {
1563 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1566 sdmmc0ext_cmd: sdmmc0ext-cmd {
1567 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1570 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1571 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1574 sdmmc0ext_dectn: sdmmc0ext-dectn {
1575 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1578 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1579 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1582 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1584 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1585 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1586 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1587 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1590 sdmmc0ext_gpio: sdmmc0ext-gpio {
1592 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1593 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1594 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1595 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1596 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1597 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1598 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1599 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1604 sdmmc1_clk: sdmmc1-clk {
1605 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1608 sdmmc1_cmd: sdmmc1-cmd {
1609 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1612 sdmmc1_pwren: sdmmc1-pwren {
1613 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1616 sdmmc1_wrprt: sdmmc1-wrprt {
1617 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1620 sdmmc1_dectn: sdmmc1-dectn {
1621 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1624 sdmmc1_bus1: sdmmc1-bus1 {
1625 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1628 sdmmc1_bus4: sdmmc1-bus4 {
1629 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1630 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1631 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1632 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1635 sdmmc1_gpio: sdmmc1-gpio {
1637 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1638 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1639 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1640 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1641 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1642 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1643 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1644 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1645 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1650 emmc_clk: emmc-clk {
1651 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1654 emmc_cmd: emmc-cmd {
1655 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1658 emmc_pwren: emmc-pwren {
1659 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1662 emmc_rstnout: emmc-rstnout {
1663 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1666 emmc_bus1: emmc-bus1 {
1667 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1670 emmc_bus4: emmc-bus4 {
1672 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1673 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1674 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1675 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1678 emmc_bus8: emmc-bus8 {
1680 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1681 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1682 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1683 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1684 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1685 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1686 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1687 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1692 pwm0_pin: pwm0-pin {
1693 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1698 pwm1_pin: pwm1-pin {
1699 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1704 pwm2_pin: pwm2-pin {
1705 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1710 pwmir_pin: pwmir-pin {
1711 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1716 rgmiim1_pins: rgmiim1-pins {
1719 <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1721 <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1723 <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1725 <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1727 <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1729 <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1731 <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1733 <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1735 <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1737 <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1739 <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1741 <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1743 <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1745 <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1747 <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1750 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1752 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1754 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1756 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1758 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1760 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1762 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1765 rmiim1_pins: rmiim1-pins {
1768 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1770 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1772 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1774 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1776 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1778 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1780 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1782 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1784 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1786 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1789 <0 RK_PB3 1 &pcfg_pull_none>,
1791 <0 RK_PB4 1 &pcfg_pull_none>,
1793 <0 RK_PD0 1 &pcfg_pull_none>,
1795 <0 RK_PC3 1 &pcfg_pull_none>,
1797 <0 RK_PC0 1 &pcfg_pull_none>,
1799 <0 RK_PC1 1 &pcfg_pull_none>;
1804 fephyled_speed10: fephyled-speed10 {
1805 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1808 fephyled_duplex: fephyled-duplex {
1809 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1812 fephyled_rxm1: fephyled-rxm1 {
1813 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1816 fephyled_txm1: fephyled-txm1 {
1817 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1820 fephyled_linkm1: fephyled-linkm1 {
1821 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1826 tsadc_int: tsadc-int {
1827 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1829 tsadc_gpio: tsadc-gpio {
1830 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1835 hdmi_cec: hdmi-cec {
1836 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1839 hdmi_hpd: hdmi-hpd {
1840 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1845 dvp_d2d9_m0:dvp-d2d9-m0 {
1848 <3 RK_PA4 2 &pcfg_pull_none>,
1850 <3 RK_PA5 2 &pcfg_pull_none>,
1852 <3 RK_PA6 2 &pcfg_pull_none>,
1854 <3 RK_PA7 2 &pcfg_pull_none>,
1856 <3 RK_PB0 2 &pcfg_pull_none>,
1858 <3 RK_PB1 2 &pcfg_pull_none>,
1860 <3 RK_PB2 2 &pcfg_pull_none>,
1862 <3 RK_PB3 2 &pcfg_pull_none>,
1864 <3 RK_PA1 2 &pcfg_pull_none>,
1866 <3 RK_PA0 2 &pcfg_pull_none>,
1868 <3 RK_PA3 2 &pcfg_pull_none>,
1870 <3 RK_PA2 2 &pcfg_pull_none>;
1875 dvp_d2d9_m1:dvp-d2d9-m1 {
1878 <3 RK_PA4 2 &pcfg_pull_none>,
1880 <3 RK_PA5 2 &pcfg_pull_none>,
1882 <3 RK_PA6 2 &pcfg_pull_none>,
1884 <3 RK_PA7 2 &pcfg_pull_none>,
1886 <3 RK_PB0 2 &pcfg_pull_none>,
1888 <2 RK_PC0 4 &pcfg_pull_none>,
1890 <2 RK_PC1 4 &pcfg_pull_none>,
1892 <2 RK_PC2 4 &pcfg_pull_none>,
1894 <3 RK_PA1 2 &pcfg_pull_none>,
1896 <3 RK_PA0 2 &pcfg_pull_none>,
1898 <2 RK_PB7 4 &pcfg_pull_none>,
1900 <3 RK_PA2 2 &pcfg_pull_none>;