arch/arm/dts/rk3328.dtsi

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <dt-bindings/clock/rk3328-cru.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/pinctrl/rockchip.h>
  12
  13 / {
  14         compatible = "rockchip,rk3328";
  15
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28         };
  29
  30         cpus {
  31                 #address-cells = <2>;
  32                 #size-cells = <0>;
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53", "arm,armv8";
  37                         reg = <0x0 0x0>;
  38                         enable-method = "psci";
  39 //                      clocks = <&cru ARMCLK>;
  40                         operating-points-v2 = <&cpu0_opp_table>;
  41                 };
  42                 cpu1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53", "arm,armv8";
  45                         reg = <0x0 0x1>;
  46                         enable-method = "psci";
  47                 };
  48                 cpu2: cpu@2 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a53", "arm,armv8";
  51                         reg = <0x0 0x2>;
  52                         enable-method = "psci";
  53                 };
  54                 cpu3: cpu@3 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a53", "arm,armv8";
  57                         reg = <0x0 0x3>;
  58                         enable-method = "psci";
  59                 };
  60         };
  61
  62         cpu0_opp_table: opp_table0 {
  63                 compatible = "operating-points-v2";
  64                 opp-shared;
  65
  66                 opp@408000000 {
  67                         opp-hz = /bits/ 64 <408000000>;
  68                         opp-microvolt = <950000>;
  69                         clock-latency-ns = <40000>;
  70                         opp-suspend;
  71                 };
  72                 opp@600000000 {
  73                         opp-hz = /bits/ 64 <600000000>;
  74                         opp-microvolt = <950000>;
  75                         clock-latency-ns = <40000>;
  76                 };
  77                 opp@816000000 {
  78                         opp-hz = /bits/ 64 <816000000>;
  79                         opp-microvolt = <1000000>;
  80                         clock-latency-ns = <40000>;
  81                 };
  82                 opp@1008000000 {
  83                         opp-hz = /bits/ 64 <1008000000>;
  84                         opp-microvolt = <1100000>;
  85                         clock-latency-ns = <40000>;
  86                 };
  87                 opp@1200000000 {
  88                         opp-hz = /bits/ 64 <1200000000>;
  89                         opp-microvolt = <1225000>;
  90                         clock-latency-ns = <40000>;
  91                 };
  92                 opp@1296000000 {
  93                         opp-hz = /bits/ 64 <1296000000>;
  94                         opp-microvolt = <1300000>;
  95                         clock-latency-ns = <40000>;
  96                 };
  97         };
  98
  99         arm-pmu {
 100                 compatible = "arm,cortex-a53-pmu";
 101                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 102                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 103                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 104                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 105                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 106         };
 107
 108         psci {
 109                 compatible = "arm,psci-1.0";
 110                 method = "smc";
 111         };
 112
 113         timer {
 114                 compatible = "arm,armv8-timer";
 115                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 116                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 117                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 118                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 119         };
 120
 121         xin24m: xin24m {
 122                 compatible = "fixed-clock";
 123                 #clock-cells = <0>;
 124                 clock-frequency = <24000000>;
 125                 clock-output-names = "xin24m";
 126         };
 127
 128         i2s0: i2s@ff000000 {
 129                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 130                 reg = <0x0 0xff000000 0x0 0x1000>;
 131                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 132                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 133                 clock-names = "i2s_clk", "i2s_hclk";
 134                 dmas = <&dmac 11>, <&dmac 12>;
 135                 #dma-cells = <2>;
 136                 dma-names = "tx", "rx";
 137                 status = "disabled";
 138         };
 139
 140         i2s1: i2s@ff010000 {
 141                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 142                 reg = <0x0 0xff010000 0x0 0x1000>;
 143                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 144                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 145                 clock-names = "i2s_clk", "i2s_hclk";
 146                 dmas = <&dmac 14>, <&dmac 15>;
 147                 #dma-cells = <2>;
 148                 dma-names = "tx", "rx";
 149                 status = "disabled";
 150         };
 151
 152         i2s2: i2s@ff020000 {
 153                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 154                 reg = <0x0 0xff020000 0x0 0x1000>;
 155                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 157                 clock-names = "i2s_clk", "i2s_hclk";
 158                 dmas = <&dmac 0>, <&dmac 1>;
 159                 #dma-cells = <2>;
 160                 dma-names = "tx", "rx";
 161                 pinctrl-names = "default", "sleep";
 162                 pinctrl-0 = <&i2s2m0_mclk
 163                              &i2s2m0_sclk
 164                              &i2s2m0_lrcktx
 165                              &i2s2m0_lrckrx
 166                              &i2s2m0_sdo
 167                              &i2s2m0_sdi>;
 168                 pinctrl-1 = <&i2s2m0_sleep>;
 169                 status = "disabled";
 170         };
 171
 172         spdif: spdif@ff030000 {
 173                 compatible = "rockchip,rk3328-spdif";
 174                 reg = <0x0 0xff030000 0x0 0x1000>;
 175                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 177                 clock-names = "mclk", "hclk";
 178                 dmas = <&dmac 10>;
 179                 #dma-cells = <1>;
 180                 dma-names = "tx";
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&spdifm2_tx>;
 183                 status = "disabled";
 184         };
 185
 186         grf: syscon@ff100000 {
 187                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 188                 reg = <0x0 0xff100000 0x0 0x1000>;
 189                 #address-cells = <1>;
 190                 #size-cells = <1>;
 191
 192                 io_domains: io-domains {
 193                         compatible = "rockchip,rk3328-io-voltage-domain";
 194                         status = "disabled";
 195                 };
 196         };
 197
 198         uart0: serial@ff110000 {
 199                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 200                 reg = <0x0 0xff110000 0x0 0x100>;
 201                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 203                 clock-names = "baudclk", "apb_pclk";
 204                 reg-shift = <2>;
 205                 reg-io-width = <4>;
 206                 dmas = <&dmac 2>, <&dmac 3>;
 207                 #dma-cells = <2>;
 208                 pinctrl-names = "default";
 209                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 210                 status = "disabled";
 211         };
 212
 213         uart1: serial@ff120000 {
 214                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 215                 reg = <0x0 0xff120000 0x0 0x100>;
 216                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 217                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 218                 clock-names = "sclk_uart", "pclk_uart";
 219                 reg-shift = <2>;
 220                 reg-io-width = <4>;
 221                 dmas = <&dmac 4>, <&dmac 5>;
 222                 #dma-cells = <2>;
 223                 pinctrl-names = "default";
 224                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 225                 status = "disabled";
 226         };
 227
 228         uart2: serial@ff130000 {
 229                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 230                 reg = <0x0 0xff130000 0x0 0x100>;
 231                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 233                 clock-names = "baudclk", "apb_pclk";
 234                 clock-frequency = <24000000>;
 235                 reg-shift = <2>;
 236                 reg-io-width = <4>;
 237                 dmas = <&dmac 6>, <&dmac 7>;
 238                 #dma-cells = <2>;
 239                 pinctrl-names = "default";
 240                 pinctrl-0 = <&uart2m1_xfer>;
 241                 status = "disabled";
 242         };
 243
 244         pmu: power-management@ff140000 {
 245                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 246                 reg = <0x0 0xff140000 0x0 0x1000>;
 247         };
 248
 249         i2c0: i2c@ff150000 {
 250                 compatible = "rockchip,rk3328-i2c";
 251                 reg = <0x0 0xff150000 0x0 0x1000>;
 252                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 253                 #address-cells = <1>;
 254                 #size-cells = <0>;
 255                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 256                 clock-names = "i2c", "pclk";
 257                 pinctrl-names = "default";
 258                 pinctrl-0 = <&i2c0_xfer>;
 259                 status = "disabled";
 260         };
 261
 262         i2c1: i2c@ff160000 {
 263                 compatible = "rockchip,rk3328-i2c";
 264                 reg = <0x0 0xff160000 0x0 0x1000>;
 265                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 266                 #address-cells = <1>;
 267                 #size-cells = <0>;
 268                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 269                 clock-names = "i2c", "pclk";
 270                 pinctrl-names = "default";
 271                 pinctrl-0 = <&i2c1_xfer>;
 272                 status = "disabled";
 273         };
 274
 275         i2c2: i2c@ff170000 {
 276                 compatible = "rockchip,rk3328-i2c";
 277                 reg = <0x0 0xff170000 0x0 0x1000>;
 278                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 279                 #address-cells = <1>;
 280                 #size-cells = <0>;
 281                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 282                 clock-names = "i2c", "pclk";
 283                 pinctrl-names = "default";
 284                 pinctrl-0 = <&i2c2_xfer>;
 285                 status = "disabled";
 286         };
 287
 288         i2c3: i2c@ff180000 {
 289                 compatible = "rockchip,rk3328-i2c";
 290                 reg = <0x0 0xff180000 0x0 0x1000>;
 291                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 295                 clock-names = "i2c", "pclk";
 296                 pinctrl-names = "default";
 297                 pinctrl-0 = <&i2c3_xfer>;
 298                 status = "disabled";
 299         };
 300
 301         spi0: spi@ff190000 {
 302                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 303                 reg = <0x0 0xff190000 0x0 0x1000>;
 304                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 308                 clock-names = "spiclk", "apb_pclk";
 309                 dmas = <&dmac 8>, <&dmac 9>;
 310                 #dma-cells = <2>;
 311                 dma-names = "tx", "rx";
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 314                 status = "disabled";
 315         };
 316
 317         wdt: watchdog@ff1a0000 {
 318                 compatible = "snps,dw-wdt";
 319                 reg = <0x0 0xff1a0000 0x0 0x100>;
 320                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 321                 status = "disabled";
 322         };
 323
 324         amba {
 325                 compatible = "simple-bus";
 326                 #address-cells = <2>;
 327                 #size-cells = <2>;
 328                 ranges;
 329
 330                 dmac: dmac@ff1f0000 {
 331                         compatible = "arm,pl330", "arm,primecell";
 332                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 333                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 334                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 335                         clocks = <&cru ACLK_DMAC>;
 336                         clock-names = "apb_pclk";
 337                         #dma-cells = <1>;
 338                 };
 339         };
 340
 341         saradc: saradc@ff280000 {
 342                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 343                 reg = <0x0 0xff280000 0x0 0x100>;
 344                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 345                 #io-channel-cells = <1>;
 346                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 347                 clock-names = "saradc", "apb_pclk";
 348                 resets = <&cru SRST_SARADC_P>;
 349                 reset-names = "saradc-apb";
 350                 status = "disabled";
 351         };
 352
 353         cru: clock-controller@ff440000 {
 354                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 355                 reg = <0x0 0xff440000 0x0 0x1000>;
 356                 rockchip,grf = <&grf>;
 357                 #clock-cells = <1>;
 358                 #reset-cells = <1>;
 359                 assigned-clocks =
 360                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 361                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 362                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 363                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 364                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 365                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 366                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 367                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 368                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 369                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 370                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 371                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 372                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 373                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 374                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 375                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 376                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 377                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 378                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 379                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 380                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 381                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 382                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 383                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 384                 assigned-clock-parents =
 385                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 386                         <&cru PLL_GPLL>, <&xin24m>,
 387                         <&xin24m>, <&xin24m>;
 388                 assigned-clock-rates =
 389                         <0>, <61440000>,
 390                         <0>, <24000000>,
 391                         <24000000>, <24000000>,
 392                         <15000000>, <15000000>,
 393                         <100000000>, <100000000>,
 394                         <100000000>, <100000000>,
 395                         <50000000>, <100000000>,
 396                         <100000000>, <100000000>,
 397                         <50000000>, <50000000>,
 398                         <50000000>, <50000000>,
 399                         <24000000>, <600000000>,
 400                         <491520000>, <1200000000>,
 401                         <150000000>, <75000000>,
 402                         <75000000>, <150000000>,
 403                         <75000000>, <75000000>,
 404                         <300000000>, <100000000>,
 405                         <300000000>, <200000000>,
 406                         <400000000>, <500000000>,
 407                         <200000000>, <300000000>,
 408                         <300000000>, <250000000>,
 409                         <200000000>, <100000000>,
 410                         <24000000>, <100000000>,
 411                         <150000000>, <50000000>,
 412                         <32768>, <32768>;
 413         };
 414
 415         sdmmc: rksdmmc@ff500000 {
 416                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 417                 reg = <0x0 0xff500000 0x0 0x4000>;
 418                 clock-freq-min-max = <400000 150000000>;
 419                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 420                 clock-names = "biu", "ciu";
 421                 fifo-depth = <0x100>;
 422                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 423                 status = "disabled";
 424         };
 425
 426         sdio: dwmmc@ff510000 {
 427                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 428                 reg = <0x0 0xff510000 0x0 0x4000>;
 429                 clock-freq-min-max = <400000 150000000>;
 430                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 431                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 432                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 433                 fifo-depth = <0x100>;
 434                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 435                 status = "disabled";
 436         };
 437
 438         emmc: rksdmmc@ff520000 {
 439                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 440                 reg = <0x0 0xff520000 0x0 0x4000>;
 441                 clock-freq-min-max = <400000 150000000>;
 442                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 443                 clock-names = "biu", "ciu";
 444                 fifo-depth = <0x100>;
 445                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 446                 status = "disabled";
 447         };
 448
 449         sdmmc_ext: rksdmmc@ff5f0000 {
 450                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 451                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 452                 clock-freq-min-max = <400000 150000000>;
 453                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 454                 clock-names = "biu", "ciu";
 455                 fifo-depth = <0x100>;
 456                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 457                 status = "disabled";
 458         };
 459
 460         gic: interrupt-controller@ffb70000 {
 461                 compatible = "arm,gic-400";
 462                 #interrupt-cells = <3>;
 463                 #address-cells = <0>;
 464                 interrupt-controller;
 465                 reg = <0x0 0xff811000 0 0x1000>,
 466                       <0x0 0xff812000 0 0x2000>,
 467                       <0x0 0xff814000 0 0x2000>,
 468                       <0x0 0xff816000 0 0x2000>;
 469                 interrupts = <GIC_PPI 9
 470                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 471         };
 472
 473         pinctrl: pinctrl {
 474                 compatible = "rockchip,rk3328-pinctrl";
 475                 rockchip,grf = <&grf>;
 476                 #address-cells = <2>;
 477                 #size-cells = <2>;
 478                 ranges;
 479
 480                 gpio0: gpio0@ff210000 {
 481                         compatible = "rockchip,gpio-bank";
 482                         reg = <0x0 0xff210000 0x0 0x100>;
 483                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&cru PCLK_GPIO0>;
 485
 486                         gpio-controller;
 487                         #gpio-cells = <2>;
 488
 489                         interrupt-controller;
 490                         #interrupt-cells = <2>;
 491                 };
 492
 493                 gpio1: gpio1@ff220000 {
 494                         compatible = "rockchip,gpio-bank";
 495                         reg = <0x0 0xff220000 0x0 0x100>;
 496                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 497                         clocks = <&cru PCLK_GPIO1>;
 498
 499                         gpio-controller;
 500                         #gpio-cells = <2>;
 501
 502                         interrupt-controller;
 503                         #interrupt-cells = <2>;
 504                 };
 505
 506                 gpio2: gpio2@ff230000 {
 507                         compatible = "rockchip,gpio-bank";
 508                         reg = <0x0 0xff230000 0x0 0x100>;
 509                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&cru PCLK_GPIO2>;
 511
 512                         gpio-controller;
 513                         #gpio-cells = <2>;
 514
 515                         interrupt-controller;
 516                         #interrupt-cells = <2>;
 517                 };
 518
 519                 gpio3: gpio3@ff240000 {
 520                         compatible = "rockchip,gpio-bank";
 521                         reg = <0x0 0xff240000 0x0 0x100>;
 522                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 523                         clocks = <&cru PCLK_GPIO3>;
 524
 525                         gpio-controller;
 526                         #gpio-cells = <2>;
 527
 528                         interrupt-controller;
 529                         #interrupt-cells = <2>;
 530                 };
 531
 532                 pcfg_pull_up: pcfg-pull-up {
 533                         bias-pull-up;
 534                 };
 535
 536                 pcfg_pull_down: pcfg-pull-down {
 537                         bias-pull-down;
 538                 };
 539
 540                 pcfg_pull_none: pcfg-pull-none {
 541                         bias-disable;
 542                 };
 543
 544                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 545                         bias-disable;
 546                         drive-strength = <2>;
 547                 };
 548
 549                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 550                         bias-pull-up;
 551                         drive-strength = <2>;
 552                 };
 553
 554                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 555                         bias-pull-up;
 556                         drive-strength = <4>;
 557                 };
 558
 559                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 560                         bias-disable;
 561                         drive-strength = <4>;
 562                 };
 563
 564                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 565                         bias-pull-down;
 566                         drive-strength = <4>;
 567                 };
 568
 569                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 570                         bias-disable;
 571                         drive-strength = <8>;
 572                 };
 573
 574                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 575                         bias-pull-up;
 576                         drive-strength = <8>;
 577                 };
 578
 579                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 580                         bias-disable;
 581                         drive-strength = <12>;
 582                 };
 583
 584                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 585                         bias-pull-up;
 586                         drive-strength = <12>;
 587                 };
 588
 589                 pcfg_output_high: pcfg-output-high {
 590                         output-high;
 591                 };
 592
 593                 pcfg_output_low: pcfg-output-low {
 594                         output-low;
 595                 };
 596
 597                 pcfg_input_high: pcfg-input-high {
 598                         bias-pull-up;
 599                         input-enable;
 600                 };
 601
 602                 pcfg_input: pcfg-input {
 603                         input-enable;
 604                 };
 605
 606                 i2c0 {
 607                         i2c0_xfer: i2c0-xfer {
 608                                 rockchip,pins =
 609                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 610                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 611                         };
 612                 };
 613
 614                 i2c1 {
 615                         i2c1_xfer: i2c1-xfer {
 616                                 rockchip,pins =
 617                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 618                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 619                         };
 620                 };
 621
 622                 i2c2 {
 623                         i2c2_xfer: i2c2-xfer {
 624                                 rockchip,pins =
 625                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 626                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 627                         };
 628                 };
 629
 630                 i2c3 {
 631                         i2c3_xfer: i2c3-xfer {
 632                                 rockchip,pins =
 633                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 634                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 635                         };
 636                         i2c3_gpio: i2c3-gpio {
 637                                 rockchip,pins =
 638                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 639                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 640                         };
 641                 };
 642
 643                 hdmi_i2c {
 644                         hdmii2c_xfer: hdmii2c-xfer {
 645                                 rockchip,pins =
 646                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 647                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 648                         };
 649                 };
 650
 651                 uart0 {
 652                         uart0_xfer: uart0-xfer {
 653                                 rockchip,pins =
 654                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 655                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 656                         };
 657
 658                         uart0_cts: uart0-cts {
 659                                 rockchip,pins =
 660                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 661                         };
 662
 663                         uart0_rts: uart0-rts {
 664                                 rockchip,pins =
 665                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 666                         };
 667
 668                         uart0_rts_gpio: uart0-rts-gpio {
 669                                 rockchip,pins =
 670                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 671                         };
 672                 };
 673
 674                 uart1 {
 675                         uart1_xfer: uart1-xfer {
 676                                 rockchip,pins =
 677                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 678                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 679                         };
 680
 681                         uart1_cts: uart1-cts {
 682                                 rockchip,pins =
 683                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 684                         };
 685
 686                         uart1_rts: uart1-rts {
 687                                 rockchip,pins =
 688                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 689                         };
 690
 691                         uart1_rts_gpio: uart1-rts-gpio {
 692                                 rockchip,pins =
 693                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 694                         };
 695                 };
 696
 697                 uart2-0 {
 698                         uart2m0_xfer: uart2m0-xfer {
 699                                 rockchip,pins =
 700                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 701                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 702                         };
 703                 };
 704
 705                 uart2-1 {
 706                         uart2m1_xfer: uart2m1-xfer {
 707                                 rockchip,pins =
 708                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 709                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 710                         };
 711                 };
 712
 713                 spi0-0 {
 714                         spi0m0_clk: spi0m0-clk {
 715                                 rockchip,pins =
 716                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 717                         };
 718
 719                         spi0m0_cs0: spi0m0-cs0 {
 720                                 rockchip,pins =
 721                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 722                         };
 723
 724                         spi0m0_tx: spi0m0-tx {
 725                                 rockchip,pins =
 726                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 727                         };
 728
 729                         spi0m0_rx: spi0m0-rx {
 730                                 rockchip,pins =
 731                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 732                         };
 733
 734                         spi0m0_cs1: spi0m0-cs1 {
 735                                 rockchip,pins =
 736                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 737                         };
 738                 };
 739
 740                 spi0-1 {
 741                         spi0m1_clk: spi0m1-clk {
 742                                 rockchip,pins =
 743                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
 744                         };
 745
 746                         spi0m1_cs0: spi0m1-cs0 {
 747                                 rockchip,pins =
 748                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
 749                         };
 750
 751                         spi0m1_tx: spi0m1-tx {
 752                                 rockchip,pins =
 753                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
 754                         };
 755
 756                         spi0m1_rx: spi0m1-rx {
 757                                 rockchip,pins =
 758                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
 759                         };
 760
 761                         spi0m1_cs1: spi0m1-cs1 {
 762                                 rockchip,pins =
 763                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
 764                         };
 765                 };
 766
 767                 spi0-2 {
 768                         spi0m2_clk: spi0m2-clk {
 769                                 rockchip,pins =
 770                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
 771                         };
 772
 773                         spi0m2_cs0: spi0m2-cs0 {
 774                                 rockchip,pins =
 775                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
 776                         };
 777
 778                         spi0m2_tx: spi0m2-tx {
 779                                 rockchip,pins =
 780                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
 781                         };
 782
 783                         spi0m2_rx: spi0m2-rx {
 784                                 rockchip,pins =
 785                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
 786                         };
 787                 };
 788
 789                 i2s1 {
 790                         i2s1_mclk: i2s1-mclk {
 791                                 rockchip,pins =
 792                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
 793                         };
 794
 795                         i2s1_sclk: i2s1-sclk {
 796                                 rockchip,pins =
 797                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 798                         };
 799
 800                         i2s1_lrckrx: i2s1-lrckrx {
 801                                 rockchip,pins =
 802                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
 803                         };
 804
 805                         i2s1_lrcktx: i2s1-lrcktx {
 806                                 rockchip,pins =
 807                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 808                         };
 809
 810                         i2s1_sdi: i2s1-sdi {
 811                                 rockchip,pins =
 812                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 813                         };
 814
 815                         i2s1_sdo: i2s1-sdo {
 816                                 rockchip,pins =
 817                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
 818                         };
 819
 820                         i2s1_sdio1: i2s1-sdio1 {
 821                                 rockchip,pins =
 822                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
 823                         };
 824
 825                         i2s1_sdio2: i2s1-sdio2 {
 826                                 rockchip,pins =
 827                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
 828                         };
 829
 830                         i2s1_sdio3: i2s1-sdio3 {
 831                                 rockchip,pins =
 832                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
 833                         };
 834
 835                         i2s1_sleep: i2s1-sleep {
 836                                 rockchip,pins =
 837                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
 838                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
 839                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
 840                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
 841                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
 842                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
 843                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
 844                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
 845                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
 846                         };
 847                 };
 848
 849                 i2s2-0 {
 850                         i2s2m0_mclk: i2s2m0-mclk {
 851                                 rockchip,pins =
 852                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 853                         };
 854
 855                         i2s2m0_sclk: i2s2m0-sclk {
 856                                 rockchip,pins =
 857                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
 858                         };
 859
 860                         i2s2m0_lrckrx: i2s2m0-lrckrx {
 861                                 rockchip,pins =
 862                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
 863                         };
 864
 865                         i2s2m0_lrcktx: i2s2m0-lrcktx {
 866                                 rockchip,pins =
 867                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
 868                         };
 869
 870                         i2s2m0_sdi: i2s2m0-sdi {
 871                                 rockchip,pins =
 872                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
 873                         };
 874
 875                         i2s2m0_sdo: i2s2m0-sdo {
 876                                 rockchip,pins =
 877                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
 878                         };
 879
 880                         i2s2m0_sleep: i2s2m0-sleep {
 881                                 rockchip,pins =
 882                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 883                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
 884                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
 885                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
 886                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
 887                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
 888                         };
 889                 };
 890
 891                 i2s2-1 {
 892                         i2s2m1_mclk: i2s2m1-mclk {
 893                                 rockchip,pins =
 894                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 895                         };
 896
 897                         i2s2m1_sclk: i2s2m1-sclk {
 898                                 rockchip,pins =
 899                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
 900                         };
 901
 902                         i2s2m1_lrckrx: i2sm1-lrckrx {
 903                                 rockchip,pins =
 904                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
 905                         };
 906
 907                         i2s2m1_lrcktx: i2s2m1-lrcktx {
 908                                 rockchip,pins =
 909                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
 910                         };
 911
 912                         i2s2m1_sdi: i2s2m1-sdi {
 913                                 rockchip,pins =
 914                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
 915                         };
 916
 917                         i2s2m1_sdo: i2s2m1-sdo {
 918                                 rockchip,pins =
 919                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
 920                         };
 921
 922                         i2s2m1_sleep: i2s2m1-sleep {
 923                                 rockchip,pins =
 924                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 925                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
 926                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
 927                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
 928                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
 929                         };
 930                 };
 931
 932                 spdif-0 {
 933                         spdifm0_tx: spdifm0-tx {
 934                                 rockchip,pins =
 935                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
 936                         };
 937                 };
 938
 939                 spdif-1 {
 940                         spdifm1_tx: spdifm1-tx {
 941                                 rockchip,pins =
 942                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 943                         };
 944                 };
 945
 946                 spdif-2 {
 947                         spdifm2_tx: spdifm2-tx {
 948                                 rockchip,pins =
 949                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
 950                         };
 951                 };
 952
 953                 sdmmc0-0 {
 954                         sdmmc0m0_pwren: sdmmc0m0-pwren {
 955                                 rockchip,pins =
 956                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
 957                         };
 958
 959                         sdmmc0m0_gpio: sdmmc0m0-gpio {
 960                                 rockchip,pins =
 961                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
 962                         };
 963                 };
 964
 965                 sdmmc0-1 {
 966                         sdmmc0m1_pwren: sdmmc0m1-pwren {
 967                                 rockchip,pins =
 968                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
 969                         };
 970
 971                         sdmmc0m1_gpio: sdmmc0m1-gpio {
 972                                 rockchip,pins =
 973                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
 974                         };
 975                 };
 976
 977                 sdmmc0 {
 978                         sdmmc0_clk: sdmmc0-clk {
 979                                 rockchip,pins =
 980                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
 981                         };
 982
 983                         sdmmc0_cmd: sdmmc0-cmd {
 984                                 rockchip,pins =
 985                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
 986                         };
 987
 988                         sdmmc0_dectn: sdmmc0-dectn {
 989                                 rockchip,pins =
 990                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
 991                         };
 992
 993                         sdmmc0_wrprt: sdmmc0-wrprt {
 994                                 rockchip,pins =
 995                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
 996                         };
 997
 998                         sdmmc0_bus1: sdmmc0-bus1 {
 999                                 rockchip,pins =
1000                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1001                         };
1002
1003                         sdmmc0_bus4: sdmmc0-bus4 {
1004                                 rockchip,pins =
1005                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1006                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1007                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1008                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1009                         };
1010
1011                         sdmmc0_gpio: sdmmc0-gpio {
1012                                 rockchip,pins =
1013                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1014                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1015                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1016                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1017                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1018                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1019                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1020                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1021                         };
1022                 };
1023
1024                 sdmmc0ext {
1025                         sdmmc0ext_clk: sdmmc0ext-clk {
1026                                 rockchip,pins =
1027                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1028                         };
1029
1030                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1031                                 rockchip,pins =
1032                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1033                         };
1034
1035                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1036                                 rockchip,pins =
1037                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1038                         };
1039
1040                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1041                                 rockchip,pins =
1042                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1043                         };
1044
1045                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1046                                 rockchip,pins =
1047                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1048                         };
1049
1050                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1051                                 rockchip,pins =
1052                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1053                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1054                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1055                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1056                         };
1057
1058                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1059                                 rockchip,pins =
1060                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1061                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1062                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1063                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1064                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1065                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1066                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1067                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1068                         };
1069                 };
1070
1071                 sdmmc1 {
1072                         sdmmc1_clk: sdmmc1-clk {
1073                                 rockchip,pins =
1074                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1075                         };
1076
1077                         sdmmc1_cmd: sdmmc1-cmd {
1078                                 rockchip,pins =
1079                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1080                         };
1081
1082                         sdmmc1_pwren: sdmmc1-pwren {
1083                                 rockchip,pins =
1084                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1085                         };
1086
1087                         sdmmc1_wrprt: sdmmc1-wrprt {
1088                                 rockchip,pins =
1089                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1090                         };
1091
1092                         sdmmc1_dectn: sdmmc1-dectn {
1093                                 rockchip,pins =
1094                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1095                         };
1096
1097                         sdmmc1_bus1: sdmmc1-bus1 {
1098                                 rockchip,pins =
1099                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1100                         };
1101
1102                         sdmmc1_bus4: sdmmc1-bus4 {
1103                                 rockchip,pins =
1104                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1105                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1106                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1107                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1108                         };
1109
1110                         sdmmc1_gpio: sdmmc1-gpio {
1111                                 rockchip,pins =
1112                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1113                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1114                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1115                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1116                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1117                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1118                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1119                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1120                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1121                         };
1122                 };
1123
1124                 emmc {
1125                         emmc_clk: emmc-clk {
1126                                 rockchip,pins =
1127                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1128                         };
1129
1130                         emmc_cmd: emmc-cmd {
1131                                 rockchip,pins =
1132                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1133                         };
1134
1135                         emmc_pwren: emmc-pwren {
1136                                 rockchip,pins =
1137                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1138                         };
1139
1140                         emmc_rstnout: emmc-rstnout {
1141                                 rockchip,pins =
1142                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1143                         };
1144
1145                         emmc_bus1: emmc-bus1 {
1146                                 rockchip,pins =
1147                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1148                         };
1149
1150                         emmc_bus4: emmc-bus4 {
1151                                 rockchip,pins =
1152                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1153                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1154                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1155                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1156                         };
1157
1158                         emmc_bus8: emmc-bus8 {
1159                                 rockchip,pins =
1160                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1161                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1162                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1163                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1164                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1165                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1166                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1167                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1168                         };
1169                 };
1170
1171                 pwm0 {
1172                         pwm0_pin: pwm0-pin {
1173                                 rockchip,pins =
1174                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1175                         };
1176                 };
1177
1178                 pwm1 {
1179                         pwm1_pin: pwm1-pin {
1180                                 rockchip,pins =
1181                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1182                         };
1183                 };
1184
1185                 pwm2 {
1186                         pwm2_pin: pwm2-pin {
1187                                 rockchip,pins =
1188                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1189                         };
1190                 };
1191
1192                 pwmir {
1193                         pwmir_pin: pwmir-pin {
1194                                 rockchip,pins =
1195                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1196                         };
1197                 };
1198
1199                 gmac-0 {
1200                         rgmiim0_pins: rgmiim0-pins {
1201                                 rockchip,pins =
1202                                         /* mac_txclk */
1203                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1204                                         /* mac_rxclk */
1205                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1206                                         /* mac_mdio */
1207                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1208                                         /* mac_txen */
1209                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1210                                         /* mac_clk */
1211                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1212                                         /* mac_rxdv */
1213                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1214                                         /* mac_mdc */
1215                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1216                                         /* mac_rxd1 */
1217                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1218                                         /* mac_rxd0 */
1219                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1220                                         /* mac_txd1 */
1221                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1222                                         /* mac_txd0 */
1223                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1224                                         /* mac_rxd3 */
1225                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1226                                         /* mac_rxd2 */
1227                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1228                                         /* mac_txd3 */
1229                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1230                                         /* mac_txd2 */
1231                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1232                         };
1233
1234                         rmiim0_pins: rmiim0-pins {
1235                                 rockchip,pins =
1236                                         /* mac_mdio */
1237                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1238                                         /* mac_txen */
1239                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1240                                         /* mac_clk */
1241                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1242                                         /* mac_rxer */
1243                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1244                                         /* mac_rxdv */
1245                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1246                                         /* mac_mdc */
1247                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1248                                         /* mac_rxd1 */
1249                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1250                                         /* mac_rxd0 */
1251                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1252                                         /* mac_txd1 */
1253                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1254                                         /* mac_txd0 */
1255                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1256                         };
1257                 };
1258
1259                 gmac-1 {
1260                         rgmiim1_pins: rgmiim1-pins {
1261                                 rockchip,pins =
1262                                         /* mac_txclk */
1263                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1264                                         /* mac_rxclk */
1265                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1266                                         /* mac_mdio */
1267                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1268                                         /* mac_txen */
1269                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1270                                         /* mac_clk */
1271                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1272                                         /* mac_rxdv */
1273                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1274                                         /* mac_mdc */
1275                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1276                                         /* mac_rxd1 */
1277                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1278                                         /* mac_rxd0 */
1279                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1280                                         /* mac_txd1 */
1281                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1282                                         /* mac_txd0 */
1283                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1284                                         /* mac_rxd3 */
1285                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1286                                         /* mac_rxd2 */
1287                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1288                                         /* mac_txd3 */
1289                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1290                                         /* mac_txd2 */
1291                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1292
1293                                         /* mac_txclk */
1294                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1295                                         /* mac_txen */
1296                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1297                                         /* mac_clk */
1298                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1299                                         /* mac_txd1 */
1300                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1301                                         /* mac_txd0 */
1302                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1303                                         /* mac_txd3 */
1304                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1305                                         /* mac_txd2 */
1306                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1307                         };
1308
1309                         rmiim1_pins: rmiim1-pins {
1310                                 rockchip,pins =
1311                                         /* mac_mdio */
1312                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1313                                         /* mac_txen */
1314                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1315                                         /* mac_clk */
1316                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1317                                         /* mac_rxer */
1318                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1319                                         /* mac_rxdv */
1320                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1321                                         /* mac_mdc */
1322                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1323                                         /* mac_rxd1 */
1324                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1325                                         /* mac_rxd0 */
1326                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1327                                         /* mac_txd1 */
1328                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1329                                         /* mac_txd0 */
1330                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1331
1332                                         /* mac_mdio */
1333                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1334                                         /* mac_txen */
1335                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1336                                         /* mac_clk */
1337                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1338                                         /* mac_mdc */
1339                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1340                                         /* mac_txd1 */
1341                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1342                                         /* mac_txd0 */
1343                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1344                         };
1345                 };
1346
1347                 gmac2phy {
1348                         fephyled_speed100: fephyled-speed100 {
1349                                 rockchip,pins =
1350                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1351                         };
1352
1353                         fephyled_speed10: fephyled-speed10 {
1354                                 rockchip,pins =
1355                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1356                         };
1357
1358                         fephyled_duplex: fephyled-duplex {
1359                                 rockchip,pins =
1360                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1361                         };
1362
1363                         fephyled_rxm0: fephyled-rxm0 {
1364                                 rockchip,pins =
1365                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1366                         };
1367
1368                         fephyled_txm0: fephyled-txm0 {
1369                                 rockchip,pins =
1370                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1371                         };
1372
1373                         fephyled_linkm0: fephyled-linkm0 {
1374                                 rockchip,pins =
1375                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1376                         };
1377
1378                         fephyled_rxm1: fephyled-rxm1 {
1379                                 rockchip,pins =
1380                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1381                         };
1382
1383                         fephyled_txm1: fephyled-txm1 {
1384                                 rockchip,pins =
1385                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1386                         };
1387
1388                         fephyled_linkm1: fephyled-linkm1 {
1389                                 rockchip,pins =
1390                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1391                         };
1392                 };
1393
1394                 tsadc_pin {
1395                         tsadc_int: tsadc-int {
1396                                 rockchip,pins =
1397                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1398                         };
1399                         tsadc_gpio: tsadc-gpio {
1400                                 rockchip,pins =
1401                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1402                         };
1403                 };
1404
1405                 hdmi_pin {
1406                         hdmi_cec: hdmi-cec {
1407                                 rockchip,pins =
1408                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1409                         };
1410
1411                         hdmi_hpd: hdmi-hpd {
1412                                 rockchip,pins =
1413                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1414                         };
1415                 };
1416
1417                 cif-0 {
1418                         dvp_d2d9_m0:dvp-d2d9-m0 {
1419                                 rockchip,pins =
1420                                         /* cif_d0 */
1421                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1422                                         /* cif_d1 */
1423                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1424                                         /* cif_d2 */
1425                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1426                                         /* cif_d3 */
1427                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1428                                         /* cif_d4 */
1429                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1430                                         /* cif_d5m0 */
1431                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1432                                         /* cif_d6m0 */
1433                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1434                                         /* cif_d7m0 */
1435                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1436                                         /* cif_href */
1437                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1438                                         /* cif_vsync */
1439                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1440                                         /* cif_clkoutm0 */
1441                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1442                                         /* cif_clkin */
1443                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1444                         };
1445                 };
1446
1447                 cif-1 {
1448                         dvp_d2d9_m1:dvp-d2d9-m1 {
1449                                 rockchip,pins =
1450                                         /* cif_d0 */
1451                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1452                                         /* cif_d1 */
1453                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1454                                         /* cif_d2 */
1455                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1456                                         /* cif_d3 */
1457                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1458                                         /* cif_d4 */
1459                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1460                                         /* cif_d5m1 */
1461                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1462                                         /* cif_d6m1 */
1463                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1464                                         /* cif_d7m1 */
1465                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1466                                         /* cif_href */
1467                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1468                                         /* cif_vsync */
1469                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1470                                         /* cif_clkoutm1 */
1471                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1472                                         /* cif_clkin */
1473                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1474                         };
1475                 };
1476         };
1477 };