2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/clock/rk3328-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
14 compatible = "rockchip,rk3328";
16 interrupt-parent = <&gic>;
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
42 // clocks = <&cru ARMCLK>;
43 operating-points-v2 = <&cpu0_opp_table>;
47 compatible = "arm,cortex-a53", "arm,armv8";
49 enable-method = "psci";
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
59 compatible = "arm,cortex-a53", "arm,armv8";
61 enable-method = "psci";
65 cpu0_opp_table: opp_table0 {
66 compatible = "operating-points-v2";
70 opp-hz = /bits/ 64 <408000000>;
71 opp-microvolt = <950000>;
72 clock-latency-ns = <40000>;
76 opp-hz = /bits/ 64 <600000000>;
77 opp-microvolt = <950000>;
78 clock-latency-ns = <40000>;
81 opp-hz = /bits/ 64 <816000000>;
82 opp-microvolt = <1000000>;
83 clock-latency-ns = <40000>;
86 opp-hz = /bits/ 64 <1008000000>;
87 opp-microvolt = <1100000>;
88 clock-latency-ns = <40000>;
91 opp-hz = /bits/ 64 <1200000000>;
92 opp-microvolt = <1225000>;
93 clock-latency-ns = <40000>;
96 opp-hz = /bits/ 64 <1296000000>;
97 opp-microvolt = <1300000>;
98 clock-latency-ns = <40000>;
103 compatible = "arm,cortex-a53-pmu";
104 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
112 compatible = "arm,psci-1.0";
117 compatible = "arm,armv8-timer";
118 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
120 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
125 compatible = "fixed-clock";
127 clock-frequency = <24000000>;
128 clock-output-names = "xin24m";
132 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
133 reg = <0x0 0xff000000 0x0 0x1000>;
134 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
135 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
136 clock-names = "i2s_clk", "i2s_hclk";
137 dmas = <&dmac 11>, <&dmac 12>;
139 dma-names = "tx", "rx";
144 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
145 reg = <0x0 0xff010000 0x0 0x1000>;
146 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
148 clock-names = "i2s_clk", "i2s_hclk";
149 dmas = <&dmac 14>, <&dmac 15>;
151 dma-names = "tx", "rx";
156 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
157 reg = <0x0 0xff020000 0x0 0x1000>;
158 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
160 clock-names = "i2s_clk", "i2s_hclk";
161 dmas = <&dmac 0>, <&dmac 1>;
163 dma-names = "tx", "rx";
164 pinctrl-names = "default", "sleep";
165 pinctrl-0 = <&i2s2m0_mclk
171 pinctrl-1 = <&i2s2m0_sleep>;
175 spdif: spdif@ff030000 {
176 compatible = "rockchip,rk3328-spdif";
177 reg = <0x0 0xff030000 0x0 0x1000>;
178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
180 clock-names = "mclk", "hclk";
184 pinctrl-names = "default";
185 pinctrl-0 = <&spdifm2_tx>;
189 grf: syscon@ff100000 {
191 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
192 reg = <0x0 0xff100000 0x0 0x1000>;
193 #address-cells = <1>;
196 io_domains: io-domains {
197 compatible = "rockchip,rk3328-io-voltage-domain";
202 uart0: serial@ff110000 {
203 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
204 reg = <0x0 0xff110000 0x0 0x100>;
205 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
207 clock-names = "baudclk", "apb_pclk";
210 dmas = <&dmac 2>, <&dmac 3>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
217 uart1: serial@ff120000 {
218 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
219 reg = <0x0 0xff120000 0x0 0x100>;
220 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
222 clock-names = "sclk_uart", "pclk_uart";
225 dmas = <&dmac 4>, <&dmac 5>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
232 uart2: serial@ff130000 {
233 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
234 reg = <0x0 0xff130000 0x0 0x100>;
235 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
237 clock-names = "baudclk", "apb_pclk";
238 clock-frequency = <24000000>;
241 dmas = <&dmac 6>, <&dmac 7>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&uart2m1_xfer>;
248 pmu: power-management@ff140000 {
249 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
250 reg = <0x0 0xff140000 0x0 0x1000>;
254 compatible = "rockchip,rk3328-i2c";
255 reg = <0x0 0xff150000 0x0 0x1000>;
256 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
257 #address-cells = <1>;
259 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
260 clock-names = "i2c", "pclk";
261 pinctrl-names = "default";
262 pinctrl-0 = <&i2c0_xfer>;
267 compatible = "rockchip,rk3328-i2c";
268 reg = <0x0 0xff160000 0x0 0x1000>;
269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
270 #address-cells = <1>;
272 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
273 clock-names = "i2c", "pclk";
274 pinctrl-names = "default";
275 pinctrl-0 = <&i2c1_xfer>;
280 compatible = "rockchip,rk3328-i2c";
281 reg = <0x0 0xff170000 0x0 0x1000>;
282 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
283 #address-cells = <1>;
285 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
286 clock-names = "i2c", "pclk";
287 pinctrl-names = "default";
288 pinctrl-0 = <&i2c2_xfer>;
293 compatible = "rockchip,rk3328-i2c";
294 reg = <0x0 0xff180000 0x0 0x1000>;
295 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
296 #address-cells = <1>;
298 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
299 clock-names = "i2c", "pclk";
300 pinctrl-names = "default";
301 pinctrl-0 = <&i2c3_xfer>;
306 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
307 reg = <0x0 0xff190000 0x0 0x1000>;
308 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
309 #address-cells = <1>;
311 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
312 clock-names = "spiclk", "apb_pclk";
313 dmas = <&dmac 8>, <&dmac 9>;
315 dma-names = "tx", "rx";
316 pinctrl-names = "default";
317 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
321 wdt: watchdog@ff1a0000 {
322 compatible = "snps,dw-wdt";
323 reg = <0x0 0xff1a0000 0x0 0x100>;
324 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
329 compatible = "simple-bus";
330 #address-cells = <2>;
334 dmac: dmac@ff1f0000 {
335 compatible = "arm,pl330", "arm,primecell";
336 reg = <0x0 0xff1f0000 0x0 0x4000>;
337 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&cru ACLK_DMAC>;
340 clock-names = "apb_pclk";
345 saradc: saradc@ff280000 {
346 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
347 reg = <0x0 0xff280000 0x0 0x100>;
348 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
349 #io-channel-cells = <1>;
350 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
351 clock-names = "saradc", "apb_pclk";
352 resets = <&cru SRST_SARADC_P>;
353 reset-names = "saradc-apb";
359 compatible = "rockchip,rk3328-dmc", "syscon";
360 reg = <0x0 0xff400000 0x0 0x1000>;
363 cru: clock-controller@ff440000 {
364 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
365 reg = <0x0 0xff440000 0x0 0x1000>;
366 rockchip,grf = <&grf>;
370 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
371 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
372 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
373 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
374 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
375 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
376 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
377 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
378 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
379 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
380 <&cru SCLK_WIFI>, <&cru ARMCLK>,
381 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
382 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
383 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
384 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
385 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
386 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
387 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
388 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
389 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
390 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
391 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
392 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
393 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
394 assigned-clock-parents =
395 <&cru HDMIPHY>, <&cru PLL_APLL>,
396 <&cru PLL_GPLL>, <&xin24m>,
397 <&xin24m>, <&xin24m>;
398 assigned-clock-rates =
401 <24000000>, <24000000>,
402 <15000000>, <15000000>,
403 <100000000>, <100000000>,
404 <100000000>, <100000000>,
405 <50000000>, <100000000>,
406 <100000000>, <100000000>,
407 <50000000>, <50000000>,
408 <50000000>, <50000000>,
409 <24000000>, <600000000>,
410 <491520000>, <1200000000>,
411 <150000000>, <75000000>,
412 <75000000>, <150000000>,
413 <75000000>, <75000000>,
414 <300000000>, <100000000>,
415 <300000000>, <200000000>,
416 <400000000>, <500000000>,
417 <200000000>, <300000000>,
418 <300000000>, <250000000>,
419 <200000000>, <100000000>,
420 <24000000>, <100000000>,
421 <150000000>, <50000000>,
425 sdmmc: rksdmmc@ff500000 {
426 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
427 reg = <0x0 0xff500000 0x0 0x4000>;
428 max-frequency = <150000000>;
429 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
430 clock-names = "biu", "ciu";
431 fifo-depth = <0x100>;
432 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
436 sdio: dwmmc@ff510000 {
437 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
438 reg = <0x0 0xff510000 0x0 0x4000>;
439 max-frequency = <150000000>;
440 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
441 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
442 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
443 fifo-depth = <0x100>;
444 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
448 emmc: rksdmmc@ff520000 {
449 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
450 reg = <0x0 0xff520000 0x0 0x4000>;
451 max-frequency = <150000000>;
452 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
453 clock-names = "biu", "ciu";
454 fifo-depth = <0x100>;
455 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
459 gmac2io: ethernet@ff540000 {
460 compatible = "rockchip,rk3328-gmac";
461 reg = <0x0 0xff540000 0x0 0x10000>;
462 rockchip,grf = <&grf>;
463 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
464 interrupt-names = "macirq";
465 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
466 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
467 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
469 clock-names = "stmmaceth", "mac_clk_rx",
470 "mac_clk_tx", "clk_mac_ref",
471 "clk_mac_refout", "aclk_mac",
473 resets = <&cru SRST_GMAC2IO_A>;
474 reset-names = "stmmaceth";
478 usb_host0_ehci: usb@ff5c0000 {
479 compatible = "generic-ehci";
480 reg = <0x0 0xff5c0000 0x0 0x10000>;
481 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
485 usb_host0_ohci: usb@ff5d0000 {
486 compatible = "generic-ohci";
487 reg = <0x0 0xff5d0000 0x0 0x10000>;
488 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
492 usb20_otg: usb@ff580000 {
493 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
495 reg = <0x0 0xff580000 0x0 0x40000>;
496 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
502 sdmmc_ext: rksdmmc@ff5f0000 {
503 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
504 reg = <0x0 0xff5f0000 0x0 0x4000>;
505 max-frequency = <150000000>;
506 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
507 clock-names = "biu", "ciu";
508 fifo-depth = <0x100>;
509 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
513 usb_host0_xhci: usb@ff600000 {
514 compatible = "rockchip,rk3328-xhci";
515 reg = <0x0 0xff600000 0x0 0x100000>;
516 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
517 snps,dis-enblslpm-quirk;
518 snps,phyif-utmi-bits = <16>;
519 snps,dis-u2-freeclk-exists-quirk;
520 snps,dis-u2-susphy-quirk;
524 gic: interrupt-controller@ffb70000 {
525 compatible = "arm,gic-400";
526 #interrupt-cells = <3>;
527 #address-cells = <0>;
528 interrupt-controller;
529 reg = <0x0 0xff811000 0 0x1000>,
530 <0x0 0xff812000 0 0x2000>,
531 <0x0 0xff814000 0 0x2000>,
532 <0x0 0xff816000 0 0x2000>;
533 interrupts = <GIC_PPI 9
534 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
538 compatible = "rockchip,rk3328-pinctrl";
539 rockchip,grf = <&grf>;
540 #address-cells = <2>;
544 gpio0: gpio0@ff210000 {
545 compatible = "rockchip,gpio-bank";
546 reg = <0x0 0xff210000 0x0 0x100>;
547 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru PCLK_GPIO0>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
557 gpio1: gpio1@ff220000 {
558 compatible = "rockchip,gpio-bank";
559 reg = <0x0 0xff220000 0x0 0x100>;
560 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&cru PCLK_GPIO1>;
566 interrupt-controller;
567 #interrupt-cells = <2>;
570 gpio2: gpio2@ff230000 {
571 compatible = "rockchip,gpio-bank";
572 reg = <0x0 0xff230000 0x0 0x100>;
573 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cru PCLK_GPIO2>;
579 interrupt-controller;
580 #interrupt-cells = <2>;
583 gpio3: gpio3@ff240000 {
584 compatible = "rockchip,gpio-bank";
585 reg = <0x0 0xff240000 0x0 0x100>;
586 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cru PCLK_GPIO3>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
596 pcfg_pull_up: pcfg-pull-up {
600 pcfg_pull_down: pcfg-pull-down {
604 pcfg_pull_none: pcfg-pull-none {
608 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
610 drive-strength = <2>;
613 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
615 drive-strength = <2>;
618 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
620 drive-strength = <4>;
623 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
625 drive-strength = <4>;
628 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
630 drive-strength = <4>;
633 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
635 drive-strength = <8>;
638 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
640 drive-strength = <8>;
643 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
645 drive-strength = <12>;
648 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
650 drive-strength = <12>;
653 pcfg_output_high: pcfg-output-high {
657 pcfg_output_low: pcfg-output-low {
661 pcfg_input_high: pcfg-input-high {
666 pcfg_input: pcfg-input {
671 i2c0_xfer: i2c0-xfer {
673 <2 24 RK_FUNC_1 &pcfg_pull_none>,
674 <2 25 RK_FUNC_1 &pcfg_pull_none>;
679 i2c1_xfer: i2c1-xfer {
681 <2 4 RK_FUNC_2 &pcfg_pull_none>,
682 <2 5 RK_FUNC_2 &pcfg_pull_none>;
687 i2c2_xfer: i2c2-xfer {
689 <2 13 RK_FUNC_1 &pcfg_pull_none>,
690 <2 14 RK_FUNC_1 &pcfg_pull_none>;
695 i2c3_xfer: i2c3-xfer {
697 <0 5 RK_FUNC_2 &pcfg_pull_none>,
698 <0 6 RK_FUNC_2 &pcfg_pull_none>;
700 i2c3_gpio: i2c3-gpio {
702 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
703 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
708 hdmii2c_xfer: hdmii2c-xfer {
710 <0 5 RK_FUNC_1 &pcfg_pull_none>,
711 <0 6 RK_FUNC_1 &pcfg_pull_none>;
716 uart0_xfer: uart0-xfer {
718 <1 9 RK_FUNC_1 &pcfg_pull_up>,
719 <1 8 RK_FUNC_1 &pcfg_pull_none>;
722 uart0_cts: uart0-cts {
724 <1 11 RK_FUNC_1 &pcfg_pull_none>;
727 uart0_rts: uart0-rts {
729 <1 10 RK_FUNC_1 &pcfg_pull_none>;
732 uart0_rts_gpio: uart0-rts-gpio {
734 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
739 uart1_xfer: uart1-xfer {
741 <3 4 RK_FUNC_4 &pcfg_pull_up>,
742 <3 6 RK_FUNC_4 &pcfg_pull_none>;
745 uart1_cts: uart1-cts {
747 <3 7 RK_FUNC_4 &pcfg_pull_none>;
750 uart1_rts: uart1-rts {
752 <3 5 RK_FUNC_4 &pcfg_pull_none>;
755 uart1_rts_gpio: uart1-rts-gpio {
757 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
762 uart2m0_xfer: uart2m0-xfer {
764 <1 0 RK_FUNC_2 &pcfg_pull_up>,
765 <1 1 RK_FUNC_2 &pcfg_pull_none>;
770 uart2m1_xfer: uart2m1-xfer {
772 <2 0 RK_FUNC_1 &pcfg_pull_up>,
773 <2 1 RK_FUNC_1 &pcfg_pull_none>;
778 spi0m0_clk: spi0m0-clk {
780 <2 8 RK_FUNC_1 &pcfg_pull_up>;
783 spi0m0_cs0: spi0m0-cs0 {
785 <2 11 RK_FUNC_1 &pcfg_pull_up>;
788 spi0m0_tx: spi0m0-tx {
790 <2 9 RK_FUNC_1 &pcfg_pull_up>;
793 spi0m0_rx: spi0m0-rx {
795 <2 10 RK_FUNC_1 &pcfg_pull_up>;
798 spi0m0_cs1: spi0m0-cs1 {
800 <2 12 RK_FUNC_1 &pcfg_pull_up>;
805 spi0m1_clk: spi0m1-clk {
807 <3 23 RK_FUNC_2 &pcfg_pull_up>;
810 spi0m1_cs0: spi0m1-cs0 {
812 <3 26 RK_FUNC_2 &pcfg_pull_up>;
815 spi0m1_tx: spi0m1-tx {
817 <3 25 RK_FUNC_2 &pcfg_pull_up>;
820 spi0m1_rx: spi0m1-rx {
822 <3 24 RK_FUNC_2 &pcfg_pull_up>;
825 spi0m1_cs1: spi0m1-cs1 {
827 <3 27 RK_FUNC_2 &pcfg_pull_up>;
832 spi0m2_clk: spi0m2-clk {
834 <3 0 RK_FUNC_4 &pcfg_pull_up>;
837 spi0m2_cs0: spi0m2-cs0 {
839 <3 8 RK_FUNC_3 &pcfg_pull_up>;
842 spi0m2_tx: spi0m2-tx {
844 <3 1 RK_FUNC_4 &pcfg_pull_up>;
847 spi0m2_rx: spi0m2-rx {
849 <3 2 RK_FUNC_4 &pcfg_pull_up>;
854 i2s1_mclk: i2s1-mclk {
856 <2 15 RK_FUNC_1 &pcfg_pull_none>;
859 i2s1_sclk: i2s1-sclk {
861 <2 18 RK_FUNC_1 &pcfg_pull_none>;
864 i2s1_lrckrx: i2s1-lrckrx {
866 <2 16 RK_FUNC_1 &pcfg_pull_none>;
869 i2s1_lrcktx: i2s1-lrcktx {
871 <2 17 RK_FUNC_1 &pcfg_pull_none>;
876 <2 19 RK_FUNC_1 &pcfg_pull_none>;
881 <2 23 RK_FUNC_1 &pcfg_pull_none>;
884 i2s1_sdio1: i2s1-sdio1 {
886 <2 20 RK_FUNC_1 &pcfg_pull_none>;
889 i2s1_sdio2: i2s1-sdio2 {
891 <2 21 RK_FUNC_1 &pcfg_pull_none>;
894 i2s1_sdio3: i2s1-sdio3 {
896 <2 22 RK_FUNC_1 &pcfg_pull_none>;
899 i2s1_sleep: i2s1-sleep {
901 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
902 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
903 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
904 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
905 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
906 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
907 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
908 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
909 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
914 i2s2m0_mclk: i2s2m0-mclk {
916 <1 21 RK_FUNC_1 &pcfg_pull_none>;
919 i2s2m0_sclk: i2s2m0-sclk {
921 <1 22 RK_FUNC_1 &pcfg_pull_none>;
924 i2s2m0_lrckrx: i2s2m0-lrckrx {
926 <1 26 RK_FUNC_1 &pcfg_pull_none>;
929 i2s2m0_lrcktx: i2s2m0-lrcktx {
931 <1 23 RK_FUNC_1 &pcfg_pull_none>;
934 i2s2m0_sdi: i2s2m0-sdi {
936 <1 24 RK_FUNC_1 &pcfg_pull_none>;
939 i2s2m0_sdo: i2s2m0-sdo {
941 <1 25 RK_FUNC_1 &pcfg_pull_none>;
944 i2s2m0_sleep: i2s2m0-sleep {
946 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
947 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
948 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
949 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
950 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
951 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
956 i2s2m1_mclk: i2s2m1-mclk {
958 <1 21 RK_FUNC_1 &pcfg_pull_none>;
961 i2s2m1_sclk: i2s2m1-sclk {
963 <3 0 RK_FUNC_6 &pcfg_pull_none>;
966 i2s2m1_lrckrx: i2sm1-lrckrx {
968 <3 8 RK_FUNC_6 &pcfg_pull_none>;
971 i2s2m1_lrcktx: i2s2m1-lrcktx {
973 <3 8 RK_FUNC_4 &pcfg_pull_none>;
976 i2s2m1_sdi: i2s2m1-sdi {
978 <3 2 RK_FUNC_6 &pcfg_pull_none>;
981 i2s2m1_sdo: i2s2m1-sdo {
983 <3 1 RK_FUNC_6 &pcfg_pull_none>;
986 i2s2m1_sleep: i2s2m1-sleep {
988 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
989 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
990 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
991 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
992 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
997 spdifm0_tx: spdifm0-tx {
999 <0 27 RK_FUNC_1 &pcfg_pull_none>;
1004 spdifm1_tx: spdifm1-tx {
1006 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1011 spdifm2_tx: spdifm2-tx {
1013 <0 2 RK_FUNC_2 &pcfg_pull_none>;
1018 sdmmc0m0_pwren: sdmmc0m0-pwren {
1020 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1023 sdmmc0m0_gpio: sdmmc0m0-gpio {
1025 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1030 sdmmc0m1_pwren: sdmmc0m1-pwren {
1032 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1035 sdmmc0m1_gpio: sdmmc0m1-gpio {
1037 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1042 sdmmc0_clk: sdmmc0-clk {
1044 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1047 sdmmc0_cmd: sdmmc0-cmd {
1049 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1052 sdmmc0_dectn: sdmmc0-dectn {
1054 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1057 sdmmc0_wrprt: sdmmc0-wrprt {
1059 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1062 sdmmc0_bus1: sdmmc0-bus1 {
1064 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1067 sdmmc0_bus4: sdmmc0-bus4 {
1069 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1070 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1071 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1072 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1075 sdmmc0_gpio: sdmmc0-gpio {
1077 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1078 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1079 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1080 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1081 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1082 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1083 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1084 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1089 sdmmc0ext_clk: sdmmc0ext-clk {
1091 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1094 sdmmc0ext_cmd: sdmmc0ext-cmd {
1096 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1099 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1101 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1104 sdmmc0ext_dectn: sdmmc0ext-dectn {
1106 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1109 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1111 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1114 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1116 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1117 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1118 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1119 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1122 sdmmc0ext_gpio: sdmmc0ext-gpio {
1124 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1125 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1126 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1127 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1128 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1129 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1130 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1131 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1136 sdmmc1_clk: sdmmc1-clk {
1138 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1141 sdmmc1_cmd: sdmmc1-cmd {
1143 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1146 sdmmc1_pwren: sdmmc1-pwren {
1148 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1151 sdmmc1_wrprt: sdmmc1-wrprt {
1153 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1156 sdmmc1_dectn: sdmmc1-dectn {
1158 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1161 sdmmc1_bus1: sdmmc1-bus1 {
1163 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1166 sdmmc1_bus4: sdmmc1-bus4 {
1168 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1169 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1170 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1171 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1174 sdmmc1_gpio: sdmmc1-gpio {
1176 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1177 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1178 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1179 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1180 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1181 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1182 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1183 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1184 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1189 emmc_clk: emmc-clk {
1191 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1194 emmc_cmd: emmc-cmd {
1196 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1199 emmc_pwren: emmc-pwren {
1201 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1204 emmc_rstnout: emmc-rstnout {
1206 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1209 emmc_bus1: emmc-bus1 {
1211 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1214 emmc_bus4: emmc-bus4 {
1216 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1217 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1218 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1219 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1222 emmc_bus8: emmc-bus8 {
1224 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1225 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1226 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1227 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1228 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1229 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1230 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1231 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1236 pwm0_pin: pwm0-pin {
1238 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1243 pwm1_pin: pwm1-pin {
1245 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1250 pwm2_pin: pwm2-pin {
1252 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1257 pwmir_pin: pwmir-pin {
1259 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1264 rgmiim0_pins: rgmiim0-pins {
1267 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1269 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1271 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1273 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1275 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1277 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1279 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1281 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1283 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1285 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1287 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1289 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1291 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1293 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1295 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1298 rmiim0_pins: rmiim0-pins {
1301 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1303 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1305 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1307 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1309 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1311 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1313 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1315 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1317 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1319 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1324 rgmiim1_pins: rgmiim1-pins {
1327 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1329 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1331 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1333 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1335 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1337 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1339 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1341 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1343 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1345 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1347 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1349 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1351 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1353 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1355 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1358 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1360 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1362 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1364 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1366 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1368 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1370 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1373 rmiim1_pins: rmiim1-pins {
1376 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1378 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1380 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1382 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1384 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1386 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1388 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1390 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1392 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1394 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1397 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1399 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1401 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1403 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1405 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1407 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1412 fephyled_speed100: fephyled-speed100 {
1414 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1417 fephyled_speed10: fephyled-speed10 {
1419 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1422 fephyled_duplex: fephyled-duplex {
1424 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1427 fephyled_rxm0: fephyled-rxm0 {
1429 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1432 fephyled_txm0: fephyled-txm0 {
1434 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1437 fephyled_linkm0: fephyled-linkm0 {
1439 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1442 fephyled_rxm1: fephyled-rxm1 {
1444 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1447 fephyled_txm1: fephyled-txm1 {
1449 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1452 fephyled_linkm1: fephyled-linkm1 {
1454 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1459 tsadc_int: tsadc-int {
1461 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1463 tsadc_gpio: tsadc-gpio {
1465 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1470 hdmi_cec: hdmi-cec {
1472 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1475 hdmi_hpd: hdmi-hpd {
1477 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1482 dvp_d2d9_m0:dvp-d2d9-m0 {
1485 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1487 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1489 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1491 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1493 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1495 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1497 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1499 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1501 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1503 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1505 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1507 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1512 dvp_d2d9_m1:dvp-d2d9-m1 {
1515 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1517 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1519 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1521 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1523 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1525 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1527 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1529 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1531 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1533 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1535 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1537 <3 2 RK_FUNC_2 &pcfg_pull_none>;