1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
13 compatible = "rockchip,rk3328";
15 interrupt-parent = <&gic>;
38 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
41 // clocks = <&cru ARMCLK>;
42 operating-points-v2 = <&cpu0_opp_table>;
46 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
52 compatible = "arm,cortex-a53", "arm,armv8";
54 enable-method = "psci";
58 compatible = "arm,cortex-a53", "arm,armv8";
60 enable-method = "psci";
64 cpu0_opp_table: opp_table0 {
65 compatible = "operating-points-v2";
69 opp-hz = /bits/ 64 <408000000>;
70 opp-microvolt = <950000>;
71 clock-latency-ns = <40000>;
75 opp-hz = /bits/ 64 <600000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
80 opp-hz = /bits/ 64 <816000000>;
81 opp-microvolt = <1000000>;
82 clock-latency-ns = <40000>;
85 opp-hz = /bits/ 64 <1008000000>;
86 opp-microvolt = <1100000>;
87 clock-latency-ns = <40000>;
90 opp-hz = /bits/ 64 <1200000000>;
91 opp-microvolt = <1225000>;
92 clock-latency-ns = <40000>;
95 opp-hz = /bits/ 64 <1296000000>;
96 opp-microvolt = <1300000>;
97 clock-latency-ns = <40000>;
102 compatible = "arm,cortex-a53-pmu";
103 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
111 compatible = "arm,psci-1.0";
116 compatible = "arm,armv8-timer";
117 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
120 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
124 compatible = "fixed-clock";
126 clock-frequency = <24000000>;
127 clock-output-names = "xin24m";
131 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
132 reg = <0x0 0xff000000 0x0 0x1000>;
133 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
135 clock-names = "i2s_clk", "i2s_hclk";
136 dmas = <&dmac 11>, <&dmac 12>;
138 dma-names = "tx", "rx";
143 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
144 reg = <0x0 0xff010000 0x0 0x1000>;
145 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
147 clock-names = "i2s_clk", "i2s_hclk";
148 dmas = <&dmac 14>, <&dmac 15>;
150 dma-names = "tx", "rx";
155 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
156 reg = <0x0 0xff020000 0x0 0x1000>;
157 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
159 clock-names = "i2s_clk", "i2s_hclk";
160 dmas = <&dmac 0>, <&dmac 1>;
162 dma-names = "tx", "rx";
163 pinctrl-names = "default", "sleep";
164 pinctrl-0 = <&i2s2m0_mclk
170 pinctrl-1 = <&i2s2m0_sleep>;
174 spdif: spdif@ff030000 {
175 compatible = "rockchip,rk3328-spdif";
176 reg = <0x0 0xff030000 0x0 0x1000>;
177 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
179 clock-names = "mclk", "hclk";
183 pinctrl-names = "default";
184 pinctrl-0 = <&spdifm2_tx>;
188 grf: syscon@ff100000 {
190 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
191 reg = <0x0 0xff100000 0x0 0x1000>;
193 io_domains: io-domains {
194 compatible = "rockchip,rk3328-io-voltage-domain";
199 uart0: serial@ff110000 {
200 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
201 reg = <0x0 0xff110000 0x0 0x100>;
202 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
204 clock-names = "baudclk", "apb_pclk";
207 dmas = <&dmac 2>, <&dmac 3>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
214 uart1: serial@ff120000 {
215 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
216 reg = <0x0 0xff120000 0x0 0x100>;
217 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
219 clock-names = "sclk_uart", "pclk_uart";
222 dmas = <&dmac 4>, <&dmac 5>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
229 uart2: serial@ff130000 {
230 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
231 reg = <0x0 0xff130000 0x0 0x100>;
232 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
234 clock-names = "baudclk", "apb_pclk";
235 clock-frequency = <24000000>;
238 dmas = <&dmac 6>, <&dmac 7>;
240 pinctrl-names = "default";
241 pinctrl-0 = <&uart2m1_xfer>;
245 pmu: power-management@ff140000 {
246 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
247 reg = <0x0 0xff140000 0x0 0x1000>;
251 compatible = "rockchip,rk3328-i2c";
252 reg = <0x0 0xff150000 0x0 0x1000>;
253 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
254 #address-cells = <1>;
256 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
257 clock-names = "i2c", "pclk";
258 pinctrl-names = "default";
259 pinctrl-0 = <&i2c0_xfer>;
264 compatible = "rockchip,rk3328-i2c";
265 reg = <0x0 0xff160000 0x0 0x1000>;
266 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
267 #address-cells = <1>;
269 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
270 clock-names = "i2c", "pclk";
271 pinctrl-names = "default";
272 pinctrl-0 = <&i2c1_xfer>;
277 compatible = "rockchip,rk3328-i2c";
278 reg = <0x0 0xff170000 0x0 0x1000>;
279 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
280 #address-cells = <1>;
282 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
283 clock-names = "i2c", "pclk";
284 pinctrl-names = "default";
285 pinctrl-0 = <&i2c2_xfer>;
290 compatible = "rockchip,rk3328-i2c";
291 reg = <0x0 0xff180000 0x0 0x1000>;
292 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
293 #address-cells = <1>;
295 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
296 clock-names = "i2c", "pclk";
297 pinctrl-names = "default";
298 pinctrl-0 = <&i2c3_xfer>;
303 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
304 reg = <0x0 0xff190000 0x0 0x1000>;
305 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
306 #address-cells = <1>;
308 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
309 clock-names = "spiclk", "apb_pclk";
310 dmas = <&dmac 8>, <&dmac 9>;
312 dma-names = "tx", "rx";
313 pinctrl-names = "default";
314 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
318 wdt: watchdog@ff1a0000 {
319 compatible = "snps,dw-wdt";
320 reg = <0x0 0xff1a0000 0x0 0x100>;
321 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
326 compatible = "simple-bus";
327 #address-cells = <2>;
331 dmac: dmac@ff1f0000 {
332 compatible = "arm,pl330", "arm,primecell";
333 reg = <0x0 0xff1f0000 0x0 0x4000>;
334 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&cru ACLK_DMAC>;
337 clock-names = "apb_pclk";
342 saradc: saradc@ff280000 {
343 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
344 reg = <0x0 0xff280000 0x0 0x100>;
345 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
346 #io-channel-cells = <1>;
347 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
348 clock-names = "saradc", "apb_pclk";
349 resets = <&cru SRST_SARADC_P>;
350 reset-names = "saradc-apb";
356 compatible = "rockchip,rk3328-dmc", "syscon";
357 reg = <0x0 0xff400000 0x0 0x1000>;
360 cru: clock-controller@ff440000 {
361 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
362 reg = <0x0 0xff440000 0x0 0x1000>;
363 rockchip,grf = <&grf>;
367 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
368 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
369 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
370 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
371 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
372 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
373 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
374 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
375 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
376 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
377 <&cru SCLK_WIFI>, <&cru ARMCLK>,
378 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
379 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
380 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
381 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
382 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
383 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
384 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
385 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
386 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
387 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
388 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
389 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
390 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
391 assigned-clock-parents =
392 <&cru HDMIPHY>, <&cru PLL_APLL>,
393 <&cru PLL_GPLL>, <&xin24m>,
394 <&xin24m>, <&xin24m>;
395 assigned-clock-rates =
398 <24000000>, <24000000>,
399 <15000000>, <15000000>,
400 <100000000>, <100000000>,
401 <100000000>, <100000000>,
402 <50000000>, <100000000>,
403 <100000000>, <100000000>,
404 <50000000>, <50000000>,
405 <50000000>, <50000000>,
406 <24000000>, <600000000>,
407 <491520000>, <1200000000>,
408 <150000000>, <75000000>,
409 <75000000>, <150000000>,
410 <75000000>, <75000000>,
411 <300000000>, <100000000>,
412 <300000000>, <200000000>,
413 <400000000>, <500000000>,
414 <200000000>, <300000000>,
415 <300000000>, <250000000>,
416 <200000000>, <100000000>,
417 <24000000>, <100000000>,
418 <150000000>, <50000000>,
422 sdmmc: rksdmmc@ff500000 {
423 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
424 reg = <0x0 0xff500000 0x0 0x4000>;
425 max-frequency = <150000000>;
426 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
427 clock-names = "biu", "ciu";
428 fifo-depth = <0x100>;
429 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
433 sdio: dwmmc@ff510000 {
434 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
435 reg = <0x0 0xff510000 0x0 0x4000>;
436 max-frequency = <150000000>;
437 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
438 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
439 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
440 fifo-depth = <0x100>;
441 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
445 emmc: rksdmmc@ff520000 {
446 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
447 reg = <0x0 0xff520000 0x0 0x4000>;
448 max-frequency = <150000000>;
449 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
450 clock-names = "biu", "ciu";
451 fifo-depth = <0x100>;
452 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
456 gmac2io: ethernet@ff540000 {
457 compatible = "rockchip,rk3328-gmac";
458 reg = <0x0 0xff540000 0x0 0x10000>;
459 rockchip,grf = <&grf>;
460 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "macirq";
462 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
463 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
464 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
466 clock-names = "stmmaceth", "mac_clk_rx",
467 "mac_clk_tx", "clk_mac_ref",
468 "clk_mac_refout", "aclk_mac",
470 resets = <&cru SRST_GMAC2IO_A>;
471 reset-names = "stmmaceth";
475 usb_host0_ehci: usb@ff5c0000 {
476 compatible = "generic-ehci";
477 reg = <0x0 0xff5c0000 0x0 0x10000>;
478 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
482 usb_host0_ohci: usb@ff5d0000 {
483 compatible = "generic-ohci";
484 reg = <0x0 0xff5d0000 0x0 0x10000>;
485 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
489 usb20_otg: usb@ff580000 {
490 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
492 reg = <0x0 0xff580000 0x0 0x40000>;
493 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
499 sdmmc_ext: rksdmmc@ff5f0000 {
500 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
501 reg = <0x0 0xff5f0000 0x0 0x4000>;
502 max-frequency = <150000000>;
503 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
504 clock-names = "biu", "ciu";
505 fifo-depth = <0x100>;
506 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
510 usb_host0_xhci: usb@ff600000 {
511 compatible = "rockchip,rk3328-xhci";
512 reg = <0x0 0xff600000 0x0 0x100000>;
513 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
514 snps,dis-enblslpm-quirk;
515 snps,phyif-utmi-bits = <16>;
516 snps,dis-u2-freeclk-exists-quirk;
517 snps,dis-u2-susphy-quirk;
521 gic: interrupt-controller@ffb70000 {
522 compatible = "arm,gic-400";
523 #interrupt-cells = <3>;
524 #address-cells = <0>;
525 interrupt-controller;
526 reg = <0x0 0xff811000 0 0x1000>,
527 <0x0 0xff812000 0 0x2000>,
528 <0x0 0xff814000 0 0x2000>,
529 <0x0 0xff816000 0 0x2000>;
530 interrupts = <GIC_PPI 9
531 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
535 compatible = "rockchip,rk3328-pinctrl";
536 rockchip,grf = <&grf>;
537 #address-cells = <2>;
541 gpio0: gpio0@ff210000 {
542 compatible = "rockchip,gpio-bank";
543 reg = <0x0 0xff210000 0x0 0x100>;
544 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&cru PCLK_GPIO0>;
550 interrupt-controller;
551 #interrupt-cells = <2>;
554 gpio1: gpio1@ff220000 {
555 compatible = "rockchip,gpio-bank";
556 reg = <0x0 0xff220000 0x0 0x100>;
557 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cru PCLK_GPIO1>;
563 interrupt-controller;
564 #interrupt-cells = <2>;
567 gpio2: gpio2@ff230000 {
568 compatible = "rockchip,gpio-bank";
569 reg = <0x0 0xff230000 0x0 0x100>;
570 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cru PCLK_GPIO2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
580 gpio3: gpio3@ff240000 {
581 compatible = "rockchip,gpio-bank";
582 reg = <0x0 0xff240000 0x0 0x100>;
583 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cru PCLK_GPIO3>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
593 pcfg_pull_up: pcfg-pull-up {
597 pcfg_pull_down: pcfg-pull-down {
601 pcfg_pull_none: pcfg-pull-none {
605 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
607 drive-strength = <2>;
610 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
612 drive-strength = <2>;
615 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
617 drive-strength = <4>;
620 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
622 drive-strength = <4>;
625 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
627 drive-strength = <4>;
630 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
632 drive-strength = <8>;
635 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
637 drive-strength = <8>;
640 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
642 drive-strength = <12>;
645 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
647 drive-strength = <12>;
650 pcfg_output_high: pcfg-output-high {
654 pcfg_output_low: pcfg-output-low {
658 pcfg_input_high: pcfg-input-high {
663 pcfg_input: pcfg-input {
668 i2c0_xfer: i2c0-xfer {
670 <2 24 RK_FUNC_1 &pcfg_pull_none>,
671 <2 25 RK_FUNC_1 &pcfg_pull_none>;
676 i2c1_xfer: i2c1-xfer {
678 <2 4 RK_FUNC_2 &pcfg_pull_none>,
679 <2 5 RK_FUNC_2 &pcfg_pull_none>;
684 i2c2_xfer: i2c2-xfer {
686 <2 13 RK_FUNC_1 &pcfg_pull_none>,
687 <2 14 RK_FUNC_1 &pcfg_pull_none>;
692 i2c3_xfer: i2c3-xfer {
694 <0 5 RK_FUNC_2 &pcfg_pull_none>,
695 <0 6 RK_FUNC_2 &pcfg_pull_none>;
697 i2c3_gpio: i2c3-gpio {
699 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
700 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
705 hdmii2c_xfer: hdmii2c-xfer {
707 <0 5 RK_FUNC_1 &pcfg_pull_none>,
708 <0 6 RK_FUNC_1 &pcfg_pull_none>;
713 uart0_xfer: uart0-xfer {
715 <1 9 RK_FUNC_1 &pcfg_pull_up>,
716 <1 8 RK_FUNC_1 &pcfg_pull_none>;
719 uart0_cts: uart0-cts {
721 <1 11 RK_FUNC_1 &pcfg_pull_none>;
724 uart0_rts: uart0-rts {
726 <1 10 RK_FUNC_1 &pcfg_pull_none>;
729 uart0_rts_gpio: uart0-rts-gpio {
731 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
736 uart1_xfer: uart1-xfer {
738 <3 4 RK_FUNC_4 &pcfg_pull_up>,
739 <3 6 RK_FUNC_4 &pcfg_pull_none>;
742 uart1_cts: uart1-cts {
744 <3 7 RK_FUNC_4 &pcfg_pull_none>;
747 uart1_rts: uart1-rts {
749 <3 5 RK_FUNC_4 &pcfg_pull_none>;
752 uart1_rts_gpio: uart1-rts-gpio {
754 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
759 uart2m0_xfer: uart2m0-xfer {
761 <1 0 RK_FUNC_2 &pcfg_pull_up>,
762 <1 1 RK_FUNC_2 &pcfg_pull_none>;
767 uart2m1_xfer: uart2m1-xfer {
769 <2 0 RK_FUNC_1 &pcfg_pull_up>,
770 <2 1 RK_FUNC_1 &pcfg_pull_none>;
775 spi0m0_clk: spi0m0-clk {
777 <2 8 RK_FUNC_1 &pcfg_pull_up>;
780 spi0m0_cs0: spi0m0-cs0 {
782 <2 11 RK_FUNC_1 &pcfg_pull_up>;
785 spi0m0_tx: spi0m0-tx {
787 <2 9 RK_FUNC_1 &pcfg_pull_up>;
790 spi0m0_rx: spi0m0-rx {
792 <2 10 RK_FUNC_1 &pcfg_pull_up>;
795 spi0m0_cs1: spi0m0-cs1 {
797 <2 12 RK_FUNC_1 &pcfg_pull_up>;
802 spi0m1_clk: spi0m1-clk {
804 <3 23 RK_FUNC_2 &pcfg_pull_up>;
807 spi0m1_cs0: spi0m1-cs0 {
809 <3 26 RK_FUNC_2 &pcfg_pull_up>;
812 spi0m1_tx: spi0m1-tx {
814 <3 25 RK_FUNC_2 &pcfg_pull_up>;
817 spi0m1_rx: spi0m1-rx {
819 <3 24 RK_FUNC_2 &pcfg_pull_up>;
822 spi0m1_cs1: spi0m1-cs1 {
824 <3 27 RK_FUNC_2 &pcfg_pull_up>;
829 spi0m2_clk: spi0m2-clk {
831 <3 0 RK_FUNC_4 &pcfg_pull_up>;
834 spi0m2_cs0: spi0m2-cs0 {
836 <3 8 RK_FUNC_3 &pcfg_pull_up>;
839 spi0m2_tx: spi0m2-tx {
841 <3 1 RK_FUNC_4 &pcfg_pull_up>;
844 spi0m2_rx: spi0m2-rx {
846 <3 2 RK_FUNC_4 &pcfg_pull_up>;
851 i2s1_mclk: i2s1-mclk {
853 <2 15 RK_FUNC_1 &pcfg_pull_none>;
856 i2s1_sclk: i2s1-sclk {
858 <2 18 RK_FUNC_1 &pcfg_pull_none>;
861 i2s1_lrckrx: i2s1-lrckrx {
863 <2 16 RK_FUNC_1 &pcfg_pull_none>;
866 i2s1_lrcktx: i2s1-lrcktx {
868 <2 17 RK_FUNC_1 &pcfg_pull_none>;
873 <2 19 RK_FUNC_1 &pcfg_pull_none>;
878 <2 23 RK_FUNC_1 &pcfg_pull_none>;
881 i2s1_sdio1: i2s1-sdio1 {
883 <2 20 RK_FUNC_1 &pcfg_pull_none>;
886 i2s1_sdio2: i2s1-sdio2 {
888 <2 21 RK_FUNC_1 &pcfg_pull_none>;
891 i2s1_sdio3: i2s1-sdio3 {
893 <2 22 RK_FUNC_1 &pcfg_pull_none>;
896 i2s1_sleep: i2s1-sleep {
898 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
899 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
900 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
901 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
902 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
903 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
904 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
905 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
906 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
911 i2s2m0_mclk: i2s2m0-mclk {
913 <1 21 RK_FUNC_1 &pcfg_pull_none>;
916 i2s2m0_sclk: i2s2m0-sclk {
918 <1 22 RK_FUNC_1 &pcfg_pull_none>;
921 i2s2m0_lrckrx: i2s2m0-lrckrx {
923 <1 26 RK_FUNC_1 &pcfg_pull_none>;
926 i2s2m0_lrcktx: i2s2m0-lrcktx {
928 <1 23 RK_FUNC_1 &pcfg_pull_none>;
931 i2s2m0_sdi: i2s2m0-sdi {
933 <1 24 RK_FUNC_1 &pcfg_pull_none>;
936 i2s2m0_sdo: i2s2m0-sdo {
938 <1 25 RK_FUNC_1 &pcfg_pull_none>;
941 i2s2m0_sleep: i2s2m0-sleep {
943 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
944 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
945 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
946 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
947 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
948 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
953 i2s2m1_mclk: i2s2m1-mclk {
955 <1 21 RK_FUNC_1 &pcfg_pull_none>;
958 i2s2m1_sclk: i2s2m1-sclk {
960 <3 0 RK_FUNC_6 &pcfg_pull_none>;
963 i2s2m1_lrckrx: i2sm1-lrckrx {
965 <3 8 RK_FUNC_6 &pcfg_pull_none>;
968 i2s2m1_lrcktx: i2s2m1-lrcktx {
970 <3 8 RK_FUNC_4 &pcfg_pull_none>;
973 i2s2m1_sdi: i2s2m1-sdi {
975 <3 2 RK_FUNC_6 &pcfg_pull_none>;
978 i2s2m1_sdo: i2s2m1-sdo {
980 <3 1 RK_FUNC_6 &pcfg_pull_none>;
983 i2s2m1_sleep: i2s2m1-sleep {
985 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
986 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
987 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
988 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
989 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
994 spdifm0_tx: spdifm0-tx {
996 <0 27 RK_FUNC_1 &pcfg_pull_none>;
1001 spdifm1_tx: spdifm1-tx {
1003 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1008 spdifm2_tx: spdifm2-tx {
1010 <0 2 RK_FUNC_2 &pcfg_pull_none>;
1015 sdmmc0m0_pwren: sdmmc0m0-pwren {
1017 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1020 sdmmc0m0_gpio: sdmmc0m0-gpio {
1022 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1027 sdmmc0m1_pwren: sdmmc0m1-pwren {
1029 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1032 sdmmc0m1_gpio: sdmmc0m1-gpio {
1034 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1039 sdmmc0_clk: sdmmc0-clk {
1041 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1044 sdmmc0_cmd: sdmmc0-cmd {
1046 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1049 sdmmc0_dectn: sdmmc0-dectn {
1051 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1054 sdmmc0_wrprt: sdmmc0-wrprt {
1056 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1059 sdmmc0_bus1: sdmmc0-bus1 {
1061 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1064 sdmmc0_bus4: sdmmc0-bus4 {
1066 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1067 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1068 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1069 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1072 sdmmc0_gpio: sdmmc0-gpio {
1074 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1075 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1076 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1077 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1078 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1079 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1080 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1081 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1086 sdmmc0ext_clk: sdmmc0ext-clk {
1088 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1091 sdmmc0ext_cmd: sdmmc0ext-cmd {
1093 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1096 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1098 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1101 sdmmc0ext_dectn: sdmmc0ext-dectn {
1103 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1106 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1108 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1111 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1113 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1114 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1115 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1116 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1119 sdmmc0ext_gpio: sdmmc0ext-gpio {
1121 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1122 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1123 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1124 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1125 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1126 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1127 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1128 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1133 sdmmc1_clk: sdmmc1-clk {
1135 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1138 sdmmc1_cmd: sdmmc1-cmd {
1140 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1143 sdmmc1_pwren: sdmmc1-pwren {
1145 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1148 sdmmc1_wrprt: sdmmc1-wrprt {
1150 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1153 sdmmc1_dectn: sdmmc1-dectn {
1155 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1158 sdmmc1_bus1: sdmmc1-bus1 {
1160 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1163 sdmmc1_bus4: sdmmc1-bus4 {
1165 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1166 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1167 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1168 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1171 sdmmc1_gpio: sdmmc1-gpio {
1173 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1174 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1175 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1176 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1177 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1178 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1179 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1180 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1181 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1186 emmc_clk: emmc-clk {
1188 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1191 emmc_cmd: emmc-cmd {
1193 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1196 emmc_pwren: emmc-pwren {
1198 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1201 emmc_rstnout: emmc-rstnout {
1203 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1206 emmc_bus1: emmc-bus1 {
1208 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1211 emmc_bus4: emmc-bus4 {
1213 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1214 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1215 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1216 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1219 emmc_bus8: emmc-bus8 {
1221 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1222 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1223 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1224 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1225 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1226 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1227 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1228 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1233 pwm0_pin: pwm0-pin {
1235 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1240 pwm1_pin: pwm1-pin {
1242 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1247 pwm2_pin: pwm2-pin {
1249 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1254 pwmir_pin: pwmir-pin {
1256 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1261 rgmiim0_pins: rgmiim0-pins {
1264 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1266 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1268 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1270 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1272 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1274 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1276 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1278 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1280 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1282 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1284 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1286 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1288 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1290 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1292 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1295 rmiim0_pins: rmiim0-pins {
1298 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1300 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1302 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1304 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1306 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1308 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1310 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1312 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1314 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1316 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1321 rgmiim1_pins: rgmiim1-pins {
1324 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1326 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1328 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1330 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1332 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1334 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1336 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1338 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1340 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1342 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1344 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1346 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1348 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1350 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1352 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1355 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1357 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1359 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1361 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1363 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1365 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1367 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1370 rmiim1_pins: rmiim1-pins {
1373 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1375 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1377 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1379 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1381 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1383 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1385 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1387 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1389 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1391 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1394 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1396 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1398 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1400 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1402 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1404 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1409 fephyled_speed100: fephyled-speed100 {
1411 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1414 fephyled_speed10: fephyled-speed10 {
1416 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1419 fephyled_duplex: fephyled-duplex {
1421 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1424 fephyled_rxm0: fephyled-rxm0 {
1426 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1429 fephyled_txm0: fephyled-txm0 {
1431 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1434 fephyled_linkm0: fephyled-linkm0 {
1436 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1439 fephyled_rxm1: fephyled-rxm1 {
1441 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1444 fephyled_txm1: fephyled-txm1 {
1446 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1449 fephyled_linkm1: fephyled-linkm1 {
1451 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1456 tsadc_int: tsadc-int {
1458 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1460 tsadc_gpio: tsadc-gpio {
1462 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1467 hdmi_cec: hdmi-cec {
1469 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1472 hdmi_hpd: hdmi-hpd {
1474 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1479 dvp_d2d9_m0:dvp-d2d9-m0 {
1482 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1484 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1486 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1488 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1490 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1492 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1494 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1496 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1498 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1500 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1502 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1504 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1509 dvp_d2d9_m1:dvp-d2d9-m1 {
1512 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1514 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1516 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1518 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1520 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1522 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1524 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1526 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1528 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1530 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1532 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1534 <3 2 RK_FUNC_2 &pcfg_pull_none>;