1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
13 compatible = "rockchip,rk3328";
15 interrupt-parent = <&gic>;
38 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
41 // clocks = <&cru ARMCLK>;
42 operating-points-v2 = <&cpu0_opp_table>;
46 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
52 compatible = "arm,cortex-a53", "arm,armv8";
54 enable-method = "psci";
58 compatible = "arm,cortex-a53", "arm,armv8";
60 enable-method = "psci";
64 cpu0_opp_table: opp_table0 {
65 compatible = "operating-points-v2";
69 opp-hz = /bits/ 64 <408000000>;
70 opp-microvolt = <950000>;
71 clock-latency-ns = <40000>;
75 opp-hz = /bits/ 64 <600000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
80 opp-hz = /bits/ 64 <816000000>;
81 opp-microvolt = <1000000>;
82 clock-latency-ns = <40000>;
85 opp-hz = /bits/ 64 <1008000000>;
86 opp-microvolt = <1100000>;
87 clock-latency-ns = <40000>;
90 opp-hz = /bits/ 64 <1200000000>;
91 opp-microvolt = <1225000>;
92 clock-latency-ns = <40000>;
95 opp-hz = /bits/ 64 <1296000000>;
96 opp-microvolt = <1300000>;
97 clock-latency-ns = <40000>;
102 compatible = "arm,cortex-a53-pmu";
103 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
111 compatible = "arm,psci-1.0";
116 compatible = "arm,armv8-timer";
117 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
120 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
124 compatible = "fixed-clock";
126 clock-frequency = <24000000>;
127 clock-output-names = "xin24m";
131 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
132 reg = <0x0 0xff000000 0x0 0x1000>;
133 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
135 clock-names = "i2s_clk", "i2s_hclk";
136 dmas = <&dmac 11>, <&dmac 12>;
138 dma-names = "tx", "rx";
143 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
144 reg = <0x0 0xff010000 0x0 0x1000>;
145 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
147 clock-names = "i2s_clk", "i2s_hclk";
148 dmas = <&dmac 14>, <&dmac 15>;
150 dma-names = "tx", "rx";
155 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
156 reg = <0x0 0xff020000 0x0 0x1000>;
157 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
159 clock-names = "i2s_clk", "i2s_hclk";
160 dmas = <&dmac 0>, <&dmac 1>;
162 dma-names = "tx", "rx";
163 pinctrl-names = "default", "sleep";
164 pinctrl-0 = <&i2s2m0_mclk
170 pinctrl-1 = <&i2s2m0_sleep>;
174 spdif: spdif@ff030000 {
175 compatible = "rockchip,rk3328-spdif";
176 reg = <0x0 0xff030000 0x0 0x1000>;
177 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
179 clock-names = "mclk", "hclk";
183 pinctrl-names = "default";
184 pinctrl-0 = <&spdifm2_tx>;
188 grf: syscon@ff100000 {
189 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
190 reg = <0x0 0xff100000 0x0 0x1000>;
192 io_domains: io-domains {
193 compatible = "rockchip,rk3328-io-voltage-domain";
198 uart0: serial@ff110000 {
199 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
200 reg = <0x0 0xff110000 0x0 0x100>;
201 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
203 clock-names = "baudclk", "apb_pclk";
206 dmas = <&dmac 2>, <&dmac 3>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
213 uart1: serial@ff120000 {
214 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
215 reg = <0x0 0xff120000 0x0 0x100>;
216 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
218 clock-names = "sclk_uart", "pclk_uart";
221 dmas = <&dmac 4>, <&dmac 5>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
228 uart2: serial@ff130000 {
229 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
230 reg = <0x0 0xff130000 0x0 0x100>;
231 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
233 clock-names = "baudclk", "apb_pclk";
236 dmas = <&dmac 6>, <&dmac 7>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&uart2m1_xfer>;
243 pmu: power-management@ff140000 {
244 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
245 reg = <0x0 0xff140000 0x0 0x1000>;
249 compatible = "rockchip,rk3328-i2c";
250 reg = <0x0 0xff150000 0x0 0x1000>;
251 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
252 #address-cells = <1>;
254 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
255 clock-names = "i2c", "pclk";
256 pinctrl-names = "default";
257 pinctrl-0 = <&i2c0_xfer>;
262 compatible = "rockchip,rk3328-i2c";
263 reg = <0x0 0xff160000 0x0 0x1000>;
264 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
265 #address-cells = <1>;
267 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
268 clock-names = "i2c", "pclk";
269 pinctrl-names = "default";
270 pinctrl-0 = <&i2c1_xfer>;
275 compatible = "rockchip,rk3328-i2c";
276 reg = <0x0 0xff170000 0x0 0x1000>;
277 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
278 #address-cells = <1>;
280 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
281 clock-names = "i2c", "pclk";
282 pinctrl-names = "default";
283 pinctrl-0 = <&i2c2_xfer>;
288 compatible = "rockchip,rk3328-i2c";
289 reg = <0x0 0xff180000 0x0 0x1000>;
290 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
291 #address-cells = <1>;
293 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
294 clock-names = "i2c", "pclk";
295 pinctrl-names = "default";
296 pinctrl-0 = <&i2c3_xfer>;
301 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
302 reg = <0x0 0xff190000 0x0 0x1000>;
303 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
304 #address-cells = <1>;
306 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
307 clock-names = "spiclk", "apb_pclk";
308 dmas = <&dmac 8>, <&dmac 9>;
310 dma-names = "tx", "rx";
311 pinctrl-names = "default";
312 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
316 wdt: watchdog@ff1a0000 {
317 compatible = "snps,dw-wdt";
318 reg = <0x0 0xff1a0000 0x0 0x100>;
319 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
324 compatible = "simple-bus";
325 #address-cells = <2>;
329 dmac: dmac@ff1f0000 {
330 compatible = "arm,pl330", "arm,primecell";
331 reg = <0x0 0xff1f0000 0x0 0x4000>;
332 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&cru ACLK_DMAC>;
335 clock-names = "apb_pclk";
340 saradc: saradc@ff280000 {
341 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
342 reg = <0x0 0xff280000 0x0 0x100>;
343 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
344 #io-channel-cells = <1>;
345 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
346 clock-names = "saradc", "apb_pclk";
347 resets = <&cru SRST_SARADC_P>;
348 reset-names = "saradc-apb";
352 cru: clock-controller@ff440000 {
353 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
354 reg = <0x0 0xff440000 0x0 0x1000>;
355 rockchip,grf = <&grf>;
359 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
360 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
361 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
362 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
363 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
364 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
365 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
366 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
367 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
368 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
369 <&cru SCLK_WIFI>, <&cru ARMCLK>,
370 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
371 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
372 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
373 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
374 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
375 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
376 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
377 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
378 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
379 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
380 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
381 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
382 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
383 assigned-clock-parents =
384 <&cru HDMIPHY>, <&cru PLL_APLL>,
385 <&cru PLL_GPLL>, <&xin24m>,
386 <&xin24m>, <&xin24m>;
387 assigned-clock-rates =
390 <24000000>, <24000000>,
391 <15000000>, <15000000>,
392 <100000000>, <100000000>,
393 <100000000>, <100000000>,
394 <50000000>, <100000000>,
395 <100000000>, <100000000>,
396 <50000000>, <50000000>,
397 <50000000>, <50000000>,
398 <24000000>, <600000000>,
399 <491520000>, <1200000000>,
400 <150000000>, <75000000>,
401 <75000000>, <150000000>,
402 <75000000>, <75000000>,
403 <300000000>, <100000000>,
404 <300000000>, <200000000>,
405 <400000000>, <500000000>,
406 <200000000>, <300000000>,
407 <300000000>, <250000000>,
408 <200000000>, <100000000>,
409 <24000000>, <100000000>,
410 <150000000>, <50000000>,
414 sdmmc: rksdmmc@ff500000 {
415 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
416 reg = <0x0 0xff500000 0x0 0x4000>;
417 max-frequency = <150000000>;
418 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
419 clock-names = "biu", "ciu";
420 fifo-depth = <0x100>;
421 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
425 sdio: dwmmc@ff510000 {
426 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
427 reg = <0x0 0xff510000 0x0 0x4000>;
428 max-frequency = <150000000>;
429 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
430 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
431 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
432 fifo-depth = <0x100>;
433 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
437 emmc: rksdmmc@ff520000 {
438 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
439 reg = <0x0 0xff520000 0x0 0x4000>;
440 max-frequency = <150000000>;
441 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
442 clock-names = "biu", "ciu";
443 fifo-depth = <0x100>;
444 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
448 gmac2io: ethernet@ff540000 {
449 compatible = "rockchip,rk3328-gmac";
450 reg = <0x0 0xff540000 0x0 0x10000>;
451 rockchip,grf = <&grf>;
452 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
453 interrupt-names = "macirq";
454 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
455 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
456 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
458 clock-names = "stmmaceth", "mac_clk_rx",
459 "mac_clk_tx", "clk_mac_ref",
460 "clk_mac_refout", "aclk_mac",
462 resets = <&cru SRST_GMAC2IO_A>;
463 reset-names = "stmmaceth";
467 usb_host0_ehci: usb@ff5c0000 {
468 compatible = "generic-ehci";
469 reg = <0x0 0xff5c0000 0x0 0x10000>;
470 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
474 usb_host0_ohci: usb@ff5d0000 {
475 compatible = "generic-ohci";
476 reg = <0x0 0xff5d0000 0x0 0x10000>;
477 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
481 usb20_otg: usb@ff580000 {
482 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
484 reg = <0x0 0xff580000 0x0 0x40000>;
485 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
491 sdmmc_ext: rksdmmc@ff5f0000 {
492 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
493 reg = <0x0 0xff5f0000 0x0 0x4000>;
494 max-frequency = <150000000>;
495 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
496 clock-names = "biu", "ciu";
497 fifo-depth = <0x100>;
498 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
502 gic: interrupt-controller@ffb70000 {
503 compatible = "arm,gic-400";
504 #interrupt-cells = <3>;
505 #address-cells = <0>;
506 interrupt-controller;
507 reg = <0x0 0xff811000 0 0x1000>,
508 <0x0 0xff812000 0 0x2000>,
509 <0x0 0xff814000 0 0x2000>,
510 <0x0 0xff816000 0 0x2000>;
511 interrupts = <GIC_PPI 9
512 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
516 compatible = "rockchip,rk3328-pinctrl";
517 rockchip,grf = <&grf>;
518 #address-cells = <2>;
522 gpio0: gpio0@ff210000 {
523 compatible = "rockchip,gpio-bank";
524 reg = <0x0 0xff210000 0x0 0x100>;
525 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&cru PCLK_GPIO0>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
535 gpio1: gpio1@ff220000 {
536 compatible = "rockchip,gpio-bank";
537 reg = <0x0 0xff220000 0x0 0x100>;
538 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&cru PCLK_GPIO1>;
544 interrupt-controller;
545 #interrupt-cells = <2>;
548 gpio2: gpio2@ff230000 {
549 compatible = "rockchip,gpio-bank";
550 reg = <0x0 0xff230000 0x0 0x100>;
551 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&cru PCLK_GPIO2>;
557 interrupt-controller;
558 #interrupt-cells = <2>;
561 gpio3: gpio3@ff240000 {
562 compatible = "rockchip,gpio-bank";
563 reg = <0x0 0xff240000 0x0 0x100>;
564 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cru PCLK_GPIO3>;
570 interrupt-controller;
571 #interrupt-cells = <2>;
574 pcfg_pull_up: pcfg-pull-up {
578 pcfg_pull_down: pcfg-pull-down {
582 pcfg_pull_none: pcfg-pull-none {
586 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
588 drive-strength = <2>;
591 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
593 drive-strength = <2>;
596 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
598 drive-strength = <4>;
601 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
603 drive-strength = <4>;
606 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
608 drive-strength = <4>;
611 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
613 drive-strength = <8>;
616 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
618 drive-strength = <8>;
621 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
623 drive-strength = <12>;
626 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
628 drive-strength = <12>;
631 pcfg_output_high: pcfg-output-high {
635 pcfg_output_low: pcfg-output-low {
639 pcfg_input_high: pcfg-input-high {
644 pcfg_input: pcfg-input {
649 i2c0_xfer: i2c0-xfer {
651 <2 24 RK_FUNC_1 &pcfg_pull_none>,
652 <2 25 RK_FUNC_1 &pcfg_pull_none>;
657 i2c1_xfer: i2c1-xfer {
659 <2 4 RK_FUNC_2 &pcfg_pull_none>,
660 <2 5 RK_FUNC_2 &pcfg_pull_none>;
665 i2c2_xfer: i2c2-xfer {
667 <2 13 RK_FUNC_1 &pcfg_pull_none>,
668 <2 14 RK_FUNC_1 &pcfg_pull_none>;
673 i2c3_xfer: i2c3-xfer {
675 <0 5 RK_FUNC_2 &pcfg_pull_none>,
676 <0 6 RK_FUNC_2 &pcfg_pull_none>;
678 i2c3_gpio: i2c3-gpio {
680 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
681 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
686 hdmii2c_xfer: hdmii2c-xfer {
688 <0 5 RK_FUNC_1 &pcfg_pull_none>,
689 <0 6 RK_FUNC_1 &pcfg_pull_none>;
694 uart0_xfer: uart0-xfer {
696 <1 9 RK_FUNC_1 &pcfg_pull_up>,
697 <1 8 RK_FUNC_1 &pcfg_pull_none>;
700 uart0_cts: uart0-cts {
702 <1 11 RK_FUNC_1 &pcfg_pull_none>;
705 uart0_rts: uart0-rts {
707 <1 10 RK_FUNC_1 &pcfg_pull_none>;
710 uart0_rts_gpio: uart0-rts-gpio {
712 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
717 uart1_xfer: uart1-xfer {
719 <3 4 RK_FUNC_4 &pcfg_pull_up>,
720 <3 6 RK_FUNC_4 &pcfg_pull_none>;
723 uart1_cts: uart1-cts {
725 <3 7 RK_FUNC_4 &pcfg_pull_none>;
728 uart1_rts: uart1-rts {
730 <3 5 RK_FUNC_4 &pcfg_pull_none>;
733 uart1_rts_gpio: uart1-rts-gpio {
735 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
740 uart2m0_xfer: uart2m0-xfer {
742 <1 0 RK_FUNC_2 &pcfg_pull_up>,
743 <1 1 RK_FUNC_2 &pcfg_pull_none>;
748 uart2m1_xfer: uart2m1-xfer {
750 <2 0 RK_FUNC_1 &pcfg_pull_up>,
751 <2 1 RK_FUNC_1 &pcfg_pull_none>;
756 spi0m0_clk: spi0m0-clk {
758 <2 8 RK_FUNC_1 &pcfg_pull_up>;
761 spi0m0_cs0: spi0m0-cs0 {
763 <2 11 RK_FUNC_1 &pcfg_pull_up>;
766 spi0m0_tx: spi0m0-tx {
768 <2 9 RK_FUNC_1 &pcfg_pull_up>;
771 spi0m0_rx: spi0m0-rx {
773 <2 10 RK_FUNC_1 &pcfg_pull_up>;
776 spi0m0_cs1: spi0m0-cs1 {
778 <2 12 RK_FUNC_1 &pcfg_pull_up>;
783 spi0m1_clk: spi0m1-clk {
785 <3 23 RK_FUNC_2 &pcfg_pull_up>;
788 spi0m1_cs0: spi0m1-cs0 {
790 <3 26 RK_FUNC_2 &pcfg_pull_up>;
793 spi0m1_tx: spi0m1-tx {
795 <3 25 RK_FUNC_2 &pcfg_pull_up>;
798 spi0m1_rx: spi0m1-rx {
800 <3 24 RK_FUNC_2 &pcfg_pull_up>;
803 spi0m1_cs1: spi0m1-cs1 {
805 <3 27 RK_FUNC_2 &pcfg_pull_up>;
810 spi0m2_clk: spi0m2-clk {
812 <3 0 RK_FUNC_4 &pcfg_pull_up>;
815 spi0m2_cs0: spi0m2-cs0 {
817 <3 8 RK_FUNC_3 &pcfg_pull_up>;
820 spi0m2_tx: spi0m2-tx {
822 <3 1 RK_FUNC_4 &pcfg_pull_up>;
825 spi0m2_rx: spi0m2-rx {
827 <3 2 RK_FUNC_4 &pcfg_pull_up>;
832 i2s1_mclk: i2s1-mclk {
834 <2 15 RK_FUNC_1 &pcfg_pull_none>;
837 i2s1_sclk: i2s1-sclk {
839 <2 18 RK_FUNC_1 &pcfg_pull_none>;
842 i2s1_lrckrx: i2s1-lrckrx {
844 <2 16 RK_FUNC_1 &pcfg_pull_none>;
847 i2s1_lrcktx: i2s1-lrcktx {
849 <2 17 RK_FUNC_1 &pcfg_pull_none>;
854 <2 19 RK_FUNC_1 &pcfg_pull_none>;
859 <2 23 RK_FUNC_1 &pcfg_pull_none>;
862 i2s1_sdio1: i2s1-sdio1 {
864 <2 20 RK_FUNC_1 &pcfg_pull_none>;
867 i2s1_sdio2: i2s1-sdio2 {
869 <2 21 RK_FUNC_1 &pcfg_pull_none>;
872 i2s1_sdio3: i2s1-sdio3 {
874 <2 22 RK_FUNC_1 &pcfg_pull_none>;
877 i2s1_sleep: i2s1-sleep {
879 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
880 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
881 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
882 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
883 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
884 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
885 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
886 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
887 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
892 i2s2m0_mclk: i2s2m0-mclk {
894 <1 21 RK_FUNC_1 &pcfg_pull_none>;
897 i2s2m0_sclk: i2s2m0-sclk {
899 <1 22 RK_FUNC_1 &pcfg_pull_none>;
902 i2s2m0_lrckrx: i2s2m0-lrckrx {
904 <1 26 RK_FUNC_1 &pcfg_pull_none>;
907 i2s2m0_lrcktx: i2s2m0-lrcktx {
909 <1 23 RK_FUNC_1 &pcfg_pull_none>;
912 i2s2m0_sdi: i2s2m0-sdi {
914 <1 24 RK_FUNC_1 &pcfg_pull_none>;
917 i2s2m0_sdo: i2s2m0-sdo {
919 <1 25 RK_FUNC_1 &pcfg_pull_none>;
922 i2s2m0_sleep: i2s2m0-sleep {
924 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
925 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
926 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
927 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
928 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
929 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
934 i2s2m1_mclk: i2s2m1-mclk {
936 <1 21 RK_FUNC_1 &pcfg_pull_none>;
939 i2s2m1_sclk: i2s2m1-sclk {
941 <3 0 RK_FUNC_6 &pcfg_pull_none>;
944 i2s2m1_lrckrx: i2sm1-lrckrx {
946 <3 8 RK_FUNC_6 &pcfg_pull_none>;
949 i2s2m1_lrcktx: i2s2m1-lrcktx {
951 <3 8 RK_FUNC_4 &pcfg_pull_none>;
954 i2s2m1_sdi: i2s2m1-sdi {
956 <3 2 RK_FUNC_6 &pcfg_pull_none>;
959 i2s2m1_sdo: i2s2m1-sdo {
961 <3 1 RK_FUNC_6 &pcfg_pull_none>;
964 i2s2m1_sleep: i2s2m1-sleep {
966 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
967 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
968 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
969 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
970 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
975 spdifm0_tx: spdifm0-tx {
977 <0 27 RK_FUNC_1 &pcfg_pull_none>;
982 spdifm1_tx: spdifm1-tx {
984 <2 17 RK_FUNC_2 &pcfg_pull_none>;
989 spdifm2_tx: spdifm2-tx {
991 <0 2 RK_FUNC_2 &pcfg_pull_none>;
996 sdmmc0m0_pwren: sdmmc0m0-pwren {
998 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1001 sdmmc0m0_gpio: sdmmc0m0-gpio {
1003 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1008 sdmmc0m1_pwren: sdmmc0m1-pwren {
1010 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1013 sdmmc0m1_gpio: sdmmc0m1-gpio {
1015 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1020 sdmmc0_clk: sdmmc0-clk {
1022 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1025 sdmmc0_cmd: sdmmc0-cmd {
1027 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1030 sdmmc0_dectn: sdmmc0-dectn {
1032 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1035 sdmmc0_wrprt: sdmmc0-wrprt {
1037 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1040 sdmmc0_bus1: sdmmc0-bus1 {
1042 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1045 sdmmc0_bus4: sdmmc0-bus4 {
1047 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1048 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1049 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1050 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1053 sdmmc0_gpio: sdmmc0-gpio {
1055 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1056 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1057 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1058 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1059 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1060 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1061 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1062 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1067 sdmmc0ext_clk: sdmmc0ext-clk {
1069 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1072 sdmmc0ext_cmd: sdmmc0ext-cmd {
1074 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1077 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1079 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1082 sdmmc0ext_dectn: sdmmc0ext-dectn {
1084 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1087 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1089 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1092 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1094 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1095 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1096 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1097 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1100 sdmmc0ext_gpio: sdmmc0ext-gpio {
1102 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1103 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1104 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1105 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1106 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1107 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1108 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1109 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1114 sdmmc1_clk: sdmmc1-clk {
1116 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1119 sdmmc1_cmd: sdmmc1-cmd {
1121 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1124 sdmmc1_pwren: sdmmc1-pwren {
1126 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1129 sdmmc1_wrprt: sdmmc1-wrprt {
1131 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1134 sdmmc1_dectn: sdmmc1-dectn {
1136 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1139 sdmmc1_bus1: sdmmc1-bus1 {
1141 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1144 sdmmc1_bus4: sdmmc1-bus4 {
1146 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1147 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1148 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1149 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1152 sdmmc1_gpio: sdmmc1-gpio {
1154 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1155 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1156 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1157 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1158 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1159 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1160 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1161 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1162 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1167 emmc_clk: emmc-clk {
1169 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1172 emmc_cmd: emmc-cmd {
1174 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1177 emmc_pwren: emmc-pwren {
1179 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1182 emmc_rstnout: emmc-rstnout {
1184 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1187 emmc_bus1: emmc-bus1 {
1189 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1192 emmc_bus4: emmc-bus4 {
1194 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1195 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1196 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1197 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1200 emmc_bus8: emmc-bus8 {
1202 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1203 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1204 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1205 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1206 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1207 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1208 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1209 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1214 pwm0_pin: pwm0-pin {
1216 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1221 pwm1_pin: pwm1-pin {
1223 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1228 pwm2_pin: pwm2-pin {
1230 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1235 pwmir_pin: pwmir-pin {
1237 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1242 rgmiim0_pins: rgmiim0-pins {
1245 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1247 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1249 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1251 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1253 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1255 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1257 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1259 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1261 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1263 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1265 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1267 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1269 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1271 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1273 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1276 rmiim0_pins: rmiim0-pins {
1279 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1281 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1283 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1285 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1287 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1289 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1291 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1293 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1295 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1297 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1302 rgmiim1_pins: rgmiim1-pins {
1305 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1307 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1309 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1311 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1313 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1315 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1317 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1319 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1321 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1323 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1325 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1327 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1329 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1331 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1333 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1336 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1338 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1340 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1342 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1344 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1346 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1348 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1351 rmiim1_pins: rmiim1-pins {
1354 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1356 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1358 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1360 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1362 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1364 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1366 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1368 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1370 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1372 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1375 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1377 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1379 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1381 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1383 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1385 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1390 fephyled_speed100: fephyled-speed100 {
1392 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1395 fephyled_speed10: fephyled-speed10 {
1397 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1400 fephyled_duplex: fephyled-duplex {
1402 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1405 fephyled_rxm0: fephyled-rxm0 {
1407 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1410 fephyled_txm0: fephyled-txm0 {
1412 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1415 fephyled_linkm0: fephyled-linkm0 {
1417 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1420 fephyled_rxm1: fephyled-rxm1 {
1422 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1425 fephyled_txm1: fephyled-txm1 {
1427 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1430 fephyled_linkm1: fephyled-linkm1 {
1432 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1437 tsadc_int: tsadc-int {
1439 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1441 tsadc_gpio: tsadc-gpio {
1443 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1448 hdmi_cec: hdmi-cec {
1450 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1453 hdmi_hpd: hdmi-hpd {
1455 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1460 dvp_d2d9_m0:dvp-d2d9-m0 {
1463 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1465 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1467 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1469 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1471 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1473 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1475 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1477 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1479 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1481 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1483 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1485 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1490 dvp_d2d9_m1:dvp-d2d9-m1 {
1493 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1495 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1497 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1499 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1501 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1503 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1505 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1507 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1509 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1511 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1513 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1515 <3 2 RK_FUNC_2 &pcfg_pull_none>;