2 * SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3288-cru.h>
10 #include <dt-bindings/power-domain/rk3288.h>
11 #include <dt-bindings/thermal/thermal.h>
12 #include "skeleton.dtsi"
15 compatible = "rockchip,rk3288";
17 interrupt-parent = <&gic>;
46 enable-method = "rockchip,rk3066-smp";
47 rockchip,pmu = <&pmu>;
51 compatible = "arm,cortex-a12";
69 #cooling-cells = <2>; /* min followed by max */
70 clock-latency = <40000>;
71 clocks = <&cru ARMCLK>;
72 resets = <&cru SRST_CORE0>;
76 compatible = "arm,cortex-a12";
78 resets = <&cru SRST_CORE1>;
82 compatible = "arm,cortex-a12";
84 resets = <&cru SRST_CORE2>;
88 compatible = "arm,cortex-a12";
90 resets = <&cru SRST_CORE3>;
95 compatible = "arm,amba-bus";
100 dmac_peri: dma-controller@ff250000 {
101 compatible = "arm,pl330", "arm,primecell";
103 reg = <0xff250000 0x4000>;
104 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&cru ACLK_DMAC2>;
108 clock-names = "apb_pclk";
111 dmac_bus_ns: dma-controller@ff600000 {
112 compatible = "arm,pl330", "arm,primecell";
114 reg = <0xff600000 0x4000>;
115 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&cru ACLK_DMAC1>;
119 clock-names = "apb_pclk";
123 dmac_bus_s: dma-controller@ffb20000 {
124 compatible = "arm,pl330", "arm,primecell";
126 reg = <0xffb20000 0x4000>;
127 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&cru ACLK_DMAC1>;
131 clock-names = "apb_pclk";
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
143 arm,use-physical-timer;
144 compatible = "arm,armv7-timer";
145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 clock-frequency = <24000000>;
154 compatible = "rockchip,display-subsystem";
155 ports = <&vopl_out>, <&vopb_out>;
158 sdmmc: dwmmc@ff0c0000 {
159 compatible = "rockchip,rk3288-dw-mshc";
160 clock-freq-min-max = <400000 150000000>;
161 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
162 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
163 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
164 fifo-depth = <0x100>;
165 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
166 reg = <0xff0c0000 0x4000>;
170 sdio0: dwmmc@ff0d0000 {
171 compatible = "rockchip,rk3288-dw-mshc";
172 clock-freq-min-max = <400000 150000000>;
173 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
174 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
175 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
176 fifo-depth = <0x100>;
177 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
178 reg = <0xff0d0000 0x4000>;
182 sdio1: dwmmc@ff0e0000 {
183 compatible = "rockchip,rk3288-dw-mshc";
184 clock-freq-min-max = <400000 150000000>;
185 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
186 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
187 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
188 fifo-depth = <0x100>;
189 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
190 reg = <0xff0e0000 0x4000>;
194 emmc: dwmmc@ff0f0000 {
195 compatible = "rockchip,rk3288-dw-mshc";
196 clock-freq-min-max = <400000 150000000>;
197 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
198 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
199 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
200 fifo-depth = <0x100>;
201 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
202 reg = <0xff0f0000 0x4000>;
206 saradc: saradc@ff100000 {
207 compatible = "rockchip,saradc";
208 reg = <0xff100000 0x100>;
209 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
210 #io-channel-cells = <1>;
211 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
212 clock-names = "saradc", "apb_pclk";
217 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
218 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
219 clock-names = "spiclk", "apb_pclk";
220 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
221 dma-names = "tx", "rx";
222 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
225 reg = <0xff110000 0x1000>;
226 #address-cells = <1>;
232 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
233 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
234 clock-names = "spiclk", "apb_pclk";
235 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
236 dma-names = "tx", "rx";
237 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
240 reg = <0xff120000 0x1000>;
241 #address-cells = <1>;
247 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
248 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
249 clock-names = "spiclk", "apb_pclk";
250 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
251 dma-names = "tx", "rx";
252 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
255 reg = <0xff130000 0x1000>;
256 #address-cells = <1>;
262 compatible = "rockchip,rk3288-i2c";
263 reg = <0xff140000 0x1000>;
264 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
265 #address-cells = <1>;
268 clocks = <&cru PCLK_I2C1>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&i2c1_xfer>;
275 compatible = "rockchip,rk3288-i2c";
276 reg = <0xff150000 0x1000>;
277 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
278 #address-cells = <1>;
281 clocks = <&cru PCLK_I2C3>;
282 pinctrl-names = "default";
283 pinctrl-0 = <&i2c3_xfer>;
288 compatible = "rockchip,rk3288-i2c";
289 reg = <0xff160000 0x1000>;
290 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
291 #address-cells = <1>;
294 clocks = <&cru PCLK_I2C4>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&i2c4_xfer>;
301 compatible = "rockchip,rk3288-i2c";
302 reg = <0xff170000 0x1000>;
303 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
304 #address-cells = <1>;
307 clocks = <&cru PCLK_I2C5>;
308 pinctrl-names = "default";
309 pinctrl-0 = <&i2c5_xfer>;
312 uart0: serial@ff180000 {
313 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
314 reg = <0xff180000 0x100>;
315 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
319 clock-names = "baudclk", "apb_pclk";
320 pinctrl-names = "default";
321 pinctrl-0 = <&uart0_xfer>;
325 uart1: serial@ff190000 {
326 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
327 reg = <0xff190000 0x100>;
328 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
332 clock-names = "baudclk", "apb_pclk";
333 pinctrl-names = "default";
334 pinctrl-0 = <&uart1_xfer>;
338 uart2: serial@ff690000 {
339 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
340 reg = <0xff690000 0x100>;
341 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
345 clock-names = "baudclk", "apb_pclk";
346 pinctrl-names = "default";
347 pinctrl-0 = <&uart2_xfer>;
350 uart3: serial@ff1b0000 {
351 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
352 reg = <0xff1b0000 0x100>;
353 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
357 clock-names = "baudclk", "apb_pclk";
358 pinctrl-names = "default";
359 pinctrl-0 = <&uart3_xfer>;
363 uart4: serial@ff1c0000 {
364 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
365 reg = <0xff1c0000 0x100>;
366 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
370 clock-names = "baudclk", "apb_pclk";
371 pinctrl-names = "default";
372 pinctrl-0 = <&uart4_xfer>;
375 thermal: thermal-zones {
376 #include "rk3288-thermal.dtsi"
379 tsadc: tsadc@ff280000 {
380 compatible = "rockchip,rk3288-tsadc";
381 reg = <0xff280000 0x100>;
382 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
384 clock-names = "tsadc", "apb_pclk";
385 resets = <&cru SRST_TSADC>;
386 reset-names = "tsadc-apb";
387 pinctrl-names = "otp_out";
388 pinctrl-0 = <&otp_out>;
389 #thermal-sensor-cells = <1>;
390 hw-shut-temp = <125000>;
394 gmac: ethernet@ff290000 {
395 compatible = "rockchip,rk3288-gmac";
396 reg = <0xff290000 0x10000>;
397 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
398 interrupt-names = "macirq";
399 rockchip,grf = <&grf>;
400 clocks = <&cru SCLK_MAC>,
401 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
402 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
403 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
404 clock-names = "stmmaceth",
405 "mac_clk_rx", "mac_clk_tx",
406 "clk_mac_ref", "clk_mac_refout",
407 "aclk_mac", "pclk_mac";
410 usb_host0_ehci: usb@ff500000 {
411 compatible = "generic-ehci";
412 reg = <0xff500000 0x100>;
413 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru HCLK_USBHOST0>;
415 clock-names = "usbhost";
421 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
423 usb_host1: usb@ff540000 {
424 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
426 reg = <0xff540000 0x40000>;
427 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&cru HCLK_USBHOST1>;
431 phy-names = "usb2-phy";
435 usb_otg: usb@ff580000 {
436 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
438 reg = <0xff580000 0x40000>;
439 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&cru HCLK_OTG0>;
443 phy-names = "usb2-phy";
447 usb_hsic: usb@ff5c0000 {
448 compatible = "generic-ehci";
449 reg = <0xff5c0000 0x100>;
450 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&cru HCLK_HSIC>;
452 clock-names = "usbhost";
457 compatible = "rockchip,rk3288-dmc", "syscon";
458 rockchip,cru = <&cru>;
459 rockchip,grf = <&grf>;
460 rockchip,pmu = <&pmu>;
461 rockchip,sgrf = <&sgrf>;
462 rockchip,noc = <&noc>;
463 reg = <0xff610000 0x3fc
467 rockchip,sram = <&ddr_sram>;
468 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
469 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
471 clock-names = "pclk_ddrupctl0", "pclk_publ0",
472 "pclk_ddrupctl1", "pclk_publ1",
477 compatible = "rockchip,rk3288-i2c";
478 reg = <0xff650000 0x1000>;
479 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
480 #address-cells = <1>;
483 clocks = <&cru PCLK_I2C0>;
484 pinctrl-names = "default";
485 pinctrl-0 = <&i2c0_xfer>;
490 compatible = "rockchip,rk3288-i2c";
491 reg = <0xff660000 0x1000>;
492 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
493 #address-cells = <1>;
496 clocks = <&cru PCLK_I2C2>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&i2c2_xfer>;
503 compatible = "rockchip,rk3288-pwm";
504 reg = <0xff680000 0x10>;
506 pinctrl-names = "default";
507 pinctrl-0 = <&pwm0_pin>;
508 clocks = <&cru PCLK_PWM>;
510 rockchip,grf = <&grf>;
515 compatible = "rockchip,rk3288-pwm";
516 reg = <0xff680010 0x10>;
518 pinctrl-names = "default";
519 pinctrl-0 = <&pwm1_pin>;
520 clocks = <&cru PCLK_PWM>;
522 rockchip,grf = <&grf>;
527 compatible = "rockchip,rk3288-pwm";
528 reg = <0xff680020 0x10>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&pwm2_pin>;
532 clocks = <&cru PCLK_PWM>;
534 rockchip,grf = <&grf>;
539 compatible = "rockchip,rk3288-pwm";
540 reg = <0xff680030 0x10>;
542 pinctrl-names = "default";
543 pinctrl-0 = <&pwm3_pin>;
544 clocks = <&cru PCLK_PWM>;
546 rockchip,grf = <&grf>;
550 bus_intmem@ff700000 {
551 compatible = "mmio-sram";
552 reg = <0xff700000 0x18000>;
553 #address-cells = <1>;
555 ranges = <0 0xff700000 0x18000>;
557 compatible = "rockchip,rk3066-smp-sram";
560 ddr_sram: ddr-sram@1000 {
561 compatible = "rockchip,rk3288-ddr-sram";
562 reg = <0x1000 0x4000>;
567 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
568 reg = <0xff720000 0x1000>;
571 pmu: power-management@ff730000 {
572 compatible = "rockchip,rk3288-pmu", "syscon";
573 reg = <0xff730000 0x100>;
576 sgrf: syscon@ff740000 {
577 compatible = "rockchip,rk3288-sgrf", "syscon";
578 reg = <0xff740000 0x1000>;
581 cru: clock-controller@ff760000 {
582 compatible = "rockchip,rk3288-cru";
583 reg = <0xff760000 0x1000>;
584 rockchip,grf = <&grf>;
587 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
588 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
589 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
590 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
591 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
593 assigned-clock-rates = <0>, <0>,
594 <594000000>, <400000000>,
595 <500000000>, <300000000>,
596 <150000000>, <75000000>,
597 <300000000>, <150000000>,
599 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
602 grf: syscon@ff770000 {
603 compatible = "rockchip,rk3288-grf", "syscon";
604 reg = <0xff770000 0x1000>;
607 wdt: watchdog@ff800000 {
608 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
609 reg = <0xff800000 0x100>;
610 clocks = <&cru PCLK_WDT>;
611 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
616 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
617 reg = <0xff890000 0x10000>;
618 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
619 #address-cells = <1>;
621 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
622 dma-names = "tx", "rx";
623 clock-names = "i2s_hclk", "i2s_clk";
624 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&i2s0_bus>;
631 compatible = "rockchip,rk3288-vop";
632 reg = <0xff930000 0x19c>;
633 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
635 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
636 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
637 reset-names = "axi", "ahb", "dclk";
638 iommus = <&vopb_mmu>;
639 power-domains = <&power RK3288_PD_VIO>;
642 #address-cells = <1>;
644 vopb_out_edp: endpoint@0 {
646 remote-endpoint = <&edp_in_vopb>;
648 vopb_out_hdmi: endpoint@1 {
650 remote-endpoint = <&hdmi_in_vopb>;
655 vopb_mmu: iommu@ff930300 {
656 compatible = "rockchip,iommu";
657 reg = <0xff930300 0x100>;
658 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
659 interrupt-names = "vopb_mmu";
660 power-domains = <&power RK3288_PD_VIO>;
666 compatible = "rockchip,rk3288-vop";
667 reg = <0xff940000 0x19c>;
668 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
670 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
671 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
672 reset-names = "axi", "ahb", "dclk";
673 iommus = <&vopl_mmu>;
674 power-domains = <&power RK3288_PD_VIO>;
677 #address-cells = <1>;
679 vopl_out_edp: endpoint@0 {
681 remote-endpoint = <&edp_in_vopl>;
683 vopl_out_hdmi: endpoint@1 {
685 remote-endpoint = <&hdmi_in_vopl>;
691 vopl_mmu: iommu@ff940300 {
692 compatible = "rockchip,iommu";
693 reg = <0xff940300 0x100>;
694 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
695 interrupt-names = "vopl_mmu";
696 power-domains = <&power RK3288_PD_VIO>;
702 compatible = "rockchip,rk3288-edp";
703 reg = <0xff970000 0x4000>;
704 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
706 rockchip,grf = <&grf>;
707 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
710 power-domains = <&power RK3288_PD_VIO>;
714 #address-cells = <1>;
716 edp_in_vopb: endpoint@0 {
718 remote-endpoint = <&vopb_out_edp>;
720 edp_in_vopl: endpoint@1 {
722 remote-endpoint = <&vopl_out_edp>;
728 hdmi: hdmi@ff980000 {
729 compatible = "rockchip,rk3288-dw-hdmi";
730 reg = <0xff980000 0x20000>;
732 ddc-i2c-bus = <&i2c5>;
733 rockchip,grf = <&grf>;
734 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
736 clock-names = "iahb", "isfr";
740 #address-cells = <1>;
742 hdmi_in_vopb: endpoint@0 {
744 remote-endpoint = <&vopb_out_hdmi>;
746 hdmi_in_vopl: endpoint@1 {
748 remote-endpoint = <&vopl_out_hdmi>;
754 hdmi_audio: hdmi_audio {
755 compatible = "rockchip,rk3288-hdmi-audio";
756 i2s-controller = <&i2s>;
760 vpu: video-codec@ff9a0000 {
761 compatible = "rockchip,rk3288-vpu";
762 reg = <0xff9a0000 0x800>;
763 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
765 interrupt-names = "vepu", "vdpu";
766 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
767 clock-names = "aclk_vcodec", "hclk_vcodec";
768 power-domains = <&power RK3288_PD_VIDEO>;
772 vpu_mmu: iommu@ff9a0800 {
773 compatible = "rockchip,iommu";
774 reg = <0xff9a0800 0x100>;
775 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
776 interrupt-names = "vpu_mmu";
777 power-domains = <&power RK3288_PD_VIDEO>;
782 compatible = "arm,malit764",
786 reg = <0xffa30000 0x10000>;
787 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
790 interrupt-names = "JOB", "MMU", "GPU";
791 clocks = <&cru ACLK_GPU>;
792 clock-names = "aclk_gpu";
799 /* 500000 1200000 - See crosbug.com/p/33857 */
802 power-domains = <&power RK3288_PD_GPU>;
806 noc: syscon@ffac0000 {
807 compatible = "rockchip,rk3288-noc", "syscon";
808 reg = <0xffac0000 0x2000>;
811 efuse: efuse@ffb40000 {
812 compatible = "rockchip,rk3288-efuse";
813 reg = <0xffb40000 0x10000>;
817 gic: interrupt-controller@ffc01000 {
818 compatible = "arm,gic-400";
819 interrupt-controller;
820 #interrupt-cells = <3>;
821 #address-cells = <0>;
823 reg = <0xffc01000 0x1000>,
827 interrupts = <GIC_PPI 9 0xf04>;
831 compatible = "rockchip,rk3288-cpuidle";
835 compatible = "rockchip,rk3288-usb-phy";
836 rockchip,grf = <&grf>;
837 #address-cells = <1>;
844 clocks = <&cru SCLK_OTGPHY0>;
845 clock-names = "phyclk";
851 clocks = <&cru SCLK_OTGPHY1>;
852 clock-names = "phyclk";
858 clocks = <&cru SCLK_OTGPHY2>;
859 clock-names = "phyclk";
864 compatible = "rockchip,rk3288-pinctrl";
865 rockchip,grf = <&grf>;
866 rockchip,pmu = <&pmu>;
867 #address-cells = <1>;
871 gpio0: gpio0@ff750000 {
872 compatible = "rockchip,gpio-bank";
873 reg = <0xff750000 0x100>;
874 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&cru PCLK_GPIO0>;
880 interrupt-controller;
881 #interrupt-cells = <2>;
884 gpio1: gpio1@ff780000 {
885 compatible = "rockchip,gpio-bank";
886 reg = <0xff780000 0x100>;
887 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&cru PCLK_GPIO1>;
893 interrupt-controller;
894 #interrupt-cells = <2>;
897 gpio2: gpio2@ff790000 {
898 compatible = "rockchip,gpio-bank";
899 reg = <0xff790000 0x100>;
900 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
901 clocks = <&cru PCLK_GPIO2>;
906 interrupt-controller;
907 #interrupt-cells = <2>;
910 gpio3: gpio3@ff7a0000 {
911 compatible = "rockchip,gpio-bank";
912 reg = <0xff7a0000 0x100>;
913 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&cru PCLK_GPIO3>;
919 interrupt-controller;
920 #interrupt-cells = <2>;
923 gpio4: gpio4@ff7b0000 {
924 compatible = "rockchip,gpio-bank";
925 reg = <0xff7b0000 0x100>;
926 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&cru PCLK_GPIO4>;
932 interrupt-controller;
933 #interrupt-cells = <2>;
936 gpio5: gpio5@ff7c0000 {
937 compatible = "rockchip,gpio-bank";
938 reg = <0xff7c0000 0x100>;
939 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&cru PCLK_GPIO5>;
945 interrupt-controller;
946 #interrupt-cells = <2>;
949 gpio6: gpio6@ff7d0000 {
950 compatible = "rockchip,gpio-bank";
951 reg = <0xff7d0000 0x100>;
952 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
953 clocks = <&cru PCLK_GPIO6>;
958 interrupt-controller;
959 #interrupt-cells = <2>;
962 gpio7: gpio7@ff7e0000 {
963 compatible = "rockchip,gpio-bank";
964 reg = <0xff7e0000 0x100>;
965 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&cru PCLK_GPIO7>;
971 interrupt-controller;
972 #interrupt-cells = <2>;
975 gpio8: gpio8@ff7f0000 {
976 compatible = "rockchip,gpio-bank";
977 reg = <0xff7f0000 0x100>;
978 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&cru PCLK_GPIO8>;
984 interrupt-controller;
985 #interrupt-cells = <2>;
988 pcfg_pull_up: pcfg-pull-up {
992 pcfg_pull_down: pcfg-pull-down {
996 pcfg_pull_none: pcfg-pull-none {
1000 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1002 drive-strength = <12>;
1006 global_pwroff: global-pwroff {
1007 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1010 ddrio_pwroff: ddrio-pwroff {
1011 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1014 ddr0_retention: ddr0-retention {
1015 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1018 ddr1_retention: ddr1-retention {
1019 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1024 i2c0_xfer: i2c0-xfer {
1025 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1026 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1031 i2c1_xfer: i2c1-xfer {
1032 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1033 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1038 i2c2_xfer: i2c2-xfer {
1039 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1040 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1045 i2c3_xfer: i2c3-xfer {
1046 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1047 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1052 i2c4_xfer: i2c4-xfer {
1053 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1054 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1059 i2c5_xfer: i2c5-xfer {
1060 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1061 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1066 i2s0_bus: i2s0-bus {
1067 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1068 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1069 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1070 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1071 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1072 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1077 sdmmc_clk: sdmmc-clk {
1078 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1081 sdmmc_cmd: sdmmc-cmd {
1082 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1085 sdmmc_cd: sdmcc-cd {
1086 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1089 sdmmc_bus1: sdmmc-bus1 {
1090 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1093 sdmmc_bus4: sdmmc-bus4 {
1094 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1095 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1096 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1097 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1102 sdio0_bus1: sdio0-bus1 {
1103 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1106 sdio0_bus4: sdio0-bus4 {
1107 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1108 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1109 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1110 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1113 sdio0_cmd: sdio0-cmd {
1114 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1117 sdio0_clk: sdio0-clk {
1118 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1121 sdio0_cd: sdio0-cd {
1122 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1125 sdio0_wp: sdio0-wp {
1126 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1129 sdio0_pwr: sdio0-pwr {
1130 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1133 sdio0_bkpwr: sdio0-bkpwr {
1134 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1137 sdio0_int: sdio0-int {
1138 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1143 sdio1_bus1: sdio1-bus1 {
1144 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1147 sdio1_bus4: sdio1-bus4 {
1148 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1149 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1150 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1151 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1154 sdio1_cd: sdio1-cd {
1155 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1158 sdio1_wp: sdio1-wp {
1159 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1162 sdio1_bkpwr: sdio1-bkpwr {
1163 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1166 sdio1_int: sdio1-int {
1167 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1170 sdio1_cmd: sdio1-cmd {
1171 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1174 sdio1_clk: sdio1-clk {
1175 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1178 sdio1_pwr: sdio1-pwr {
1179 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1184 emmc_clk: emmc-clk {
1185 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1188 emmc_cmd: emmc-cmd {
1189 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1192 emmc_pwr: emmc-pwr {
1193 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1196 emmc_bus1: emmc-bus1 {
1197 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1200 emmc_bus4: emmc-bus4 {
1201 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1202 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1203 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1204 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1207 emmc_bus8: emmc-bus8 {
1208 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1209 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1210 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1211 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1212 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1213 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1214 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1215 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1220 spi0_clk: spi0-clk {
1221 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1223 spi0_cs0: spi0-cs0 {
1224 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1227 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1230 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1232 spi0_cs1: spi0-cs1 {
1233 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1237 spi1_clk: spi1-clk {
1238 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1240 spi1_cs0: spi1-cs0 {
1241 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1244 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1247 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1252 spi2_cs1: spi2-cs1 {
1253 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1255 spi2_clk: spi2-clk {
1256 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1258 spi2_cs0: spi2-cs0 {
1259 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1262 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1265 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1270 uart0_xfer: uart0-xfer {
1271 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1272 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1275 uart0_cts: uart0-cts {
1276 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1279 uart0_rts: uart0-rts {
1280 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1285 uart1_xfer: uart1-xfer {
1286 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1287 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1290 uart1_cts: uart1-cts {
1291 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1294 uart1_rts: uart1-rts {
1295 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1300 uart2_xfer: uart2-xfer {
1301 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1302 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1304 /* no rts / cts for uart2 */
1308 uart3_xfer: uart3-xfer {
1309 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1310 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1313 uart3_cts: uart3-cts {
1314 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1317 uart3_rts: uart3-rts {
1318 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1323 uart4_xfer: uart4-xfer {
1324 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1325 <5 13 3 &pcfg_pull_none>;
1328 uart4_cts: uart4-cts {
1329 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1332 uart4_rts: uart4-rts {
1333 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1339 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1344 pwm0_pin: pwm0-pin {
1345 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1350 pwm1_pin: pwm1-pin {
1351 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1356 pwm2_pin: pwm2-pin {
1357 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1362 pwm3_pin: pwm3-pin {
1363 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1368 rgmii_pins: rgmii-pins {
1369 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1370 <3 31 3 &pcfg_pull_none>,
1371 <3 26 3 &pcfg_pull_none>,
1372 <3 27 3 &pcfg_pull_none>,
1373 <3 28 3 &pcfg_pull_none_12ma>,
1374 <3 29 3 &pcfg_pull_none_12ma>,
1375 <3 24 3 &pcfg_pull_none_12ma>,
1376 <3 25 3 &pcfg_pull_none_12ma>,
1377 <4 0 3 &pcfg_pull_none>,
1378 <4 5 3 &pcfg_pull_none>,
1379 <4 6 3 &pcfg_pull_none>,
1380 <4 9 3 &pcfg_pull_none_12ma>,
1381 <4 4 3 &pcfg_pull_none_12ma>,
1382 <4 1 3 &pcfg_pull_none>,
1383 <4 3 3 &pcfg_pull_none>;
1386 rmii_pins: rmii-pins {
1387 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1388 <3 31 3 &pcfg_pull_none>,
1389 <3 28 3 &pcfg_pull_none>,
1390 <3 29 3 &pcfg_pull_none>,
1391 <4 0 3 &pcfg_pull_none>,
1392 <4 5 3 &pcfg_pull_none>,
1393 <4 4 3 &pcfg_pull_none>,
1394 <4 1 3 &pcfg_pull_none>,
1395 <4 2 3 &pcfg_pull_none>,
1396 <4 3 3 &pcfg_pull_none>;
1401 power: power-controller {
1402 compatible = "rockchip,rk3288-power-controller";
1403 #power-domain-cells = <1>;
1404 rockchip,pmu = <&pmu>;
1405 #address-cells = <1>;
1409 reg = <RK3288_PD_GPU>;
1410 clocks = <&cru ACLK_GPU>;
1414 reg = <RK3288_PD_HEVC>;
1415 clocks = <&cru ACLK_HEVC>,
1416 <&cru SCLK_HEVC_CABAC>,
1417 <&cru SCLK_HEVC_CORE>,
1422 reg = <RK3288_PD_VIO>;
1423 clocks = <&cru ACLK_IEP>,
1437 <&cru PCLK_EDP_CTRL>,
1438 <&cru PCLK_HDMI_CTRL>,
1439 <&cru PCLK_LVDS_PHY>,
1440 <&cru PCLK_MIPI_CSI>,
1441 <&cru PCLK_MIPI_DSI0>,
1442 <&cru PCLK_MIPI_DSI1>,
1443 <&cru SCLK_EDP_24M>,
1445 <&cru SCLK_HDMI_CEC>,
1446 <&cru SCLK_HDMI_HDCP>,
1447 <&cru SCLK_ISP_JPE>,
1453 reg = <RK3288_PD_VIDEO>;
1454 clocks = <&cru ACLK_VCODEC>,