arch/arm/dts/rk3288.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power-domain/rk3288.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/video/rk3288.h>
  11 #include "skeleton.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3288";
  15
  16         interrupt-parent = <&gic>;
  17         aliases {
  18                 gpio0 = &gpio0;
  19                 gpio1 = &gpio1;
  20                 gpio2 = &gpio2;
  21                 gpio3 = &gpio3;
  22                 gpio4 = &gpio4;
  23                 gpio5 = &gpio5;
  24                 gpio6 = &gpio6;
  25                 gpio7 = &gpio7;
  26                 gpio8 = &gpio8;
  27                 i2c0 = &i2c0;
  28                 i2c1 = &i2c1;
  29                 i2c2 = &i2c2;
  30                 i2c3 = &i2c3;
  31                 i2c4 = &i2c4;
  32                 i2c5 = &i2c5;
  33                 mmc0 = &emmc;
  34                 mmc1 = &sdmmc;
  35                 mmc2 = &sdio0;
  36                 mmc3 = &sdio1;
  37                 mshc0 = &emmc;
  38                 mshc1 = &sdmmc;
  39                 mshc2 = &sdio0;
  40                 mshc3 = &sdio1;
  41                 serial0 = &uart0;
  42                 serial1 = &uart1;
  43                 serial2 = &uart2;
  44                 serial3 = &uart3;
  45                 serial4 = &uart4;
  46                 spi0 = &spi0;
  47                 spi1 = &spi1;
  48                 spi2 = &spi2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 enable-method = "rockchip,rk3066-smp";
  55                 rockchip,pmu = <&pmu>;
  56
  57                 cpu0: cpu@500 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a12";
  60                         reg = <0x500>;
  61                         operating-points = <
  62                                 /* KHz    uV */
  63                                 1800000 1400000
  64                                 1704000 1350000
  65                                 1608000 1300000
  66                                 1512000 1250000
  67                                 1416000 1200000
  68                                 1200000 1100000
  69                                 1008000 1050000
  70                                  816000 1000000
  71                                  696000  950000
  72                                  600000  900000
  73                                  408000  900000
  74                                  216000  900000
  75                                  126000  900000
  76                         >;
  77                         #cooling-cells = <2>; /* min followed by max */
  78                         clock-latency = <40000>;
  79                         clocks = <&cru ARMCLK>;
  80                         resets = <&cru SRST_CORE0>;
  81                 };
  82                 cpu@501 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a12";
  85                         reg = <0x501>;
  86                         resets = <&cru SRST_CORE1>;
  87                 };
  88                 cpu@502 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a12";
  91                         reg = <0x502>;
  92                         resets = <&cru SRST_CORE2>;
  93                 };
  94                 cpu@503 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a12";
  97                         reg = <0x503>;
  98                         resets = <&cru SRST_CORE3>;
  99                 };
 100         };
 101
 102         amba {
 103                 compatible = "arm,amba-bus";
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 ranges;
 107
 108                 dmac_peri: dma-controller@ff250000 {
 109                         compatible = "arm,pl330", "arm,primecell";
 110                         broken-no-flushp;
 111                         reg = <0xff250000 0x4000>;
 112                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 113                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 114                         #dma-cells = <1>;
 115                         clocks = <&cru ACLK_DMAC2>;
 116                         clock-names = "apb_pclk";
 117                 };
 118
 119                 dmac_bus_ns: dma-controller@ff600000 {
 120                         compatible = "arm,pl330", "arm,primecell";
 121                         broken-no-flushp;
 122                         reg = <0xff600000 0x4000>;
 123                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 124                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 125                         #dma-cells = <1>;
 126                         clocks = <&cru ACLK_DMAC1>;
 127                         clock-names = "apb_pclk";
 128                         status = "disabled";
 129                 };
 130
 131                 dmac_bus_s: dma-controller@ffb20000 {
 132                         compatible = "arm,pl330", "arm,primecell";
 133                         broken-no-flushp;
 134                         reg = <0xffb20000 0x4000>;
 135                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 136                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 137                         #dma-cells = <1>;
 138                         clocks = <&cru ACLK_DMAC1>;
 139                         clock-names = "apb_pclk";
 140                 };
 141         };
 142
 143         xin24m: oscillator {
 144                 compatible = "fixed-clock";
 145                 clock-frequency = <24000000>;
 146                 clock-output-names = "xin24m";
 147                 #clock-cells = <0>;
 148         };
 149
 150         timer {
 151                 arm,use-physical-timer;
 152                 compatible = "arm,armv7-timer";
 153                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 155                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 156                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 157                 clock-frequency = <24000000>;
 158                 always-on;
 159         };
 160
 161         display-subsystem {
 162                 compatible = "rockchip,display-subsystem";
 163                 ports = <&vopl_out>, <&vopb_out>;
 164         };
 165
 166         sdmmc: dwmmc@ff0c0000 {
 167                 compatible = "rockchip,rk3288-dw-mshc";
 168                 max-frequency = <150000000>;
 169                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 170                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 171                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 172                 fifo-depth = <0x100>;
 173                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 174                 reg = <0xff0c0000 0x4000>;
 175                 status = "disabled";
 176         };
 177
 178         sdio0: dwmmc@ff0d0000 {
 179                 compatible = "rockchip,rk3288-dw-mshc";
 180                 max-frequency = <150000000>;
 181                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 182                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 183                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 184                 fifo-depth = <0x100>;
 185                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 186                 reg = <0xff0d0000 0x4000>;
 187                 status = "disabled";
 188         };
 189
 190         sdio1: dwmmc@ff0e0000 {
 191                 compatible = "rockchip,rk3288-dw-mshc";
 192                 max-frequency = <150000000>;
 193                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 194                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 195                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 196                 fifo-depth = <0x100>;
 197                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 198                 reg = <0xff0e0000 0x4000>;
 199                 status = "disabled";
 200         };
 201
 202         emmc: dwmmc@ff0f0000 {
 203                 compatible = "rockchip,rk3288-dw-mshc";
 204                 max-frequency = <150000000>;
 205                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 206                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 207                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 208                 fifo-depth = <0x100>;
 209                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 210                 reg = <0xff0f0000 0x4000>;
 211                 status = "disabled";
 212         };
 213
 214         saradc: saradc@ff100000 {
 215                 compatible = "rockchip,saradc";
 216                 reg = <0xff100000 0x100>;
 217                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 218                 #io-channel-cells = <1>;
 219                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 220                 clock-names = "saradc", "apb_pclk";
 221                 status = "disabled";
 222         };
 223
 224         spi0: spi@ff110000 {
 225                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 226                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 227                 clock-names = "spiclk", "apb_pclk";
 228                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 229                 dma-names = "tx", "rx";
 230                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 231                 pinctrl-names = "default";
 232                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 233                 reg = <0xff110000 0x1000>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 status = "disabled";
 237         };
 238
 239         spi1: spi@ff120000 {
 240                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 241                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 242                 clock-names = "spiclk", "apb_pclk";
 243                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 244                 dma-names = "tx", "rx";
 245                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 246                 pinctrl-names = "default";
 247                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 248                 reg = <0xff120000 0x1000>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 status = "disabled";
 252         };
 253
 254         spi2: spi@ff130000 {
 255                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 256                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 257                 clock-names = "spiclk", "apb_pclk";
 258                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 259                 dma-names = "tx", "rx";
 260                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 263                 reg = <0xff130000 0x1000>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 status = "disabled";
 267         };
 268
 269         i2c1: i2c@ff140000 {
 270                 compatible = "rockchip,rk3288-i2c";
 271                 reg = <0xff140000 0x1000>;
 272                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 clock-names = "i2c";
 276                 clocks = <&cru PCLK_I2C1>;
 277                 pinctrl-names = "default";
 278                 pinctrl-0 = <&i2c1_xfer>;
 279                 status = "disabled";
 280         };
 281
 282         i2c3: i2c@ff150000 {
 283                 compatible = "rockchip,rk3288-i2c";
 284                 reg = <0xff150000 0x1000>;
 285                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 clock-names = "i2c";
 289                 clocks = <&cru PCLK_I2C3>;
 290                 pinctrl-names = "default";
 291                 pinctrl-0 = <&i2c3_xfer>;
 292                 status = "disabled";
 293         };
 294
 295         i2c4: i2c@ff160000 {
 296                 compatible = "rockchip,rk3288-i2c";
 297                 reg = <0xff160000 0x1000>;
 298                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 clock-names = "i2c";
 302                 clocks = <&cru PCLK_I2C4>;
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&i2c4_xfer>;
 305                 status = "disabled";
 306         };
 307
 308         i2c5: i2c@ff170000 {
 309                 compatible = "rockchip,rk3288-i2c";
 310                 reg = <0xff170000 0x1000>;
 311                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 312                 #address-cells = <1>;
 313                 #size-cells = <0>;
 314                 clock-names = "i2c";
 315                 clocks = <&cru PCLK_I2C5>;
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&i2c5_xfer>;
 318                 status = "disabled";
 319         };
 320         uart0: serial@ff180000 {
 321                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 322                 reg = <0xff180000 0x100>;
 323                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 324                 reg-shift = <2>;
 325                 reg-io-width = <4>;
 326                 clock-frequency = <24000000>;
 327                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 328                 clock-names = "baudclk", "apb_pclk";
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&uart0_xfer>;
 331                 status = "disabled";
 332         };
 333
 334         uart1: serial@ff190000 {
 335                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 336                 reg = <0xff190000 0x100>;
 337                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 338                 reg-shift = <2>;
 339                 reg-io-width = <4>;
 340                 clock-frequency = <24000000>;
 341                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 342                 clock-names = "baudclk", "apb_pclk";
 343                 pinctrl-names = "default";
 344                 pinctrl-0 = <&uart1_xfer>;
 345                 status = "disabled";
 346         };
 347
 348         uart2: serial@ff690000 {
 349                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 350                 reg = <0xff690000 0x100>;
 351                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 352                 reg-shift = <2>;
 353                 reg-io-width = <4>;
 354                 clock-frequency = <24000000>;
 355                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 356                 clock-names = "baudclk", "apb_pclk";
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&uart2_xfer>;
 359                 status = "disabled";
 360         };
 361         uart3: serial@ff1b0000 {
 362                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 363                 reg = <0xff1b0000 0x100>;
 364                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 365                 reg-shift = <2>;
 366                 reg-io-width = <4>;
 367                 clock-frequency = <24000000>;
 368                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 369                 clock-names = "baudclk", "apb_pclk";
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&uart3_xfer>;
 372                 status = "disabled";
 373         };
 374
 375         uart4: serial@ff1c0000 {
 376                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 377                 reg = <0xff1c0000 0x100>;
 378                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 379                 reg-shift = <2>;
 380                 reg-io-width = <4>;
 381                 clock-frequency = <24000000>;
 382                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 383                 clock-names = "baudclk", "apb_pclk";
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&uart4_xfer>;
 386                 status = "disabled";
 387         };
 388         thermal: thermal-zones {
 389                 #include "rk3288-thermal.dtsi"
 390         };
 391
 392         tsadc: tsadc@ff280000 {
 393                 compatible = "rockchip,rk3288-tsadc";
 394                 reg = <0xff280000 0x100>;
 395                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 397                 clock-names = "tsadc", "apb_pclk";
 398                 resets = <&cru SRST_TSADC>;
 399                 reset-names = "tsadc-apb";
 400                 pinctrl-names = "otp_out";
 401                 pinctrl-0 = <&otp_out>;
 402                 #thermal-sensor-cells = <1>;
 403                 hw-shut-temp = <125000>;
 404                 status = "disabled";
 405         };
 406
 407         gmac: ethernet@ff290000 {
 408                 compatible = "rockchip,rk3288-gmac";
 409                 reg = <0xff290000 0x10000>;
 410                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 411                 interrupt-names = "macirq";
 412                 rockchip,grf = <&grf>;
 413                 clocks = <&cru SCLK_MAC>,
 414                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 415                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 416                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 417                 clock-names = "stmmaceth",
 418                         "mac_clk_rx", "mac_clk_tx",
 419                         "clk_mac_ref", "clk_mac_refout",
 420                         "aclk_mac", "pclk_mac";
 421         };
 422
 423         usb_host0_ehci: usb@ff500000 {
 424                 compatible = "generic-ehci";
 425                 reg = <0xff500000 0x100>;
 426                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 427                 clocks = <&cru HCLK_USBHOST0>;
 428                 clock-names = "usbhost";
 429                 phys = <&usbphy1>;
 430                 phy-names = "usb";
 431                 status = "disabled";
 432         };
 433
 434         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 435
 436         usb_host1: usb@ff540000 {
 437                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 438                                 "snps,dwc2";
 439                 reg = <0xff540000 0x40000>;
 440                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 441                 clocks = <&cru HCLK_USBHOST1>;
 442                 clock-names = "otg";
 443                 phys = <&usbphy2>;
 444                 phy-names = "usb2-phy";
 445                 status = "disabled";
 446         };
 447
 448         usb_otg: usb@ff580000 {
 449                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 450                                 "snps,dwc2";
 451                 reg = <0xff580000 0x40000>;
 452                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&cru HCLK_OTG0>;
 454                 clock-names = "otg";
 455                 dr_mode = "otg";
 456                 phys = <&usbphy0>;
 457                 phy-names = "usb2-phy";
 458                 status = "disabled";
 459         };
 460
 461         usb_hsic: usb@ff5c0000 {
 462                 compatible = "generic-ehci";
 463                 reg = <0xff5c0000 0x100>;
 464                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 465                 clocks = <&cru HCLK_HSIC>;
 466                 clock-names = "usbhost";
 467                 status = "disabled";
 468         };
 469
 470         dmc: dmc@ff610000 {
 471                 u-boot,dm-pre-reloc;
 472                 compatible = "rockchip,rk3288-dmc", "syscon";
 473                 rockchip,cru = <&cru>;
 474                 rockchip,grf = <&grf>;
 475                 rockchip,pmu = <&pmu>;
 476                 rockchip,sgrf = <&sgrf>;
 477                 rockchip,noc = <&noc>;
 478                 reg = <0xff610000 0x3fc
 479                        0xff620000 0x294
 480                        0xff630000 0x3fc
 481                        0xff640000 0x294>;
 482                 rockchip,sram = <&ddr_sram>;
 483                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 484                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 485                          <&cru ARMCLK>;
 486                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 487                               "pclk_ddrupctl1", "pclk_publ1",
 488                               "arm_clk";
 489         };
 490
 491         i2c0: i2c@ff650000 {
 492                 compatible = "rockchip,rk3288-i2c";
 493                 reg = <0xff650000 0x1000>;
 494                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 clock-names = "i2c";
 498                 clocks = <&cru PCLK_I2C0>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c0_xfer>;
 501                 status = "disabled";
 502         };
 503
 504         i2c2: i2c@ff660000 {
 505                 compatible = "rockchip,rk3288-i2c";
 506                 reg = <0xff660000 0x1000>;
 507                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510                 clock-names = "i2c";
 511                 clocks = <&cru PCLK_I2C2>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2c2_xfer>;
 514                 status = "disabled";
 515         };
 516
 517         pwm0: pwm@ff680000 {
 518                 compatible = "rockchip,rk3288-pwm";
 519                 reg = <0xff680000 0x10>;
 520                 #pwm-cells = <3>;
 521                 pinctrl-names = "default";
 522                 pinctrl-0 = <&pwm0_pin>;
 523                 clocks = <&cru PCLK_PWM>;
 524                 clock-names = "pwm";
 525                 rockchip,grf = <&grf>;
 526                 status = "disabled";
 527         };
 528
 529         pwm1: pwm@ff680010 {
 530                 compatible = "rockchip,rk3288-pwm";
 531                 reg = <0xff680010 0x10>;
 532                 #pwm-cells = <3>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&pwm1_pin>;
 535                 clocks = <&cru PCLK_PWM>;
 536                 clock-names = "pwm";
 537                 rockchip,grf = <&grf>;
 538                 status = "disabled";
 539         };
 540
 541         pwm2: pwm@ff680020 {
 542                 compatible = "rockchip,rk3288-pwm";
 543                 reg = <0xff680020 0x10>;
 544                 #pwm-cells = <3>;
 545                 pinctrl-names = "default";
 546                 pinctrl-0 = <&pwm2_pin>;
 547                 clocks = <&cru PCLK_PWM>;
 548                 clock-names = "pwm";
 549                 rockchip,grf = <&grf>;
 550                 status = "disabled";
 551         };
 552
 553         pwm3: pwm@ff680030 {
 554                 compatible = "rockchip,rk3288-pwm";
 555                 reg = <0xff680030 0x10>;
 556                 #pwm-cells = <2>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&pwm3_pin>;
 559                 clocks = <&cru PCLK_PWM>;
 560                 clock-names = "pwm";
 561                 rockchip,grf = <&grf>;
 562                 status = "disabled";
 563         };
 564
 565         bus_intmem@ff700000 {
 566                 compatible = "mmio-sram";
 567                 reg = <0xff700000 0x18000>;
 568                 #address-cells = <1>;
 569                 #size-cells = <1>;
 570                 ranges = <0 0xff700000 0x18000>;
 571                 smp-sram@0 {
 572                         compatible = "rockchip,rk3066-smp-sram";
 573                         reg = <0x00 0x10>;
 574                 };
 575                 ddr_sram: ddr-sram@1000 {
 576                         compatible = "rockchip,rk3288-ddr-sram";
 577                         reg = <0x1000 0x4000>;
 578                 };
 579         };
 580
 581         sram@ff720000 {
 582                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 583                 reg = <0xff720000 0x1000>;
 584         };
 585
 586         pmu: power-management@ff730000 {
 587                 u-boot,dm-pre-reloc;
 588                 compatible = "rockchip,rk3288-pmu", "syscon";
 589                 reg = <0xff730000 0x100>;
 590         };
 591
 592         sgrf: syscon@ff740000 {
 593                 u-boot,dm-pre-reloc;
 594                 compatible = "rockchip,rk3288-sgrf", "syscon";
 595                 reg = <0xff740000 0x1000>;
 596         };
 597
 598         cru: clock-controller@ff760000 {
 599                 compatible = "rockchip,rk3288-cru";
 600                 reg = <0xff760000 0x1000>;
 601                 rockchip,grf = <&grf>;
 602                 u-boot,dm-pre-reloc;
 603                 #clock-cells = <1>;
 604                 #reset-cells = <1>;
 605                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 606                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 607                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 608                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 609                                   <&cru PCLK_PERI>;
 610                 assigned-clock-rates = <594000000>, <400000000>,
 611                                        <500000000>, <300000000>,
 612                                        <150000000>, <75000000>,
 613                                        <300000000>, <150000000>,
 614                                        <75000000>;
 615         };
 616
 617         grf: syscon@ff770000 {
 618                 u-boot,dm-pre-reloc;
 619                 compatible = "rockchip,rk3288-grf", "syscon";
 620                 reg = <0xff770000 0x1000>;
 621         };
 622
 623         wdt: watchdog@ff800000 {
 624                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 625                 reg = <0xff800000 0x100>;
 626                 clocks = <&cru PCLK_WDT>;
 627                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 628                 status = "disabled";
 629         };
 630
 631         spdif: sound@ff88b0000 {
 632                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 633                 reg = <0xff8b0000 0x10000>;
 634                 #sound-dai-cells = <0>;
 635                 clock-names = "hclk", "mclk";
 636                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 637                 dmas = <&dmac_bus_s 3>;
 638                 dma-names = "tx";
 639                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 640                 pinctrl-names = "default";
 641                 pinctrl-0 = <&spdif_tx>;
 642                 rockchip,grf = <&grf>;
 643                 status = "disabled";
 644         };
 645
 646         i2s: i2s@ff890000 {
 647                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 648                 reg = <0xff890000 0x10000>;
 649                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 650                 #address-cells = <1>;
 651                 #size-cells = <0>;
 652                 #sound-dai-cells = <1>;
 653                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 654                 dma-names = "tx", "rx";
 655                 clock-names = "i2s_hclk", "i2s_clk";
 656                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 657                 pinctrl-names = "default";
 658                 pinctrl-0 = <&i2s0_bus>;
 659                 status = "disabled";
 660         };
 661
 662         vopb: vop@ff930000 {
 663                 u-boot,dm-pre-reloc;
 664                 compatible = "rockchip,rk3288-vop";
 665                 reg = <0xff930000 0x19c>;
 666                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 667                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 668                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 669                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 670                 reset-names = "axi", "ahb", "dclk";
 671                 iommus = <&vopb_mmu>;
 672                 power-domains = <&power RK3288_PD_VIO>;
 673                 status = "disabled";
 674                 vopb_out: port {
 675                         #address-cells = <1>;
 676                         #size-cells = <0>;
 677                         vopb_out_edp: endpoint@0 {
 678                                 reg = <0>;
 679                                 remote-endpoint = <&edp_in_vopb>;
 680                         };
 681                         vopb_out_hdmi: endpoint@1 {
 682                                 reg = <1>;
 683                                 remote-endpoint = <&hdmi_in_vopb>;
 684                         };
 685                         vopb_out_lvds: endpoint@2 {
 686                                 reg = <2>;
 687                                 remote-endpoint = <&lvds_in_vopb>;
 688                         };
 689                         vopb_out_mipi: endpoint@3 {
 690                                 reg = <3>;
 691                                 remote-endpoint = <&mipi_in_vopb>;
 692                         };
 693
 694                 };
 695         };
 696
 697         vopb_mmu: iommu@ff930300 {
 698                 compatible = "rockchip,iommu";
 699                 reg = <0xff930300 0x100>;
 700                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 701                 interrupt-names = "vopb_mmu";
 702                 power-domains = <&power RK3288_PD_VIO>;
 703                 #iommu-cells = <0>;
 704                 status = "disabled";
 705         };
 706
 707         vopl: vop@ff940000 {
 708                 compatible = "rockchip,rk3288-vop";
 709                 reg = <0xff940000 0x19c>;
 710                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 711                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 712                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 713                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 714                 reset-names = "axi", "ahb", "dclk";
 715                 iommus = <&vopl_mmu>;
 716                 power-domains = <&power RK3288_PD_VIO>;
 717                 status = "disabled";
 718                 u-boot,dm-pre-reloc;
 719                 vopl_out: port {
 720                         #address-cells = <1>;
 721                         #size-cells = <0>;
 722                         vopl_out_edp: endpoint@0 {
 723                                 reg = <0>;
 724                                 remote-endpoint = <&edp_in_vopl>;
 725                         };
 726                         vopl_out_hdmi: endpoint@1 {
 727                                 reg = <1>;
 728                                 remote-endpoint = <&hdmi_in_vopl>;
 729                         };
 730                         vopl_out_lvds: endpoint@2 {
 731                                 reg = <2>;
 732                                 remote-endpoint = <&lvds_in_vopl>;
 733                         };
 734                         vopl_out_mipi: endpoint@3 {
 735                                 reg = <3>;
 736                                 remote-endpoint = <&mipi_in_vopl>;
 737                         };
 738
 739                 };
 740         };
 741
 742         vopl_mmu: iommu@ff940300 {
 743                 compatible = "rockchip,iommu";
 744                 reg = <0xff940300 0x100>;
 745                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 746                 interrupt-names = "vopl_mmu";
 747                 power-domains = <&power RK3288_PD_VIO>;
 748                 #iommu-cells = <0>;
 749                 status = "disabled";
 750         };
 751
 752         edp: edp@ff970000 {
 753                 compatible = "rockchip,rk3288-edp";
 754                 reg = <0xff970000 0x4000>;
 755                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 756                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
 757                 rockchip,grf = <&grf>;
 758                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 759                 resets = <&cru 111>;
 760                 reset-names = "edp";
 761                 power-domains = <&power RK3288_PD_VIO>;
 762                 status = "disabled";
 763                 ports {
 764                         edp_in: port {
 765                                 #address-cells = <1>;
 766                                 #size-cells = <0>;
 767                                 edp_in_vopb: endpoint@0 {
 768                                         reg = <0>;
 769                                         remote-endpoint = <&vopb_out_edp>;
 770                                 };
 771                                 edp_in_vopl: endpoint@1 {
 772                                         reg = <1>;
 773                                         remote-endpoint = <&vopl_out_edp>;
 774                                 };
 775                         };
 776                 };
 777         };
 778
 779         hdmi: hdmi@ff980000 {
 780                 compatible = "rockchip,rk3288-dw-hdmi";
 781                 reg = <0xff980000 0x20000>;
 782                 reg-io-width = <4>;
 783                 ddc-i2c-bus = <&i2c5>;
 784                 rockchip,grf = <&grf>;
 785                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 786                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 787                 clock-names = "iahb", "isfr";
 788                 status = "disabled";
 789                 ports {
 790                         hdmi_in: port {
 791                                 #address-cells = <1>;
 792                                 #size-cells = <0>;
 793                                 hdmi_in_vopb: endpoint@0 {
 794                                         reg = <0>;
 795                                         remote-endpoint = <&vopb_out_hdmi>;
 796                                 };
 797                                 hdmi_in_vopl: endpoint@1 {
 798                                         reg = <1>;
 799                                         remote-endpoint = <&vopl_out_hdmi>;
 800                                 };
 801                         };
 802                 };
 803         };
 804
 805         lvds: lvds@ff96c000 {
 806                 compatible = "rockchip,rk3288-lvds";
 807                 reg = <0xff96c000 0x4000>;
 808                 clocks = <&cru PCLK_LVDS_PHY>;
 809                 clock-names = "pclk_lvds";
 810                 pinctrl-names = "default";
 811                 pinctrl-0 = <&lcdc0_ctl>;
 812                 rockchip,grf = <&grf>;
 813                 status = "disabled";
 814                 ports {
 815                         #address-cells = <1>;
 816                         #size-cells = <0>;
 817                         lvds_in: port@0 {
 818                                 reg = <0>;
 819                                 #address-cells = <1>;
 820                                 #size-cells = <0>;
 821                                 lvds_in_vopb: endpoint@0 {
 822                                         reg = <0>;
 823                                         remote-endpoint = <&vopb_out_lvds>;
 824                                 };
 825                                 lvds_in_vopl: endpoint@1 {
 826                                         reg = <1>;
 827                                         remote-endpoint = <&vopl_out_lvds>;
 828                                 };
 829                         };
 830                 };
 831         };
 832
 833         mipi_dsi0: mipi@ff960000 {
 834                 compatible = "rockchip,rk3288_mipi_dsi";
 835                 reg = <0xff960000 0x4000>;
 836                 clocks = <&cru PCLK_MIPI_DSI0>;
 837                 clock-names = "pclk_mipi";
 838                 /*pinctrl-names = "default";
 839                 pinctrl-0 = <&lcdc0_ctl>;*/
 840                 rockchip,grf = <&grf>;
 841                 #address-cells = <1>;
 842                 #size-cells = <0>;
 843                 status = "disabled";
 844                 ports {
 845                         reg = <1>;
 846                         mipi_in: port {
 847                                 #address-cells = <1>;
 848                                 #size-cells = <0>;
 849                                 mipi_in_vopb: endpoint@0 {
 850                                         reg = <0>;
 851                                         remote-endpoint = <&vopb_out_mipi>;
 852                                 };
 853                                 mipi_in_vopl: endpoint@1 {
 854                                         reg = <1>;
 855                                         remote-endpoint = <&vopl_out_mipi>;
 856                                 };
 857                         };
 858                 };
 859         };
 860
 861         hdmi_audio: hdmi_audio {
 862                 compatible = "rockchip,rk3288-hdmi-audio";
 863                 i2s-controller = <&i2s>;
 864                 status = "disable";
 865         };
 866
 867         vpu: video-codec@ff9a0000 {
 868                 compatible = "rockchip,rk3288-vpu";
 869                 reg = <0xff9a0000 0x800>;
 870                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 871                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 872                 interrupt-names = "vepu", "vdpu";
 873                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 874                 clock-names = "aclk_vcodec", "hclk_vcodec";
 875                 power-domains = <&power RK3288_PD_VIDEO>;
 876                 iommus = <&vpu_mmu>;
 877         };
 878
 879         vpu_mmu: iommu@ff9a0800 {
 880                 compatible = "rockchip,iommu";
 881                 reg = <0xff9a0800 0x100>;
 882                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 883                 interrupt-names = "vpu_mmu";
 884                 power-domains = <&power RK3288_PD_VIDEO>;
 885                 #iommu-cells = <0>;
 886         };
 887
 888         gpu: gpu@ffa30000 {
 889                 compatible = "arm,malit764",
 890                              "arm,malit76x",
 891                              "arm,malit7xx",
 892                              "arm,mali-midgard";
 893                 reg = <0xffa30000 0x10000>;
 894                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 895                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 896                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 897                 interrupt-names = "JOB", "MMU", "GPU";
 898                 clocks = <&cru ACLK_GPU>;
 899                 clock-names = "aclk_gpu";
 900                 operating-points = <
 901                         /* KHz uV */
 902                         100000 950000
 903                         200000 950000
 904                         300000 1000000
 905                         400000 1100000
 906                         /* 500000 1200000 - See crosbug.com/p/33857 */
 907                         600000 1250000
 908                 >;
 909                 power-domains = <&power RK3288_PD_GPU>;
 910                 status = "disabled";
 911         };
 912
 913         noc: syscon@ffac0000 {
 914                 u-boot,dm-pre-reloc;
 915                 compatible = "rockchip,rk3288-noc", "syscon";
 916                 reg = <0xffac0000 0x2000>;
 917         };
 918
 919         efuse: efuse@ffb40000 {
 920                 compatible = "rockchip,rk3288-efuse";
 921                 reg = <0xffb40000 0x10000>;
 922                 status = "disabled";
 923         };
 924
 925         gic: interrupt-controller@ffc01000 {
 926                 compatible = "arm,gic-400";
 927                 interrupt-controller;
 928                 #interrupt-cells = <3>;
 929                 #address-cells = <0>;
 930
 931                 reg = <0xffc01000 0x1000>,
 932                       <0xffc02000 0x1000>,
 933                       <0xffc04000 0x2000>,
 934                       <0xffc06000 0x2000>;
 935                 interrupts = <GIC_PPI 9 0xf04>;
 936         };
 937
 938         cpuidle: cpuidle {
 939                 compatible = "rockchip,rk3288-cpuidle";
 940         };
 941
 942         usbphy: phy {
 943                 compatible = "rockchip,rk3288-usb-phy";
 944                 rockchip,grf = <&grf>;
 945                 #address-cells = <1>;
 946                 #size-cells = <0>;
 947                 status = "disabled";
 948
 949                 usbphy0: usb-phy0 {
 950                         #phy-cells = <0>;
 951                         reg = <0x320>;
 952                         clocks = <&cru SCLK_OTGPHY0>;
 953                         clock-names = "phyclk";
 954                 };
 955
 956                 usbphy1: usb-phy1 {
 957                         #phy-cells = <0>;
 958                         reg = <0x334>;
 959                         clocks = <&cru SCLK_OTGPHY1>;
 960                         clock-names = "phyclk";
 961                 };
 962
 963                 usbphy2: usb-phy2 {
 964                         #phy-cells = <0>;
 965                         reg = <0x348>;
 966                         clocks = <&cru SCLK_OTGPHY2>;
 967                         clock-names = "phyclk";
 968                 };
 969         };
 970
 971         pinctrl: pinctrl {
 972                 compatible = "rockchip,rk3288-pinctrl";
 973                 rockchip,grf = <&grf>;
 974                 rockchip,pmu = <&pmu>;
 975                 #address-cells = <1>;
 976                 #size-cells = <1>;
 977                 ranges;
 978
 979                 gpio0: gpio0@ff750000 {
 980                         compatible = "rockchip,gpio-bank";
 981                         reg =   <0xff750000 0x100>;
 982                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 983                         clocks = <&cru PCLK_GPIO0>;
 984
 985                         gpio-controller;
 986                         #gpio-cells = <2>;
 987
 988                         interrupt-controller;
 989                         #interrupt-cells = <2>;
 990                 };
 991
 992                 gpio1: gpio1@ff780000 {
 993                         compatible = "rockchip,gpio-bank";
 994                         reg = <0xff780000 0x100>;
 995                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 996                         clocks = <&cru PCLK_GPIO1>;
 997
 998                         gpio-controller;
 999                         #gpio-cells = <2>;
1000
1001                         interrupt-controller;
1002                         #interrupt-cells = <2>;
1003                 };
1004
1005                 gpio2: gpio2@ff790000 {
1006                         compatible = "rockchip,gpio-bank";
1007                         reg = <0xff790000 0x100>;
1008                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1009                         clocks = <&cru PCLK_GPIO2>;
1010
1011                         gpio-controller;
1012                         #gpio-cells = <2>;
1013
1014                         interrupt-controller;
1015                         #interrupt-cells = <2>;
1016                 };
1017
1018                 gpio3: gpio3@ff7a0000 {
1019                         compatible = "rockchip,gpio-bank";
1020                         reg = <0xff7a0000 0x100>;
1021                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1022                         clocks = <&cru PCLK_GPIO3>;
1023
1024                         gpio-controller;
1025                         #gpio-cells = <2>;
1026
1027                         interrupt-controller;
1028                         #interrupt-cells = <2>;
1029                 };
1030
1031                 gpio4: gpio4@ff7b0000 {
1032                         compatible = "rockchip,gpio-bank";
1033                         reg = <0xff7b0000 0x100>;
1034                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1035                         clocks = <&cru PCLK_GPIO4>;
1036
1037                         gpio-controller;
1038                         #gpio-cells = <2>;
1039
1040                         interrupt-controller;
1041                         #interrupt-cells = <2>;
1042                 };
1043
1044                 gpio5: gpio5@ff7c0000 {
1045                         compatible = "rockchip,gpio-bank";
1046                         reg = <0xff7c0000 0x100>;
1047                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1048                         clocks = <&cru PCLK_GPIO5>;
1049
1050                         gpio-controller;
1051                         #gpio-cells = <2>;
1052
1053                         interrupt-controller;
1054                         #interrupt-cells = <2>;
1055                 };
1056
1057                 gpio6: gpio6@ff7d0000 {
1058                         compatible = "rockchip,gpio-bank";
1059                         reg = <0xff7d0000 0x100>;
1060                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1061                         clocks = <&cru PCLK_GPIO6>;
1062
1063                         gpio-controller;
1064                         #gpio-cells = <2>;
1065
1066                         interrupt-controller;
1067                         #interrupt-cells = <2>;
1068                 };
1069
1070                 gpio7: gpio7@ff7e0000 {
1071                         compatible = "rockchip,gpio-bank";
1072                         reg = <0xff7e0000 0x100>;
1073                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1074                         clocks = <&cru PCLK_GPIO7>;
1075
1076                         gpio-controller;
1077                         #gpio-cells = <2>;
1078
1079                         interrupt-controller;
1080                         #interrupt-cells = <2>;
1081                 };
1082
1083                 gpio8: gpio8@ff7f0000 {
1084                         compatible = "rockchip,gpio-bank";
1085                         reg = <0xff7f0000 0x100>;
1086                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1087                         clocks = <&cru PCLK_GPIO8>;
1088
1089                         gpio-controller;
1090                         #gpio-cells = <2>;
1091
1092                         interrupt-controller;
1093                         #interrupt-cells = <2>;
1094                 };
1095
1096                 pcfg_pull_up: pcfg-pull-up {
1097                         bias-pull-up;
1098                 };
1099
1100                 pcfg_pull_down: pcfg-pull-down {
1101                         bias-pull-down;
1102                 };
1103
1104                 pcfg_pull_none: pcfg-pull-none {
1105                         bias-disable;
1106                 };
1107
1108                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1109                         bias-disable;
1110                         drive-strength = <12>;
1111                 };
1112
1113                 sleep {
1114                         global_pwroff: global-pwroff {
1115                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1116                         };
1117
1118                         ddrio_pwroff: ddrio-pwroff {
1119                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1120                         };
1121
1122                         ddr0_retention: ddr0-retention {
1123                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1124                         };
1125
1126                         ddr1_retention: ddr1-retention {
1127                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1128                         };
1129                 };
1130
1131                 i2c0 {
1132                         i2c0_xfer: i2c0-xfer {
1133                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1134                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1135                         };
1136                 };
1137
1138                 i2c1 {
1139                         i2c1_xfer: i2c1-xfer {
1140                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1141                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1142                         };
1143                 };
1144
1145                 i2c2 {
1146                         i2c2_xfer: i2c2-xfer {
1147                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1148                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1149                         };
1150                 };
1151
1152                 i2c3 {
1153                         i2c3_xfer: i2c3-xfer {
1154                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1155                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1156                         };
1157                 };
1158
1159                 i2c4 {
1160                         i2c4_xfer: i2c4-xfer {
1161                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1162                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1163                         };
1164                 };
1165
1166                 i2c5 {
1167                         i2c5_xfer: i2c5-xfer {
1168                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1169                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1170                         };
1171                 };
1172
1173                 i2s0 {
1174                         i2s0_bus: i2s0-bus {
1175                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1176                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1177                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1178                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1179                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1180                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1181                         };
1182                 };
1183
1184                 lcdc0 {
1185                         lcdc0_ctl: lcdc0-ctl {
1186                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1187                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1188                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1189                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1190                         };
1191                 };
1192
1193                 sdmmc {
1194                         sdmmc_clk: sdmmc-clk {
1195                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1196                         };
1197
1198                         sdmmc_cmd: sdmmc-cmd {
1199                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1200                         };
1201
1202                         sdmmc_cd: sdmcc-cd {
1203                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1204                         };
1205
1206                         sdmmc_bus1: sdmmc-bus1 {
1207                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1208                         };
1209
1210                         sdmmc_bus4: sdmmc-bus4 {
1211                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1212                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1213                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1214                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1215                         };
1216                 };
1217
1218                 sdio0 {
1219                         sdio0_bus1: sdio0-bus1 {
1220                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1221                         };
1222
1223                         sdio0_bus4: sdio0-bus4 {
1224                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1225                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1226                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1227                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1228                         };
1229
1230                         sdio0_cmd: sdio0-cmd {
1231                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1232                         };
1233
1234                         sdio0_clk: sdio0-clk {
1235                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1236                         };
1237
1238                         sdio0_cd: sdio0-cd {
1239                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1240                         };
1241
1242                         sdio0_wp: sdio0-wp {
1243                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1244                         };
1245
1246                         sdio0_pwr: sdio0-pwr {
1247                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1248                         };
1249
1250                         sdio0_bkpwr: sdio0-bkpwr {
1251                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1252                         };
1253
1254                         sdio0_int: sdio0-int {
1255                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1256                         };
1257                 };
1258
1259                 sdio1 {
1260                         sdio1_bus1: sdio1-bus1 {
1261                                 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1262                         };
1263
1264                         sdio1_bus4: sdio1-bus4 {
1265                                 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1266                                                 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1267                                                 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1268                                                 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1269                         };
1270
1271                         sdio1_cd: sdio1-cd {
1272                                 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1273                         };
1274
1275                         sdio1_wp: sdio1-wp {
1276                                 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1277                         };
1278
1279                         sdio1_bkpwr: sdio1-bkpwr {
1280                                 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1281                         };
1282
1283                         sdio1_int: sdio1-int {
1284                                 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1285                         };
1286
1287                         sdio1_cmd: sdio1-cmd {
1288                                 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1289                         };
1290
1291                         sdio1_clk: sdio1-clk {
1292                                 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1293                         };
1294
1295                         sdio1_pwr: sdio1-pwr {
1296                                 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1297                         };
1298                 };
1299
1300                 emmc {
1301                         emmc_clk: emmc-clk {
1302                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1303                         };
1304
1305                         emmc_cmd: emmc-cmd {
1306                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1307                         };
1308
1309                         emmc_pwr: emmc-pwr {
1310                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1311                         };
1312
1313                         emmc_bus1: emmc-bus1 {
1314                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1315                         };
1316
1317                         emmc_bus4: emmc-bus4 {
1318                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1319                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1320                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1321                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1322                         };
1323
1324                         emmc_bus8: emmc-bus8 {
1325                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1326                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1327                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1328                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1329                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1330                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1331                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1332                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1333                         };
1334                 };
1335
1336                 spi0 {
1337                         spi0_clk: spi0-clk {
1338                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1339                         };
1340                         spi0_cs0: spi0-cs0 {
1341                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1342                         };
1343                         spi0_tx: spi0-tx {
1344                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1345                         };
1346                         spi0_rx: spi0-rx {
1347                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1348                         };
1349                         spi0_cs1: spi0-cs1 {
1350                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1351                         };
1352                 };
1353                 spi1 {
1354                         spi1_clk: spi1-clk {
1355                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1356                         };
1357                         spi1_cs0: spi1-cs0 {
1358                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1359                         };
1360                         spi1_rx: spi1-rx {
1361                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1362                         };
1363                         spi1_tx: spi1-tx {
1364                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1365                         };
1366                 };
1367
1368                 spi2 {
1369                         spi2_cs1: spi2-cs1 {
1370                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1371                         };
1372                         spi2_clk: spi2-clk {
1373                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1374                         };
1375                         spi2_cs0: spi2-cs0 {
1376                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1377                         };
1378                         spi2_rx: spi2-rx {
1379                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1380                         };
1381                         spi2_tx: spi2-tx {
1382                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1383                         };
1384                 };
1385
1386                 uart0 {
1387                         uart0_xfer: uart0-xfer {
1388                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1389                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1390                         };
1391
1392                         uart0_cts: uart0-cts {
1393                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1394                         };
1395
1396                         uart0_rts: uart0-rts {
1397                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1398                         };
1399                 };
1400
1401                 uart1 {
1402                         uart1_xfer: uart1-xfer {
1403                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1404                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1405                         };
1406
1407                         uart1_cts: uart1-cts {
1408                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1409                         };
1410
1411                         uart1_rts: uart1-rts {
1412                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1413                         };
1414                 };
1415
1416                 uart2 {
1417                         uart2_xfer: uart2-xfer {
1418                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1419                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1420                         };
1421                         /* no rts / cts for uart2 */
1422                 };
1423
1424                 uart3 {
1425                         uart3_xfer: uart3-xfer {
1426                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1427                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1428                         };
1429
1430                         uart3_cts: uart3-cts {
1431                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1432                         };
1433
1434                         uart3_rts: uart3-rts {
1435                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1436                         };
1437                 };
1438
1439                 uart4 {
1440                         uart4_xfer: uart4-xfer {
1441                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1442                                                 <5 13 3 &pcfg_pull_none>;
1443                         };
1444
1445                         uart4_cts: uart4-cts {
1446                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1447                         };
1448
1449                         uart4_rts: uart4-rts {
1450                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1451                         };
1452                 };
1453
1454                 tsadc {
1455                         otp_out: otp-out {
1456                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1457                         };
1458                 };
1459
1460                 pwm0 {
1461                         pwm0_pin: pwm0-pin {
1462                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1463                         };
1464                 };
1465
1466                 pwm1 {
1467                         pwm1_pin: pwm1-pin {
1468                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1469                         };
1470                 };
1471
1472                 pwm2 {
1473                         pwm2_pin: pwm2-pin {
1474                                 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1475                         };
1476                 };
1477
1478                 pwm3 {
1479                         pwm3_pin: pwm3-pin {
1480                                 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1481                         };
1482                 };
1483
1484                 gmac {
1485                         rgmii_pins: rgmii-pins {
1486                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1487                                                 <3 31 3 &pcfg_pull_none>,
1488                                                 <3 26 3 &pcfg_pull_none>,
1489                                                 <3 27 3 &pcfg_pull_none>,
1490                                                 <3 28 3 &pcfg_pull_none_12ma>,
1491                                                 <3 29 3 &pcfg_pull_none_12ma>,
1492                                                 <3 24 3 &pcfg_pull_none_12ma>,
1493                                                 <3 25 3 &pcfg_pull_none_12ma>,
1494                                                 <4 0 3 &pcfg_pull_none>,
1495                                                 <4 5 3 &pcfg_pull_none>,
1496                                                 <4 6 3 &pcfg_pull_none>,
1497                                                 <4 9 3 &pcfg_pull_none_12ma>,
1498                                                 <4 4 3 &pcfg_pull_none_12ma>,
1499                                                 <4 1 3 &pcfg_pull_none>,
1500                                                 <4 3 3 &pcfg_pull_none>;
1501                         };
1502
1503                         rmii_pins: rmii-pins {
1504                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1505                                                 <3 31 3 &pcfg_pull_none>,
1506                                                 <3 28 3 &pcfg_pull_none>,
1507                                                 <3 29 3 &pcfg_pull_none>,
1508                                                 <4 0 3 &pcfg_pull_none>,
1509                                                 <4 5 3 &pcfg_pull_none>,
1510                                                 <4 4 3 &pcfg_pull_none>,
1511                                                 <4 1 3 &pcfg_pull_none>,
1512                                                 <4 2 3 &pcfg_pull_none>,
1513                                                 <4 3 3 &pcfg_pull_none>;
1514                         };
1515                 };
1516
1517                 spdif {
1518                         spdif_tx: spdif-tx {
1519                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1520                         };
1521                 };
1522         };
1523
1524         power: power-controller {
1525                 compatible = "rockchip,rk3288-power-controller";
1526                 #power-domain-cells = <1>;
1527                 rockchip,pmu = <&pmu>;
1528                 #address-cells = <1>;
1529                 #size-cells = <0>;
1530
1531                 pd_gpu {
1532                         reg = <RK3288_PD_GPU>;
1533                         clocks = <&cru ACLK_GPU>;
1534                 };
1535
1536                 pd_hevc {
1537                         reg = <RK3288_PD_HEVC>;
1538                         clocks = <&cru ACLK_HEVC>,
1539                                  <&cru SCLK_HEVC_CABAC>,
1540                                  <&cru SCLK_HEVC_CORE>,
1541                                  <&cru HCLK_HEVC>;
1542                 };
1543
1544                 pd_vio {
1545                         reg = <RK3288_PD_VIO>;
1546                         clocks = <&cru ACLK_IEP>,
1547                                  <&cru ACLK_ISP>,
1548                                  <&cru ACLK_RGA>,
1549                                  <&cru ACLK_VIP>,
1550                                  <&cru ACLK_VOP0>,
1551                                  <&cru ACLK_VOP1>,
1552                                  <&cru DCLK_VOP0>,
1553                                  <&cru DCLK_VOP1>,
1554                                  <&cru HCLK_IEP>,
1555                                  <&cru HCLK_ISP>,
1556                                  <&cru HCLK_RGA>,
1557                                  <&cru HCLK_VIP>,
1558                                  <&cru HCLK_VOP0>,
1559                                  <&cru HCLK_VOP1>,
1560                                  <&cru PCLK_EDP_CTRL>,
1561                                  <&cru PCLK_HDMI_CTRL>,
1562                                  <&cru PCLK_LVDS_PHY>,
1563                                  <&cru PCLK_MIPI_CSI>,
1564                                  <&cru PCLK_MIPI_DSI0>,
1565                                  <&cru PCLK_MIPI_DSI1>,
1566                                  <&cru SCLK_EDP_24M>,
1567                                  <&cru SCLK_EDP>,
1568                                  <&cru SCLK_HDMI_CEC>,
1569                                  <&cru SCLK_HDMI_HDCP>,
1570                                  <&cru SCLK_ISP_JPE>,
1571                                  <&cru SCLK_ISP>,
1572                                  <&cru SCLK_RGA>;
1573                 };
1574
1575                 pd_video {
1576                         reg = <RK3288_PD_VIDEO>;
1577                         clocks = <&cru ACLK_VCODEC>,
1578                                  <&cru HCLK_VCODEC>;
1579                 };
1580         };
1581 };