arch/arm/dts/rk3288.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power-domain/rk3288.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/video/rk3288.h>
  11 #include "skeleton.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3288";
  15
  16         interrupt-parent = <&gic>;
  17         aliases {
  18                 gpio0 = &gpio0;
  19                 gpio1 = &gpio1;
  20                 gpio2 = &gpio2;
  21                 gpio3 = &gpio3;
  22                 gpio4 = &gpio4;
  23                 gpio5 = &gpio5;
  24                 gpio6 = &gpio6;
  25                 gpio7 = &gpio7;
  26                 gpio8 = &gpio8;
  27                 i2c0 = &i2c0;
  28                 i2c1 = &i2c1;
  29                 i2c2 = &i2c2;
  30                 i2c3 = &i2c3;
  31                 i2c4 = &i2c4;
  32                 i2c5 = &i2c5;
  33                 mmc0 = &emmc;
  34                 mmc1 = &sdmmc;
  35                 mmc2 = &sdio0;
  36                 mmc3 = &sdio1;
  37                 mshc0 = &emmc;
  38                 mshc1 = &sdmmc;
  39                 mshc2 = &sdio0;
  40                 mshc3 = &sdio1;
  41                 serial0 = &uart0;
  42                 serial1 = &uart1;
  43                 serial2 = &uart2;
  44                 serial3 = &uart3;
  45                 serial4 = &uart4;
  46                 spi0 = &spi0;
  47                 spi1 = &spi1;
  48                 spi2 = &spi2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 enable-method = "rockchip,rk3066-smp";
  55                 rockchip,pmu = <&pmu>;
  56
  57                 cpu0: cpu@500 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a12";
  60                         reg = <0x500>;
  61                         operating-points = <
  62                                 /* KHz    uV */
  63                                 1800000 1400000
  64                                 1704000 1350000
  65                                 1608000 1300000
  66                                 1512000 1250000
  67                                 1416000 1200000
  68                                 1200000 1100000
  69                                 1008000 1050000
  70                                  816000 1000000
  71                                  696000  950000
  72                                  600000  900000
  73                                  408000  900000
  74                                  216000  900000
  75                                  126000  900000
  76                         >;
  77                         #cooling-cells = <2>; /* min followed by max */
  78                         clock-latency = <40000>;
  79                         clocks = <&cru ARMCLK>;
  80                         resets = <&cru SRST_CORE0>;
  81                 };
  82                 cpu@501 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a12";
  85                         reg = <0x501>;
  86                         resets = <&cru SRST_CORE1>;
  87                 };
  88                 cpu@502 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a12";
  91                         reg = <0x502>;
  92                         resets = <&cru SRST_CORE2>;
  93                 };
  94                 cpu@503 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a12";
  97                         reg = <0x503>;
  98                         resets = <&cru SRST_CORE3>;
  99                 };
 100         };
 101
 102         amba {
 103                 compatible = "arm,amba-bus";
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 ranges;
 107
 108                 dmac_peri: dma-controller@ff250000 {
 109                         compatible = "arm,pl330", "arm,primecell";
 110                         broken-no-flushp;
 111                         reg = <0xff250000 0x4000>;
 112                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 113                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 114                         #dma-cells = <1>;
 115                         clocks = <&cru ACLK_DMAC2>;
 116                         clock-names = "apb_pclk";
 117                 };
 118
 119                 dmac_bus_ns: dma-controller@ff600000 {
 120                         compatible = "arm,pl330", "arm,primecell";
 121                         broken-no-flushp;
 122                         reg = <0xff600000 0x4000>;
 123                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 124                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 125                         #dma-cells = <1>;
 126                         clocks = <&cru ACLK_DMAC1>;
 127                         clock-names = "apb_pclk";
 128                         status = "disabled";
 129                 };
 130
 131                 dmac_bus_s: dma-controller@ffb20000 {
 132                         compatible = "arm,pl330", "arm,primecell";
 133                         broken-no-flushp;
 134                         reg = <0xffb20000 0x4000>;
 135                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 136                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 137                         #dma-cells = <1>;
 138                         clocks = <&cru ACLK_DMAC1>;
 139                         clock-names = "apb_pclk";
 140                 };
 141         };
 142
 143         xin24m: oscillator {
 144                 compatible = "fixed-clock";
 145                 clock-frequency = <24000000>;
 146                 clock-output-names = "xin24m";
 147                 #clock-cells = <0>;
 148         };
 149
 150         timer {
 151                 arm,use-physical-timer;
 152                 compatible = "arm,armv7-timer";
 153                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 155                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 156                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 157                 clock-frequency = <24000000>;
 158                 always-on;
 159         };
 160
 161         display-subsystem {
 162                 compatible = "rockchip,display-subsystem";
 163                 ports = <&vopl_out>, <&vopb_out>;
 164         };
 165
 166         sdmmc: dwmmc@ff0c0000 {
 167                 compatible = "rockchip,rk3288-dw-mshc";
 168                 max-frequency = <150000000>;
 169                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 170                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 171                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 172                 fifo-depth = <0x100>;
 173                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 174                 reg = <0xff0c0000 0x4000>;
 175                 status = "disabled";
 176         };
 177
 178         sdio0: dwmmc@ff0d0000 {
 179                 compatible = "rockchip,rk3288-dw-mshc";
 180                 max-frequency = <150000000>;
 181                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 182                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 183                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 184                 fifo-depth = <0x100>;
 185                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 186                 reg = <0xff0d0000 0x4000>;
 187                 status = "disabled";
 188         };
 189
 190         sdio1: dwmmc@ff0e0000 {
 191                 compatible = "rockchip,rk3288-dw-mshc";
 192                 max-frequency = <150000000>;
 193                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 194                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 195                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 196                 fifo-depth = <0x100>;
 197                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 198                 reg = <0xff0e0000 0x4000>;
 199                 status = "disabled";
 200         };
 201
 202         emmc: dwmmc@ff0f0000 {
 203                 compatible = "rockchip,rk3288-dw-mshc";
 204                 max-frequency = <150000000>;
 205                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 206                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 207                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 208                 fifo-depth = <0x100>;
 209                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 210                 reg = <0xff0f0000 0x4000>;
 211                 status = "disabled";
 212         };
 213
 214         saradc: saradc@ff100000 {
 215                 compatible = "rockchip,saradc";
 216                 reg = <0xff100000 0x100>;
 217                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 218                 #io-channel-cells = <1>;
 219                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 220                 clock-names = "saradc", "apb_pclk";
 221                 status = "disabled";
 222         };
 223
 224         spi0: spi@ff110000 {
 225                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 226                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 227                 clock-names = "spiclk", "apb_pclk";
 228                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 229                 dma-names = "tx", "rx";
 230                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 231                 pinctrl-names = "default";
 232                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 233                 reg = <0xff110000 0x1000>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 status = "disabled";
 237         };
 238
 239         spi1: spi@ff120000 {
 240                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 241                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 242                 clock-names = "spiclk", "apb_pclk";
 243                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 244                 dma-names = "tx", "rx";
 245                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 246                 pinctrl-names = "default";
 247                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 248                 reg = <0xff120000 0x1000>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 status = "disabled";
 252         };
 253
 254         spi2: spi@ff130000 {
 255                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 256                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 257                 clock-names = "spiclk", "apb_pclk";
 258                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 259                 dma-names = "tx", "rx";
 260                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 263                 reg = <0xff130000 0x1000>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 status = "disabled";
 267         };
 268
 269         i2c1: i2c@ff140000 {
 270                 compatible = "rockchip,rk3288-i2c";
 271                 reg = <0xff140000 0x1000>;
 272                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 clock-names = "i2c";
 276                 clocks = <&cru PCLK_I2C1>;
 277                 pinctrl-names = "default";
 278                 pinctrl-0 = <&i2c1_xfer>;
 279                 status = "disabled";
 280         };
 281
 282         i2c3: i2c@ff150000 {
 283                 compatible = "rockchip,rk3288-i2c";
 284                 reg = <0xff150000 0x1000>;
 285                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 clock-names = "i2c";
 289                 clocks = <&cru PCLK_I2C3>;
 290                 pinctrl-names = "default";
 291                 pinctrl-0 = <&i2c3_xfer>;
 292                 status = "disabled";
 293         };
 294
 295         i2c4: i2c@ff160000 {
 296                 compatible = "rockchip,rk3288-i2c";
 297                 reg = <0xff160000 0x1000>;
 298                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 clock-names = "i2c";
 302                 clocks = <&cru PCLK_I2C4>;
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&i2c4_xfer>;
 305                 status = "disabled";
 306         };
 307
 308         i2c5: i2c@ff170000 {
 309                 compatible = "rockchip,rk3288-i2c";
 310                 reg = <0xff170000 0x1000>;
 311                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 312                 #address-cells = <1>;
 313                 #size-cells = <0>;
 314                 clock-names = "i2c";
 315                 clocks = <&cru PCLK_I2C5>;
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&i2c5_xfer>;
 318                 status = "disabled";
 319         };
 320         uart0: serial@ff180000 {
 321                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 322                 reg = <0xff180000 0x100>;
 323                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 324                 reg-shift = <2>;
 325                 reg-io-width = <4>;
 326                 clock-frequency = <24000000>;
 327                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 328                 clock-names = "baudclk", "apb_pclk";
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&uart0_xfer>;
 331                 status = "disabled";
 332         };
 333
 334         uart1: serial@ff190000 {
 335                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 336                 reg = <0xff190000 0x100>;
 337                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 338                 reg-shift = <2>;
 339                 reg-io-width = <4>;
 340                 clock-frequency = <24000000>;
 341                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 342                 clock-names = "baudclk", "apb_pclk";
 343                 pinctrl-names = "default";
 344                 pinctrl-0 = <&uart1_xfer>;
 345                 status = "disabled";
 346         };
 347
 348         uart2: serial@ff690000 {
 349                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 350                 reg = <0xff690000 0x100>;
 351                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 352                 reg-shift = <2>;
 353                 reg-io-width = <4>;
 354                 clock-frequency = <24000000>;
 355                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 356                 clock-names = "baudclk", "apb_pclk";
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&uart2_xfer>;
 359                 status = "disabled";
 360         };
 361         uart3: serial@ff1b0000 {
 362                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 363                 reg = <0xff1b0000 0x100>;
 364                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 365                 reg-shift = <2>;
 366                 reg-io-width = <4>;
 367                 clock-frequency = <24000000>;
 368                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 369                 clock-names = "baudclk", "apb_pclk";
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&uart3_xfer>;
 372                 status = "disabled";
 373         };
 374
 375         uart4: serial@ff1c0000 {
 376                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 377                 reg = <0xff1c0000 0x100>;
 378                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 379                 reg-shift = <2>;
 380                 reg-io-width = <4>;
 381                 clock-frequency = <24000000>;
 382                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 383                 clock-names = "baudclk", "apb_pclk";
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&uart4_xfer>;
 386                 status = "disabled";
 387         };
 388         thermal: thermal-zones {
 389                 #include "rk3288-thermal.dtsi"
 390         };
 391
 392         tsadc: tsadc@ff280000 {
 393                 compatible = "rockchip,rk3288-tsadc";
 394                 reg = <0xff280000 0x100>;
 395                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 397                 clock-names = "tsadc", "apb_pclk";
 398                 resets = <&cru SRST_TSADC>;
 399                 reset-names = "tsadc-apb";
 400                 pinctrl-names = "otp_out";
 401                 pinctrl-0 = <&otp_out>;
 402                 #thermal-sensor-cells = <1>;
 403                 hw-shut-temp = <125000>;
 404                 status = "disabled";
 405         };
 406
 407         gmac: ethernet@ff290000 {
 408                 compatible = "rockchip,rk3288-gmac";
 409                 reg = <0xff290000 0x10000>;
 410                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 411                 interrupt-names = "macirq";
 412                 rockchip,grf = <&grf>;
 413                 clocks = <&cru SCLK_MAC>,
 414                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 415                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 416                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 417                 clock-names = "stmmaceth",
 418                         "mac_clk_rx", "mac_clk_tx",
 419                         "clk_mac_ref", "clk_mac_refout",
 420                         "aclk_mac", "pclk_mac";
 421         };
 422
 423         usb_host0_ehci: usb@ff500000 {
 424                 compatible = "generic-ehci";
 425                 reg = <0xff500000 0x100>;
 426                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 427                 clocks = <&cru HCLK_USBHOST0>;
 428                 clock-names = "usbhost";
 429                 phys = <&usbphy1>;
 430                 phy-names = "usb";
 431                 status = "disabled";
 432         };
 433
 434         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 435
 436         usb_host1: usb@ff540000 {
 437                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 438                                 "snps,dwc2";
 439                 reg = <0xff540000 0x40000>;
 440                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 441                 clocks = <&cru HCLK_USBHOST1>;
 442                 clock-names = "otg";
 443                 phys = <&usbphy2>;
 444                 phy-names = "usb2-phy";
 445                 status = "disabled";
 446         };
 447
 448         usb_otg: usb@ff580000 {
 449                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 450                                 "snps,dwc2";
 451                 reg = <0xff580000 0x40000>;
 452                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&cru HCLK_OTG0>;
 454                 clock-names = "otg";
 455                 dr_mode = "otg";
 456                 phys = <&usbphy0>;
 457                 phy-names = "usb2-phy";
 458                 status = "disabled";
 459         };
 460
 461         usb_hsic: usb@ff5c0000 {
 462                 compatible = "generic-ehci";
 463                 reg = <0xff5c0000 0x100>;
 464                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 465                 clocks = <&cru HCLK_HSIC>;
 466                 clock-names = "usbhost";
 467                 status = "disabled";
 468         };
 469
 470         dmc: dmc@ff610000 {
 471                 u-boot,dm-pre-reloc;
 472                 compatible = "rockchip,rk3288-dmc", "syscon";
 473                 rockchip,cru = <&cru>;
 474                 rockchip,grf = <&grf>;
 475                 rockchip,pmu = <&pmu>;
 476                 rockchip,sgrf = <&sgrf>;
 477                 rockchip,noc = <&noc>;
 478                 reg = <0xff610000 0x3fc
 479                        0xff620000 0x294
 480                        0xff630000 0x3fc
 481                        0xff640000 0x294>;
 482                 rockchip,sram = <&ddr_sram>;
 483                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 484                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 485                          <&cru ARMCLK>;
 486                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 487                               "pclk_ddrupctl1", "pclk_publ1",
 488                               "arm_clk";
 489         };
 490
 491         i2c0: i2c@ff650000 {
 492                 compatible = "rockchip,rk3288-i2c";
 493                 reg = <0xff650000 0x1000>;
 494                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 495                 #address-cells = <1>;
 496                 #size-cells = <0>;
 497                 clock-names = "i2c";
 498                 clocks = <&cru PCLK_I2C0>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&i2c0_xfer>;
 501                 status = "disabled";
 502         };
 503
 504         i2c2: i2c@ff660000 {
 505                 compatible = "rockchip,rk3288-i2c";
 506                 reg = <0xff660000 0x1000>;
 507                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510                 clock-names = "i2c";
 511                 clocks = <&cru PCLK_I2C2>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&i2c2_xfer>;
 514                 status = "disabled";
 515         };
 516
 517         pwm0: pwm@ff680000 {
 518                 compatible = "rockchip,rk3288-pwm";
 519                 reg = <0xff680000 0x10>;
 520                 #pwm-cells = <3>;
 521                 pinctrl-names = "default";
 522                 pinctrl-0 = <&pwm0_pin>;
 523                 clocks = <&cru PCLK_PWM>;
 524                 clock-names = "pwm";
 525                 rockchip,grf = <&grf>;
 526                 status = "disabled";
 527         };
 528
 529         pwm1: pwm@ff680010 {
 530                 compatible = "rockchip,rk3288-pwm";
 531                 reg = <0xff680010 0x10>;
 532                 #pwm-cells = <3>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&pwm1_pin>;
 535                 clocks = <&cru PCLK_PWM>;
 536                 clock-names = "pwm";
 537                 rockchip,grf = <&grf>;
 538                 status = "disabled";
 539         };
 540
 541         pwm2: pwm@ff680020 {
 542                 compatible = "rockchip,rk3288-pwm";
 543                 reg = <0xff680020 0x10>;
 544                 #pwm-cells = <3>;
 545                 pinctrl-names = "default";
 546                 pinctrl-0 = <&pwm2_pin>;
 547                 clocks = <&cru PCLK_PWM>;
 548                 clock-names = "pwm";
 549                 rockchip,grf = <&grf>;
 550                 status = "disabled";
 551         };
 552
 553         pwm3: pwm@ff680030 {
 554                 compatible = "rockchip,rk3288-pwm";
 555                 reg = <0xff680030 0x10>;
 556                 #pwm-cells = <2>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&pwm3_pin>;
 559                 clocks = <&cru PCLK_PWM>;
 560                 clock-names = "pwm";
 561                 rockchip,grf = <&grf>;
 562                 status = "disabled";
 563         };
 564
 565         bus_intmem@ff700000 {
 566                 compatible = "mmio-sram";
 567                 reg = <0xff700000 0x18000>;
 568                 #address-cells = <1>;
 569                 #size-cells = <1>;
 570                 ranges = <0 0xff700000 0x18000>;
 571                 smp-sram@0 {
 572                         compatible = "rockchip,rk3066-smp-sram";
 573                         reg = <0x00 0x10>;
 574                 };
 575                 ddr_sram: ddr-sram@1000 {
 576                         compatible = "rockchip,rk3288-ddr-sram";
 577                         reg = <0x1000 0x4000>;
 578                 };
 579         };
 580
 581         sram@ff720000 {
 582                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 583                 reg = <0xff720000 0x1000>;
 584         };
 585
 586         pmu: power-management@ff730000 {
 587                 u-boot,dm-pre-reloc;
 588                 compatible = "rockchip,rk3288-pmu", "syscon";
 589                 reg = <0xff730000 0x100>;
 590         };
 591
 592         sgrf: syscon@ff740000 {
 593                 u-boot,dm-pre-reloc;
 594                 compatible = "rockchip,rk3288-sgrf", "syscon";
 595                 reg = <0xff740000 0x1000>;
 596         };
 597
 598         cru: clock-controller@ff760000 {
 599                 compatible = "rockchip,rk3288-cru";
 600                 reg = <0xff760000 0x1000>;
 601                 rockchip,grf = <&grf>;
 602                 u-boot,dm-pre-reloc;
 603                 #clock-cells = <1>;
 604                 #reset-cells = <1>;
 605                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 606                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 607                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 608                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 609                                   <&cru PCLK_PERI>;
 610                 assigned-clock-rates = <594000000>, <400000000>,
 611                                        <500000000>, <300000000>,
 612                                        <150000000>, <75000000>,
 613                                        <300000000>, <150000000>,
 614                                        <75000000>;
 615         };
 616
 617         grf: syscon@ff770000 {
 618                 u-boot,dm-pre-reloc;
 619                 compatible = "rockchip,rk3288-grf", "syscon";
 620                 reg = <0xff770000 0x1000>;
 621         };
 622
 623         wdt: watchdog@ff800000 {
 624                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 625                 reg = <0xff800000 0x100>;
 626                 clocks = <&cru PCLK_WDT>;
 627                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 628                 status = "disabled";
 629         };
 630
 631         spdif: sound@ff88b0000 {
 632                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 633                 reg = <0xff8b0000 0x10000>;
 634                 #sound-dai-cells = <0>;
 635                 clock-names = "hclk", "mclk";
 636                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 637                 dmas = <&dmac_bus_s 3>;
 638                 dma-names = "tx";
 639                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 640                 pinctrl-names = "default";
 641                 pinctrl-0 = <&spdif_tx>;
 642                 rockchip,grf = <&grf>;
 643                 status = "disabled";
 644         };
 645
 646         i2s: i2s@ff890000 {
 647                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 648                 reg = <0xff890000 0x10000>;
 649                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 650                 #address-cells = <1>;
 651                 #size-cells = <0>;
 652                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 653                 dma-names = "tx", "rx";
 654                 clock-names = "i2s_hclk", "i2s_clk";
 655                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&i2s0_bus>;
 658                 status = "disabled";
 659         };
 660
 661         vopb: vop@ff930000 {
 662                 u-boot,dm-pre-reloc;
 663                 compatible = "rockchip,rk3288-vop";
 664                 reg = <0xff930000 0x19c>;
 665                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 666                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 667                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 668                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 669                 reset-names = "axi", "ahb", "dclk";
 670                 iommus = <&vopb_mmu>;
 671                 power-domains = <&power RK3288_PD_VIO>;
 672                 status = "disabled";
 673                 vopb_out: port {
 674                         #address-cells = <1>;
 675                         #size-cells = <0>;
 676                         vopb_out_edp: endpoint@0 {
 677                                 reg = <0>;
 678                                 remote-endpoint = <&edp_in_vopb>;
 679                         };
 680                         vopb_out_hdmi: endpoint@1 {
 681                                 reg = <1>;
 682                                 remote-endpoint = <&hdmi_in_vopb>;
 683                         };
 684                         vopb_out_lvds: endpoint@2 {
 685                                 reg = <2>;
 686                                 remote-endpoint = <&lvds_in_vopb>;
 687                         };
 688                         vopb_out_mipi: endpoint@3 {
 689                                 reg = <3>;
 690                                 remote-endpoint = <&mipi_in_vopb>;
 691                         };
 692
 693                 };
 694         };
 695
 696         vopb_mmu: iommu@ff930300 {
 697                 compatible = "rockchip,iommu";
 698                 reg = <0xff930300 0x100>;
 699                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 700                 interrupt-names = "vopb_mmu";
 701                 power-domains = <&power RK3288_PD_VIO>;
 702                 #iommu-cells = <0>;
 703                 status = "disabled";
 704         };
 705
 706         vopl: vop@ff940000 {
 707                 compatible = "rockchip,rk3288-vop";
 708                 reg = <0xff940000 0x19c>;
 709                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 710                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 711                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 712                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 713                 reset-names = "axi", "ahb", "dclk";
 714                 iommus = <&vopl_mmu>;
 715                 power-domains = <&power RK3288_PD_VIO>;
 716                 status = "disabled";
 717                 u-boot,dm-pre-reloc;
 718                 vopl_out: port {
 719                         #address-cells = <1>;
 720                         #size-cells = <0>;
 721                         vopl_out_edp: endpoint@0 {
 722                                 reg = <0>;
 723                                 remote-endpoint = <&edp_in_vopl>;
 724                         };
 725                         vopl_out_hdmi: endpoint@1 {
 726                                 reg = <1>;
 727                                 remote-endpoint = <&hdmi_in_vopl>;
 728                         };
 729                         vopl_out_lvds: endpoint@2 {
 730                                 reg = <2>;
 731                                 remote-endpoint = <&lvds_in_vopl>;
 732                         };
 733                         vopl_out_mipi: endpoint@3 {
 734                                 reg = <3>;
 735                                 remote-endpoint = <&mipi_in_vopl>;
 736                         };
 737
 738                 };
 739         };
 740
 741         vopl_mmu: iommu@ff940300 {
 742                 compatible = "rockchip,iommu";
 743                 reg = <0xff940300 0x100>;
 744                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 745                 interrupt-names = "vopl_mmu";
 746                 power-domains = <&power RK3288_PD_VIO>;
 747                 #iommu-cells = <0>;
 748                 status = "disabled";
 749         };
 750
 751         edp: edp@ff970000 {
 752                 compatible = "rockchip,rk3288-edp";
 753                 reg = <0xff970000 0x4000>;
 754                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 755                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
 756                 rockchip,grf = <&grf>;
 757                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 758                 resets = <&cru 111>;
 759                 reset-names = "edp";
 760                 power-domains = <&power RK3288_PD_VIO>;
 761                 status = "disabled";
 762                 ports {
 763                         edp_in: port {
 764                                 #address-cells = <1>;
 765                                 #size-cells = <0>;
 766                                 edp_in_vopb: endpoint@0 {
 767                                         reg = <0>;
 768                                         remote-endpoint = <&vopb_out_edp>;
 769                                 };
 770                                 edp_in_vopl: endpoint@1 {
 771                                         reg = <1>;
 772                                         remote-endpoint = <&vopl_out_edp>;
 773                                 };
 774                         };
 775                 };
 776         };
 777
 778         hdmi: hdmi@ff980000 {
 779                 compatible = "rockchip,rk3288-dw-hdmi";
 780                 reg = <0xff980000 0x20000>;
 781                 reg-io-width = <4>;
 782                 ddc-i2c-bus = <&i2c5>;
 783                 rockchip,grf = <&grf>;
 784                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 785                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 786                 clock-names = "iahb", "isfr";
 787                 status = "disabled";
 788                 ports {
 789                         hdmi_in: port {
 790                                 #address-cells = <1>;
 791                                 #size-cells = <0>;
 792                                 hdmi_in_vopb: endpoint@0 {
 793                                         reg = <0>;
 794                                         remote-endpoint = <&vopb_out_hdmi>;
 795                                 };
 796                                 hdmi_in_vopl: endpoint@1 {
 797                                         reg = <1>;
 798                                         remote-endpoint = <&vopl_out_hdmi>;
 799                                 };
 800                         };
 801                 };
 802         };
 803
 804         lvds: lvds@ff96c000 {
 805                 compatible = "rockchip,rk3288-lvds";
 806                 reg = <0xff96c000 0x4000>;
 807                 clocks = <&cru PCLK_LVDS_PHY>;
 808                 clock-names = "pclk_lvds";
 809                 pinctrl-names = "default";
 810                 pinctrl-0 = <&lcdc0_ctl>;
 811                 rockchip,grf = <&grf>;
 812                 status = "disabled";
 813                 ports {
 814                         #address-cells = <1>;
 815                         #size-cells = <0>;
 816                         lvds_in: port@0 {
 817                                 reg = <0>;
 818                                 #address-cells = <1>;
 819                                 #size-cells = <0>;
 820                                 lvds_in_vopb: endpoint@0 {
 821                                         reg = <0>;
 822                                         remote-endpoint = <&vopb_out_lvds>;
 823                                 };
 824                                 lvds_in_vopl: endpoint@1 {
 825                                         reg = <1>;
 826                                         remote-endpoint = <&vopl_out_lvds>;
 827                                 };
 828                         };
 829                 };
 830         };
 831
 832         mipi_dsi0: mipi@ff960000 {
 833                 compatible = "rockchip,rk3288_mipi_dsi";
 834                 reg = <0xff960000 0x4000>;
 835                 clocks = <&cru PCLK_MIPI_DSI0>;
 836                 clock-names = "pclk_mipi";
 837                 /*pinctrl-names = "default";
 838                 pinctrl-0 = <&lcdc0_ctl>;*/
 839                 rockchip,grf = <&grf>;
 840                 #address-cells = <1>;
 841                 #size-cells = <0>;
 842                 status = "disabled";
 843                 ports {
 844                         reg = <1>;
 845                         mipi_in: port {
 846                                 #address-cells = <1>;
 847                                 #size-cells = <0>;
 848                                 mipi_in_vopb: endpoint@0 {
 849                                         reg = <0>;
 850                                         remote-endpoint = <&vopb_out_mipi>;
 851                                 };
 852                                 mipi_in_vopl: endpoint@1 {
 853                                         reg = <1>;
 854                                         remote-endpoint = <&vopl_out_mipi>;
 855                                 };
 856                         };
 857                 };
 858         };
 859
 860         hdmi_audio: hdmi_audio {
 861                 compatible = "rockchip,rk3288-hdmi-audio";
 862                 i2s-controller = <&i2s>;
 863                 status = "disable";
 864         };
 865
 866         vpu: video-codec@ff9a0000 {
 867                 compatible = "rockchip,rk3288-vpu";
 868                 reg = <0xff9a0000 0x800>;
 869                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 870                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 871                 interrupt-names = "vepu", "vdpu";
 872                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 873                 clock-names = "aclk_vcodec", "hclk_vcodec";
 874                 power-domains = <&power RK3288_PD_VIDEO>;
 875                 iommus = <&vpu_mmu>;
 876         };
 877
 878         vpu_mmu: iommu@ff9a0800 {
 879                 compatible = "rockchip,iommu";
 880                 reg = <0xff9a0800 0x100>;
 881                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 882                 interrupt-names = "vpu_mmu";
 883                 power-domains = <&power RK3288_PD_VIDEO>;
 884                 #iommu-cells = <0>;
 885         };
 886
 887         gpu: gpu@ffa30000 {
 888                 compatible = "arm,malit764",
 889                              "arm,malit76x",
 890                              "arm,malit7xx",
 891                              "arm,mali-midgard";
 892                 reg = <0xffa30000 0x10000>;
 893                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 894                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 895                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 896                 interrupt-names = "JOB", "MMU", "GPU";
 897                 clocks = <&cru ACLK_GPU>;
 898                 clock-names = "aclk_gpu";
 899                 operating-points = <
 900                         /* KHz uV */
 901                         100000 950000
 902                         200000 950000
 903                         300000 1000000
 904                         400000 1100000
 905                         /* 500000 1200000 - See crosbug.com/p/33857 */
 906                         600000 1250000
 907                 >;
 908                 power-domains = <&power RK3288_PD_GPU>;
 909                 status = "disabled";
 910         };
 911
 912         noc: syscon@ffac0000 {
 913                 u-boot,dm-pre-reloc;
 914                 compatible = "rockchip,rk3288-noc", "syscon";
 915                 reg = <0xffac0000 0x2000>;
 916         };
 917
 918         efuse: efuse@ffb40000 {
 919                 compatible = "rockchip,rk3288-efuse";
 920                 reg = <0xffb40000 0x10000>;
 921                 status = "disabled";
 922         };
 923
 924         gic: interrupt-controller@ffc01000 {
 925                 compatible = "arm,gic-400";
 926                 interrupt-controller;
 927                 #interrupt-cells = <3>;
 928                 #address-cells = <0>;
 929
 930                 reg = <0xffc01000 0x1000>,
 931                       <0xffc02000 0x1000>,
 932                       <0xffc04000 0x2000>,
 933                       <0xffc06000 0x2000>;
 934                 interrupts = <GIC_PPI 9 0xf04>;
 935         };
 936
 937         cpuidle: cpuidle {
 938                 compatible = "rockchip,rk3288-cpuidle";
 939         };
 940
 941         usbphy: phy {
 942                 compatible = "rockchip,rk3288-usb-phy";
 943                 rockchip,grf = <&grf>;
 944                 #address-cells = <1>;
 945                 #size-cells = <0>;
 946                 status = "disabled";
 947
 948                 usbphy0: usb-phy0 {
 949                         #phy-cells = <0>;
 950                         reg = <0x320>;
 951                         clocks = <&cru SCLK_OTGPHY0>;
 952                         clock-names = "phyclk";
 953                 };
 954
 955                 usbphy1: usb-phy1 {
 956                         #phy-cells = <0>;
 957                         reg = <0x334>;
 958                         clocks = <&cru SCLK_OTGPHY1>;
 959                         clock-names = "phyclk";
 960                 };
 961
 962                 usbphy2: usb-phy2 {
 963                         #phy-cells = <0>;
 964                         reg = <0x348>;
 965                         clocks = <&cru SCLK_OTGPHY2>;
 966                         clock-names = "phyclk";
 967                 };
 968         };
 969
 970         pinctrl: pinctrl {
 971                 compatible = "rockchip,rk3288-pinctrl";
 972                 rockchip,grf = <&grf>;
 973                 rockchip,pmu = <&pmu>;
 974                 #address-cells = <1>;
 975                 #size-cells = <1>;
 976                 ranges;
 977
 978                 gpio0: gpio0@ff750000 {
 979                         compatible = "rockchip,gpio-bank";
 980                         reg =   <0xff750000 0x100>;
 981                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 982                         clocks = <&cru PCLK_GPIO0>;
 983
 984                         gpio-controller;
 985                         #gpio-cells = <2>;
 986
 987                         interrupt-controller;
 988                         #interrupt-cells = <2>;
 989                 };
 990
 991                 gpio1: gpio1@ff780000 {
 992                         compatible = "rockchip,gpio-bank";
 993                         reg = <0xff780000 0x100>;
 994                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 995                         clocks = <&cru PCLK_GPIO1>;
 996
 997                         gpio-controller;
 998                         #gpio-cells = <2>;
 999
1000                         interrupt-controller;
1001                         #interrupt-cells = <2>;
1002                 };
1003
1004                 gpio2: gpio2@ff790000 {
1005                         compatible = "rockchip,gpio-bank";
1006                         reg = <0xff790000 0x100>;
1007                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1008                         clocks = <&cru PCLK_GPIO2>;
1009
1010                         gpio-controller;
1011                         #gpio-cells = <2>;
1012
1013                         interrupt-controller;
1014                         #interrupt-cells = <2>;
1015                 };
1016
1017                 gpio3: gpio3@ff7a0000 {
1018                         compatible = "rockchip,gpio-bank";
1019                         reg = <0xff7a0000 0x100>;
1020                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1021                         clocks = <&cru PCLK_GPIO3>;
1022
1023                         gpio-controller;
1024                         #gpio-cells = <2>;
1025
1026                         interrupt-controller;
1027                         #interrupt-cells = <2>;
1028                 };
1029
1030                 gpio4: gpio4@ff7b0000 {
1031                         compatible = "rockchip,gpio-bank";
1032                         reg = <0xff7b0000 0x100>;
1033                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1034                         clocks = <&cru PCLK_GPIO4>;
1035
1036                         gpio-controller;
1037                         #gpio-cells = <2>;
1038
1039                         interrupt-controller;
1040                         #interrupt-cells = <2>;
1041                 };
1042
1043                 gpio5: gpio5@ff7c0000 {
1044                         compatible = "rockchip,gpio-bank";
1045                         reg = <0xff7c0000 0x100>;
1046                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1047                         clocks = <&cru PCLK_GPIO5>;
1048
1049                         gpio-controller;
1050                         #gpio-cells = <2>;
1051
1052                         interrupt-controller;
1053                         #interrupt-cells = <2>;
1054                 };
1055
1056                 gpio6: gpio6@ff7d0000 {
1057                         compatible = "rockchip,gpio-bank";
1058                         reg = <0xff7d0000 0x100>;
1059                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1060                         clocks = <&cru PCLK_GPIO6>;
1061
1062                         gpio-controller;
1063                         #gpio-cells = <2>;
1064
1065                         interrupt-controller;
1066                         #interrupt-cells = <2>;
1067                 };
1068
1069                 gpio7: gpio7@ff7e0000 {
1070                         compatible = "rockchip,gpio-bank";
1071                         reg = <0xff7e0000 0x100>;
1072                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1073                         clocks = <&cru PCLK_GPIO7>;
1074
1075                         gpio-controller;
1076                         #gpio-cells = <2>;
1077
1078                         interrupt-controller;
1079                         #interrupt-cells = <2>;
1080                 };
1081
1082                 gpio8: gpio8@ff7f0000 {
1083                         compatible = "rockchip,gpio-bank";
1084                         reg = <0xff7f0000 0x100>;
1085                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1086                         clocks = <&cru PCLK_GPIO8>;
1087
1088                         gpio-controller;
1089                         #gpio-cells = <2>;
1090
1091                         interrupt-controller;
1092                         #interrupt-cells = <2>;
1093                 };
1094
1095                 pcfg_pull_up: pcfg-pull-up {
1096                         bias-pull-up;
1097                 };
1098
1099                 pcfg_pull_down: pcfg-pull-down {
1100                         bias-pull-down;
1101                 };
1102
1103                 pcfg_pull_none: pcfg-pull-none {
1104                         bias-disable;
1105                 };
1106
1107                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1108                         bias-disable;
1109                         drive-strength = <12>;
1110                 };
1111
1112                 sleep {
1113                         global_pwroff: global-pwroff {
1114                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1115                         };
1116
1117                         ddrio_pwroff: ddrio-pwroff {
1118                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1119                         };
1120
1121                         ddr0_retention: ddr0-retention {
1122                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1123                         };
1124
1125                         ddr1_retention: ddr1-retention {
1126                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1127                         };
1128                 };
1129
1130                 i2c0 {
1131                         i2c0_xfer: i2c0-xfer {
1132                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1133                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1134                         };
1135                 };
1136
1137                 i2c1 {
1138                         i2c1_xfer: i2c1-xfer {
1139                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1140                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1141                         };
1142                 };
1143
1144                 i2c2 {
1145                         i2c2_xfer: i2c2-xfer {
1146                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1147                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1148                         };
1149                 };
1150
1151                 i2c3 {
1152                         i2c3_xfer: i2c3-xfer {
1153                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1154                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1155                         };
1156                 };
1157
1158                 i2c4 {
1159                         i2c4_xfer: i2c4-xfer {
1160                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1161                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1162                         };
1163                 };
1164
1165                 i2c5 {
1166                         i2c5_xfer: i2c5-xfer {
1167                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1168                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1169                         };
1170                 };
1171
1172                 i2s0 {
1173                         i2s0_bus: i2s0-bus {
1174                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1175                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1176                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1177                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1178                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1179                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1180                         };
1181                 };
1182
1183                 lcdc0 {
1184                         lcdc0_ctl: lcdc0-ctl {
1185                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1186                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1187                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1188                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1189                         };
1190                 };
1191
1192                 sdmmc {
1193                         sdmmc_clk: sdmmc-clk {
1194                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1195                         };
1196
1197                         sdmmc_cmd: sdmmc-cmd {
1198                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1199                         };
1200
1201                         sdmmc_cd: sdmcc-cd {
1202                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1203                         };
1204
1205                         sdmmc_bus1: sdmmc-bus1 {
1206                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1207                         };
1208
1209                         sdmmc_bus4: sdmmc-bus4 {
1210                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1211                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1212                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1213                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1214                         };
1215                 };
1216
1217                 sdio0 {
1218                         sdio0_bus1: sdio0-bus1 {
1219                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1220                         };
1221
1222                         sdio0_bus4: sdio0-bus4 {
1223                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1224                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1225                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1226                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1227                         };
1228
1229                         sdio0_cmd: sdio0-cmd {
1230                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1231                         };
1232
1233                         sdio0_clk: sdio0-clk {
1234                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1235                         };
1236
1237                         sdio0_cd: sdio0-cd {
1238                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1239                         };
1240
1241                         sdio0_wp: sdio0-wp {
1242                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1243                         };
1244
1245                         sdio0_pwr: sdio0-pwr {
1246                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1247                         };
1248
1249                         sdio0_bkpwr: sdio0-bkpwr {
1250                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1251                         };
1252
1253                         sdio0_int: sdio0-int {
1254                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1255                         };
1256                 };
1257
1258                 sdio1 {
1259                         sdio1_bus1: sdio1-bus1 {
1260                                 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1261                         };
1262
1263                         sdio1_bus4: sdio1-bus4 {
1264                                 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1265                                                 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1266                                                 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1267                                                 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1268                         };
1269
1270                         sdio1_cd: sdio1-cd {
1271                                 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1272                         };
1273
1274                         sdio1_wp: sdio1-wp {
1275                                 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1276                         };
1277
1278                         sdio1_bkpwr: sdio1-bkpwr {
1279                                 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1280                         };
1281
1282                         sdio1_int: sdio1-int {
1283                                 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1284                         };
1285
1286                         sdio1_cmd: sdio1-cmd {
1287                                 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1288                         };
1289
1290                         sdio1_clk: sdio1-clk {
1291                                 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1292                         };
1293
1294                         sdio1_pwr: sdio1-pwr {
1295                                 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1296                         };
1297                 };
1298
1299                 emmc {
1300                         emmc_clk: emmc-clk {
1301                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1302                         };
1303
1304                         emmc_cmd: emmc-cmd {
1305                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1306                         };
1307
1308                         emmc_pwr: emmc-pwr {
1309                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1310                         };
1311
1312                         emmc_bus1: emmc-bus1 {
1313                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1314                         };
1315
1316                         emmc_bus4: emmc-bus4 {
1317                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1318                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1319                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1320                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1321                         };
1322
1323                         emmc_bus8: emmc-bus8 {
1324                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1325                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1326                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1327                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1328                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1329                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1330                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1331                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1332                         };
1333                 };
1334
1335                 spi0 {
1336                         spi0_clk: spi0-clk {
1337                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1338                         };
1339                         spi0_cs0: spi0-cs0 {
1340                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1341                         };
1342                         spi0_tx: spi0-tx {
1343                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1344                         };
1345                         spi0_rx: spi0-rx {
1346                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1347                         };
1348                         spi0_cs1: spi0-cs1 {
1349                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1350                         };
1351                 };
1352                 spi1 {
1353                         spi1_clk: spi1-clk {
1354                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1355                         };
1356                         spi1_cs0: spi1-cs0 {
1357                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1358                         };
1359                         spi1_rx: spi1-rx {
1360                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1361                         };
1362                         spi1_tx: spi1-tx {
1363                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1364                         };
1365                 };
1366
1367                 spi2 {
1368                         spi2_cs1: spi2-cs1 {
1369                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1370                         };
1371                         spi2_clk: spi2-clk {
1372                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1373                         };
1374                         spi2_cs0: spi2-cs0 {
1375                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1376                         };
1377                         spi2_rx: spi2-rx {
1378                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1379                         };
1380                         spi2_tx: spi2-tx {
1381                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1382                         };
1383                 };
1384
1385                 uart0 {
1386                         uart0_xfer: uart0-xfer {
1387                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1388                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1389                         };
1390
1391                         uart0_cts: uart0-cts {
1392                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1393                         };
1394
1395                         uart0_rts: uart0-rts {
1396                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1397                         };
1398                 };
1399
1400                 uart1 {
1401                         uart1_xfer: uart1-xfer {
1402                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1403                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1404                         };
1405
1406                         uart1_cts: uart1-cts {
1407                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1408                         };
1409
1410                         uart1_rts: uart1-rts {
1411                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1412                         };
1413                 };
1414
1415                 uart2 {
1416                         uart2_xfer: uart2-xfer {
1417                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1418                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1419                         };
1420                         /* no rts / cts for uart2 */
1421                 };
1422
1423                 uart3 {
1424                         uart3_xfer: uart3-xfer {
1425                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1426                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1427                         };
1428
1429                         uart3_cts: uart3-cts {
1430                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1431                         };
1432
1433                         uart3_rts: uart3-rts {
1434                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1435                         };
1436                 };
1437
1438                 uart4 {
1439                         uart4_xfer: uart4-xfer {
1440                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1441                                                 <5 13 3 &pcfg_pull_none>;
1442                         };
1443
1444                         uart4_cts: uart4-cts {
1445                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1446                         };
1447
1448                         uart4_rts: uart4-rts {
1449                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1450                         };
1451                 };
1452
1453                 tsadc {
1454                         otp_out: otp-out {
1455                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1456                         };
1457                 };
1458
1459                 pwm0 {
1460                         pwm0_pin: pwm0-pin {
1461                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1462                         };
1463                 };
1464
1465                 pwm1 {
1466                         pwm1_pin: pwm1-pin {
1467                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1468                         };
1469                 };
1470
1471                 pwm2 {
1472                         pwm2_pin: pwm2-pin {
1473                                 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1474                         };
1475                 };
1476
1477                 pwm3 {
1478                         pwm3_pin: pwm3-pin {
1479                                 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1480                         };
1481                 };
1482
1483                 gmac {
1484                         rgmii_pins: rgmii-pins {
1485                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1486                                                 <3 31 3 &pcfg_pull_none>,
1487                                                 <3 26 3 &pcfg_pull_none>,
1488                                                 <3 27 3 &pcfg_pull_none>,
1489                                                 <3 28 3 &pcfg_pull_none_12ma>,
1490                                                 <3 29 3 &pcfg_pull_none_12ma>,
1491                                                 <3 24 3 &pcfg_pull_none_12ma>,
1492                                                 <3 25 3 &pcfg_pull_none_12ma>,
1493                                                 <4 0 3 &pcfg_pull_none>,
1494                                                 <4 5 3 &pcfg_pull_none>,
1495                                                 <4 6 3 &pcfg_pull_none>,
1496                                                 <4 9 3 &pcfg_pull_none_12ma>,
1497                                                 <4 4 3 &pcfg_pull_none_12ma>,
1498                                                 <4 1 3 &pcfg_pull_none>,
1499                                                 <4 3 3 &pcfg_pull_none>;
1500                         };
1501
1502                         rmii_pins: rmii-pins {
1503                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1504                                                 <3 31 3 &pcfg_pull_none>,
1505                                                 <3 28 3 &pcfg_pull_none>,
1506                                                 <3 29 3 &pcfg_pull_none>,
1507                                                 <4 0 3 &pcfg_pull_none>,
1508                                                 <4 5 3 &pcfg_pull_none>,
1509                                                 <4 4 3 &pcfg_pull_none>,
1510                                                 <4 1 3 &pcfg_pull_none>,
1511                                                 <4 2 3 &pcfg_pull_none>,
1512                                                 <4 3 3 &pcfg_pull_none>;
1513                         };
1514                 };
1515
1516                 spdif {
1517                         spdif_tx: spdif-tx {
1518                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1519                         };
1520                 };
1521         };
1522
1523         power: power-controller {
1524                 compatible = "rockchip,rk3288-power-controller";
1525                 #power-domain-cells = <1>;
1526                 rockchip,pmu = <&pmu>;
1527                 #address-cells = <1>;
1528                 #size-cells = <0>;
1529
1530                 pd_gpu {
1531                         reg = <RK3288_PD_GPU>;
1532                         clocks = <&cru ACLK_GPU>;
1533                 };
1534
1535                 pd_hevc {
1536                         reg = <RK3288_PD_HEVC>;
1537                         clocks = <&cru ACLK_HEVC>,
1538                                  <&cru SCLK_HEVC_CABAC>,
1539                                  <&cru SCLK_HEVC_CORE>,
1540                                  <&cru HCLK_HEVC>;
1541                 };
1542
1543                 pd_vio {
1544                         reg = <RK3288_PD_VIO>;
1545                         clocks = <&cru ACLK_IEP>,
1546                                  <&cru ACLK_ISP>,
1547                                  <&cru ACLK_RGA>,
1548                                  <&cru ACLK_VIP>,
1549                                  <&cru ACLK_VOP0>,
1550                                  <&cru ACLK_VOP1>,
1551                                  <&cru DCLK_VOP0>,
1552                                  <&cru DCLK_VOP1>,
1553                                  <&cru HCLK_IEP>,
1554                                  <&cru HCLK_ISP>,
1555                                  <&cru HCLK_RGA>,
1556                                  <&cru HCLK_VIP>,
1557                                  <&cru HCLK_VOP0>,
1558                                  <&cru HCLK_VOP1>,
1559                                  <&cru PCLK_EDP_CTRL>,
1560                                  <&cru PCLK_HDMI_CTRL>,
1561                                  <&cru PCLK_LVDS_PHY>,
1562                                  <&cru PCLK_MIPI_CSI>,
1563                                  <&cru PCLK_MIPI_DSI0>,
1564                                  <&cru PCLK_MIPI_DSI1>,
1565                                  <&cru SCLK_EDP_24M>,
1566                                  <&cru SCLK_EDP>,
1567                                  <&cru SCLK_HDMI_CEC>,
1568                                  <&cru SCLK_HDMI_HDCP>,
1569                                  <&cru SCLK_ISP_JPE>,
1570                                  <&cru SCLK_ISP>,
1571                                  <&cru SCLK_RGA>;
1572                 };
1573
1574                 pd_video {
1575                         reg = <RK3288_PD_VIDEO>;
1576                         clocks = <&cru ACLK_VCODEC>,
1577                                  <&cru HCLK_VCODEC>;
1578                 };
1579         };
1580 };