arch/arm/dts/rk3288-veyron.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Google Veyron (and derivatives) board device tree source
   4  *
   5  * Copyright 2014 Google, Inc
   6  */
   7
   8 #include <dt-bindings/clock/rockchip,rk808.h>
   9 #include <dt-bindings/input/input.h>
  10 #include "rk3288.dtsi"
  11
  12 / {
  13         memory {
  14                 reg = <0x0 0x80000000>;
  15         };
  16
  17         chosen {
  18                 stdout-path = &uart2;
  19         };
  20
  21         config {
  22                 u-boot,dm-pre-reloc;
  23                 u-boot,boot0 = &spi_flash;
  24         };
  25
  26         firmware {
  27                 chromeos {
  28                         pinctrl-names = "default";
  29                         pinctrl-0 = <&fw_wp_ap>;
  30                         write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
  31                 };
  32         };
  33
  34         backlight: backlight {
  35                 compatible = "pwm-backlight";
  36                 brightness-levels = <
  37                           0   1   2   3   4   5   6   7
  38                           8   9  10  11  12  13  14  15
  39                          16  17  18  19  20  21  22  23
  40                          24  25  26  27  28  29  30  31
  41                          32  33  34  35  36  37  38  39
  42                          40  41  42  43  44  45  46  47
  43                          48  49  50  51  52  53  54  55
  44                          56  57  58  59  60  61  62  63
  45                          64  65  66  67  68  69  70  71
  46                          72  73  74  75  76  77  78  79
  47                          80  81  82  83  84  85  86  87
  48                          88  89  90  91  92  93  94  95
  49                          96  97  98  99 100 101 102 103
  50                         104 105 106 107 108 109 110 111
  51                         112 113 114 115 116 117 118 119
  52                         120 121 122 123 124 125 126 127
  53                         128 129 130 131 132 133 134 135
  54                         136 137 138 139 140 141 142 143
  55                         144 145 146 147 148 149 150 151
  56                         152 153 154 155 156 157 158 159
  57                         160 161 162 163 164 165 166 167
  58                         168 169 170 171 172 173 174 175
  59                         176 177 178 179 180 181 182 183
  60                         184 185 186 187 188 189 190 191
  61                         192 193 194 195 196 197 198 199
  62                         200 201 202 203 204 205 206 207
  63                         208 209 210 211 212 213 214 215
  64                         216 217 218 219 220 221 222 223
  65                         224 225 226 227 228 229 230 231
  66                         232 233 234 235 236 237 238 239
  67                         240 241 242 243 244 245 246 247
  68                         248 249 250 251 252 253 254 255>;
  69                 default-brightness-level = <128>;
  70                 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
  71                 backlight-boot-off;
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&bl_en>;
  74                 pwms = <&pwm0 0 1000000 0>;
  75         };
  76
  77         panel: panel {
  78                 compatible ="cnm,n116bgeea2","simple-panel";
  79                 status = "okay";
  80                 power-supply = <&vcc33_lcd>;
  81                 backlight = <&backlight>;
  82         };
  83
  84         gpio_keys: gpio-keys {
  85                 compatible = "gpio-keys";
  86
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pwr_key_h>;
  89                 power {
  90                         label = "Power";
  91                         gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
  92                         linux,code = <KEY_POWER>;
  93                         debounce-interval = <100>;
  94                         gpio-key,wakeup;
  95                 };
  96         };
  97
  98         gpio-restart {
  99                 compatible = "gpio-restart";
 100                 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
 101                 pinctrl-names = "default";
 102                 pinctrl-0 = <&ap_warm_reset_h>;
 103                 priority = /bits/ 8 <200>;
 104         };
 105
 106         emmc_pwrseq: emmc-pwrseq {
 107                 compatible = "mmc-pwrseq-emmc";
 108                 pinctrl-0 = <&emmc_reset>;
 109                 pinctrl-names = "default";
 110                 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
 111         };
 112
 113         sound {
 114                 compatible = "rockchip,rockchip-audio-max98090";
 115                 rockchip,model = "ROCKCHIP-I2S";
 116                 rockchip,i2s-controller = <&i2s>;
 117                 rockchip,audio-codec = <&max98090>;
 118                 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
 119                 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 120                 rockchip,headset-codec = <&headsetcodec>;
 121                 pinctrl-names = "default";
 122                 pinctrl-0 = <&mic_det>, <&hp_det>;
 123         };
 124
 125         vdd_logic: pwm-regulator {
 126                 compatible = "pwm-regulator";
 127                 pwms = <&pwm1 0 2000 0>;
 128
 129                 voltage-table = <1350000 0>,
 130                                 <1300000 10>,
 131                                 <1250000 20>,
 132                                 <1200000 31>,
 133                                 <1150000 41>,
 134                                 <1100000 52>,
 135                                 <1050000 62>,
 136                                 <1000000 72>,
 137                                 < 950000 83>;
 138
 139                 regulator-min-microvolt = <950000>;
 140                 regulator-max-microvolt = <1350000>;
 141                 regulator-name = "vdd_logic";
 142                 regulator-ramp-delay = <4000>;
 143         };
 144
 145         vcc33_sys: vcc33-sys {
 146                 compatible = "regulator-fixed";
 147                 regulator-name = "vcc33_sys";
 148                 regulator-always-on;
 149                 regulator-boot-on;
 150                 regulator-min-microvolt = <3300000>;
 151                 regulator-max-microvolt = <3300000>;
 152                 vin-supply = <&vccsys>;
 153         };
 154
 155         vcc_5v: vcc-5v {
 156                 compatible = "regulator-fixed";
 157                 regulator-name = "vcc_5v";
 158                 regulator-always-on;
 159                 regulator-boot-on;
 160                 regulator-min-microvolt = <5000000>;
 161                 regulator-max-microvolt = <5000000>;
 162         };
 163
 164         vcc50_hdmi: vcc50-hdmi {
 165                 compatible = "regulator-fixed";
 166                 regulator-name = "vcc50_hdmi";
 167                 regulator-always-on;
 168                 regulator-boot-on;
 169                 vin-supply = <&vcc_5v>;
 170         };
 171
 172         bt_regulator: bt-regulator {
 173                 /*
 174                  * On the module itself this is one of these (depending
 175                  * on the actual card pouplated):
 176                  * - BT_I2S_WS_BT_RFDISABLE_L
 177                  * - No connect
 178                  */
 179
 180                 compatible = "regulator-fixed";
 181                 enable-active-high;
 182                 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
 183                 pinctrl-names = "default";
 184                 pinctrl-0 = <&bt_enable_l>;
 185                 regulator-name = "bt_regulator";
 186         };
 187
 188         wifi_regulator: wifi-regulator {
 189                 /*
 190                  * On the module itself this is one of these (depending
 191                  * on the actual card populated):
 192                  * - SDIO_RESET_L_WL_REG_ON
 193                  * - PDN (power down when low)
 194                  */
 195
 196                 compatible = "regulator-fixed";
 197                 enable-active-high;
 198                 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
 199                 pinctrl-names = "default";
 200                 pinctrl-0 = <&wifi_enable_h>;
 201                 regulator-name = "wifi_regulator";
 202
 203                 /* Faux input supply.  See bt_regulator description. */
 204                 vin-supply = <&bt_regulator>;
 205         };
 206
 207         io-domains {
 208                 compatible = "rockchip,rk3288-io-voltage-domain";
 209                 rockchip,grf = <&grf>;
 210
 211                 audio-supply = <&vcc18_codec>;
 212                 bb-supply = <&vcc33_io>;
 213                 dvp-supply = <&vcc_18>;
 214                 flash0-supply = <&vcc18_flashio>;
 215                 gpio1830-supply = <&vcc33_io>;
 216                 gpio30-supply = <&vcc33_io>;
 217                 lcdc-supply = <&vcc33_lcd>;
 218                 sdcard-supply = <&vccio_sd>;
 219                 wifi-supply = <&vcc18_wl>;
 220         };
 221 };
 222
 223 &cpu0 {
 224         cpu0-supply = <&vdd_cpu>;
 225 };
 226
 227 &dmc {
 228         logic-supply = <&vdd_logic>;
 229         rockchip,odt-disable-freq = <333000000>;
 230         rockchip,dll-disable-freq = <333000000>;
 231         rockchip,sr-enable-freq = <333000000>;
 232         rockchip,pd-enable-freq = <666000000>;
 233         rockchip,auto-self-refresh-cnt = <0>;
 234         rockchip,auto-power-down-cnt = <64>;
 235         rockchip,ddr-speed-bin = <21>;
 236         rockchip,trcd = <10>;
 237         rockchip,trp = <10>;
 238         operating-points = <
 239                 /* KHz    uV */
 240                 200000 1050000
 241                 333000 1100000
 242                 533000 1150000
 243                 666000 1200000
 244         >;
 245 };
 246
 247 &efuse {
 248         status = "okay";
 249 };
 250
 251 &emmc {
 252         broken-cd;
 253         bus-width = <8>;
 254         cap-mmc-highspeed;
 255         mmc-hs200-1_8v;
 256         mmc-pwrseq = <&emmc_pwrseq>;
 257         disable-wp;
 258         non-removable;
 259         num-slots = <1>;
 260         pinctrl-names = "default";
 261         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
 262         status = "okay";
 263 };
 264
 265 &sdio0 {
 266         broken-cd;
 267         bus-width = <4>;
 268         cap-sd-highspeed;
 269         sd-uhs-sdr12;
 270         sd-uhs-sdr25;
 271         sd-uhs-sdr50;
 272         sd-uhs-sdr104;
 273         cap-sdio-irq;
 274         card-external-vcc-supply = <&wifi_regulator>;
 275         clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
 276                  <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
 277         clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
 278         keep-power-in-suspend;
 279         non-removable;
 280         num-slots = <1>;
 281         pinctrl-names = "default";
 282         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 283         status = "okay";
 284         vmmc-supply = <&vcc33_sys>;
 285         vqmmc-supply = <&vcc18_wl>;
 286 };
 287
 288 &sdmmc {
 289         bus-width = <4>;
 290         cap-mmc-highspeed;
 291         cap-sd-highspeed;
 292         sd-uhs-sdr12;
 293         sd-uhs-sdr25;
 294         sd-uhs-sdr50;
 295         sd-uhs-sdr104;
 296         card-detect-delay = <200>;
 297         cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
 298         num-slots = <1>;
 299         status = "okay";
 300         vmmc-supply = <&vcc33_sd>;
 301         vqmmc-supply = <&vccio_sd>;
 302 };
 303
 304 &spi2 {
 305         status = "okay";
 306         u-boot,dm-pre-reloc;
 307
 308         spi_flash: spiflash@0 {
 309                 u-boot,dm-pre-reloc;
 310                 compatible = "spidev", "jedec,spi-nor";
 311                 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
 312                 reg = <0>;
 313         };
 314 };
 315
 316 &i2c0 {
 317         status = "okay";
 318
 319         clock-frequency = <400000>;
 320         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 321         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 322         u-boot,dm-pre-reloc;
 323
 324         rk808: pmic@1b {
 325                 compatible = "rockchip,rk808";
 326                 clock-output-names = "xin32k", "wifibt_32kin";
 327                 interrupt-parent = <&gpio0>;
 328                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&pmic_int_l>;
 331                 reg = <0x1b>;
 332                 rockchip,system-power-controller;
 333                 wakeup-source;
 334                 #clock-cells = <1>;
 335                 u-boot,dm-pre-reloc;
 336
 337                 vcc1-supply = <&vcc33_sys>;
 338                 vcc2-supply = <&vcc33_sys>;
 339                 vcc3-supply = <&vcc33_sys>;
 340                 vcc4-supply = <&vcc33_sys>;
 341                 vcc6-supply = <&vcc_5v>;
 342                 vcc7-supply = <&vcc33_sys>;
 343                 vcc8-supply = <&vcc33_sys>;
 344                 vcc9-supply = <&vcc_5v>;
 345                 vcc10-supply = <&vcc33_sys>;
 346                 vcc11-supply = <&vcc_5v>;
 347                 vcc12-supply = <&vcc_18>;
 348
 349                 vddio-supply = <&vcc33_io>;
 350
 351                 regulators {
 352                         vdd_cpu: DCDC_REG1 {
 353                                 regulator-always-on;
 354                                 regulator-boot-on;
 355                                 regulator-min-microvolt = <750000>;
 356                                 regulator-max-microvolt = <1450000>;
 357                                 regulator-name = "vdd_arm";
 358                                 regulator-ramp-delay = <6001>;
 359                                 regulator-suspend-mem-disabled;
 360                         };
 361
 362                         vdd_gpu: DCDC_REG2 {
 363                                 regulator-always-on;
 364                                 regulator-boot-on;
 365                                 regulator-min-microvolt = <800000>;
 366                                 regulator-max-microvolt = <1250000>;
 367                                 regulator-name = "vdd_gpu";
 368                                 regulator-ramp-delay = <6001>;
 369                                 regulator-suspend-mem-disabled;
 370                         };
 371
 372                         vcc135_ddr: DCDC_REG3 {
 373                                 regulator-always-on;
 374                                 regulator-boot-on;
 375                                 regulator-name = "vcc135_ddr";
 376                                 regulator-suspend-mem-enabled;
 377                         };
 378
 379                         /*
 380                          * vcc_18 has several aliases.  (vcc18_flashio and
 381                          * vcc18_wl).  We'll add those aliases here just to
 382                          * make it easier to follow the schematic.  The signals
 383                          * are actually hooked together and only separated for
 384                          * power measurement purposes).
 385                          */
 386                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 387                                 regulator-always-on;
 388                                 regulator-boot-on;
 389                                 regulator-min-microvolt = <1800000>;
 390                                 regulator-max-microvolt = <1800000>;
 391                                 regulator-name = "vcc_18";
 392                                 regulator-suspend-mem-microvolt = <1800000>;
 393                         };
 394
 395                         /*
 396                          * Note that both vcc33_io and vcc33_pmuio are always
 397                          * powered together. To simplify the logic in the dts
 398                          * we just refer to vcc33_io every time something is
 399                          * powered from vcc33_pmuio. In fact, on later boards
 400                          * (such as danger) they're the same net.
 401                          */
 402                         vcc33_io: LDO_REG1 {
 403                                 regulator-always-on;
 404                                 regulator-boot-on;
 405                                 regulator-min-microvolt = <3300000>;
 406                                 regulator-max-microvolt = <3300000>;
 407                                 regulator-name = "vcc33_io";
 408                                 regulator-suspend-mem-microvolt = <3300000>;
 409                         };
 410
 411                         vdd_10: LDO_REG3 {
 412                                 regulator-always-on;
 413                                 regulator-boot-on;
 414                                 regulator-min-microvolt = <1000000>;
 415                                 regulator-max-microvolt = <1000000>;
 416                                 regulator-name = "vdd_10";
 417                                 regulator-suspend-mem-microvolt = <1000000>;
 418                         };
 419
 420                         vccio_sd: LDO_REG4 {
 421                                 regulator-min-microvolt = <1800000>;
 422                                 regulator-max-microvolt = <3300000>;
 423                                 regulator-name = "vccio_sd";
 424                                 regulator-suspend-mem-disabled;
 425                         };
 426
 427                         vcc33_sd: LDO_REG5 {
 428                                 regulator-min-microvolt = <3300000>;
 429                                 regulator-max-microvolt = <3300000>;
 430                                 regulator-name = "vcc33_sd";
 431                                 regulator-suspend-mem-disabled;
 432                         };
 433
 434                         vcc18_codec: LDO_REG6 {
 435                                 regulator-always-on;
 436                                 regulator-boot-on;
 437                                 regulator-min-microvolt = <1800000>;
 438                                 regulator-max-microvolt = <1800000>;
 439                                 regulator-name = "vcc18_codec";
 440                                 regulator-suspend-mem-disabled;
 441                         };
 442
 443                         vdd10_lcd_pwren_h: LDO_REG7 {
 444                                 regulator-always-on;
 445                                 regulator-boot-on;
 446                                 regulator-min-microvolt = <2500000>;
 447                                 regulator-max-microvolt = <2500000>;
 448                                 regulator-name = "vdd10_lcd_pwren_h";
 449                                 regulator-suspend-mem-disabled;
 450                         };
 451
 452                         vcc33_lcd: SWITCH_REG1 {
 453                                 regulator-always-on;
 454                                 regulator-boot-on;
 455                                 regulator-name = "vcc33_lcd";
 456                                 regulator-suspend-mem-disabled;
 457                         };
 458                 };
 459         };
 460 };
 461
 462 &i2c1 {
 463         status = "okay";
 464
 465         clock-frequency = <400000>;
 466         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 467         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 468
 469         tpm: tpm@20 {
 470                 compatible = "infineon,slb9645tt";
 471                 reg = <0x20>;
 472                 powered-while-suspended;
 473         };
 474 };
 475
 476 &i2c2 {
 477         status = "okay";
 478
 479         /* 100kHz since 4.7k resistors don't rise fast enough */
 480         clock-frequency = <100000>;
 481         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 482         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 483
 484         max98090: max98090@10 {
 485                 compatible = "maxim,max98090";
 486                 reg = <0x10>;
 487                 #sound-dai-cells = <0>;
 488                 interrupt-parent = <&gpio6>;
 489                 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&int_codec>;
 492         };
 493 };
 494
 495 &i2c3 {
 496         status = "okay";
 497
 498         clock-frequency = <400000>;
 499         i2c-scl-falling-time-ns = <50>;
 500         i2c-scl-rising-time-ns = <300>;
 501 };
 502
 503 &i2c4 {
 504         status = "okay";
 505
 506         clock-frequency = <400000>;
 507         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 508         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 509
 510         headsetcodec: ts3a227e@3b {
 511                 compatible = "ti,ts3a227e";
 512                 reg = <0x3b>;
 513                 interrupt-parent = <&gpio0>;
 514                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&ts3a227e_int_l>;
 517                 ti,micbias = <7>;               /* MICBIAS = 2.8V */
 518         };
 519 };
 520
 521 &i2c5 {
 522         status = "okay";
 523
 524         clock-frequency = <100000>;
 525         i2c-scl-falling-time-ns = <300>;
 526         i2c-scl-rising-time-ns = <1000>;
 527 };
 528
 529 &i2s {
 530         status = "okay";
 531         clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
 532         clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
 533 };
 534
 535 &wdt {
 536         status = "okay";
 537 };
 538
 539 &pwm0 {
 540         status = "okay";
 541 };
 542
 543 &pwm1 {
 544         status = "okay";
 545 };
 546
 547 &uart0 {
 548         status = "okay";
 549
 550         /* Pins don't include flow control by default; add that in */
 551         pinctrl-names = "default";
 552         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 553         /* We need to go faster than 24MHz, so adjust clock parents / rates */
 554         assigned-clocks = <&cru SCLK_UART0>;
 555         assigned-clock-rates = <48000000>;
 556 };
 557
 558 &uart1 {
 559         status = "okay";
 560 };
 561
 562 &uart2 {
 563         status = "okay";
 564         u-boot,dm-pre-reloc;
 565         reg-shift = <2>;
 566 };
 567
 568 &vopb {
 569         status = "okay";
 570 };
 571
 572 &vopb_mmu {
 573         status = "okay";
 574 };
 575
 576 &vopl {
 577         status = "okay";
 578 };
 579
 580 &vopl_mmu {
 581         status = "okay";
 582 };
 583
 584 &edp {
 585         status = "okay";
 586         rockchip,panel = <&panel>;
 587 };
 588
 589 &hdmi {
 590         status = "okay";
 591 };
 592
 593 &hdmi_audio {
 594         status = "okay";
 595 };
 596
 597 &gpu {
 598         status = "okay";
 599 };
 600
 601 &tsadc {
 602         tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 603         tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 604         status = "okay";
 605 };
 606
 607 &pinctrl {
 608         u-boot,dm-pre-reloc;
 609         pinctrl-names = "default", "sleep";
 610         pinctrl-0 = <
 611                 /* Common for sleep and wake, but no owners */
 612                 &ddr0_retention
 613                 &ddrio_pwroff
 614                 &global_pwroff
 615
 616                 /* Wake only */
 617                 &bt_dev_wake_awake
 618         >;
 619         pinctrl-1 = <
 620                 /* Common for sleep and wake, but no owners */
 621                 &ddr0_retention
 622                 &ddrio_pwroff
 623                 &global_pwroff
 624
 625                 /* Sleep only */
 626                 &bt_dev_wake_sleep
 627         >;
 628
 629         /* Add this for sdmmc pins to SD card */
 630         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 631                 drive-strength = <8>;
 632         };
 633
 634         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 635                 bias-pull-up;
 636                 drive-strength = <8>;
 637         };
 638
 639         pcfg_output_high: pcfg-output-high {
 640                 output-high;
 641         };
 642
 643         pcfg_output_low: pcfg-output-low {
 644                 output-low;
 645         };
 646
 647         backlight {
 648                 bl_en: bl-en {
 649                         rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
 650                 };
 651         };
 652
 653         buttons {
 654                 pwr_key_h: pwr-key-h {
 655                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
 656                 };
 657         };
 658
 659         codec {
 660                 hp_det: hp-det {
 661                         rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
 662                 };
 663                 int_codec: int-codec {
 664                         rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
 665                 };
 666                 mic_det: mic-det {
 667                         rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
 668                 };
 669         };
 670
 671         emmc {
 672                 emmc_reset: emmc-reset {
 673                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 674                 };
 675
 676                 /*
 677                  * We run eMMC at max speed; bump up drive strength.
 678                  * We also have external pulls, so disable the internal ones.
 679                  */
 680                 emmc_clk: emmc-clk {
 681                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 682                 };
 683
 684                 emmc_cmd: emmc-cmd {
 685                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 686                 };
 687
 688                 emmc_bus8: emmc-bus8 {
 689                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 690                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 691                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 692                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 693                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 694                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 695                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 696                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 697                 };
 698         };
 699
 700         headset {
 701                 ts3a227e_int_l: ts3a227e-int-l {
 702                         rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
 703                 };
 704         };
 705
 706         pmic {
 707                 pmic_int_l: pmic-int-l {
 708                         /*
 709                          * Causes jerry to hang when probing bus 0
 710                          * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 711                          */
 712                 };
 713         };
 714
 715         reboot {
 716                 ap_warm_reset_h: ap-warm-reset-h {
 717                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 718                 };
 719         };
 720
 721         sdio0 {
 722                 wifi_enable_h: wifienable-h {
 723                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 724                 };
 725
 726                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 727                 bt_enable_l: bt-enable-l {
 728                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 729                 };
 730
 731                 /*
 732                  * We run sdio0 at max speed; bump up drive strength.
 733                  * We also have external pulls, so disable the internal ones.
 734                  */
 735                 sdio0_bus4: sdio0-bus4 {
 736                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 737                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 738                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 739                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 740                 };
 741
 742                 sdio0_cmd: sdio0-cmd {
 743                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 744                 };
 745
 746                 sdio0_clk: sdio0-clk {
 747                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 748                 };
 749
 750                 /*
 751                  * These pins are only present on very new veyron boards; on
 752                  * older boards bt_dev_wake is simply always high.  Note that
 753                  * gpio4_26 is a NC on old veyron boards, so it doesn't hurt
 754                  * to map this pin everywhere
 755                  */
 756                 bt_dev_wake_sleep: bt-dev-wake-sleep {
 757                         rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
 758                 };
 759
 760                 bt_dev_wake_awake: bt-dev-wake-awake {
 761                         rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
 762                 };
 763         };
 764
 765         sdmmc {
 766                 /*
 767                  * We run sdmmc at max speed; bump up drive strength.
 768                  * We also have external pulls, so disable the internal ones.
 769                  */
 770                 sdmmc_bus4: sdmmc-bus4 {
 771                         rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 772                                         <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 773                                         <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 774                                         <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 775                 };
 776
 777                 sdmmc_clk: sdmmc-clk {
 778                         rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 779                 };
 780
 781                 sdmmc_cmd: sdmmc-cmd {
 782                         rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 783                 };
 784
 785                 /*
 786                  * Builtin CD line is hooked to ground to prevent JTAG at boot
 787                  * (and also to get the voltage rail correct).  Make we
 788                  * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
 789                  * think there's a card inserted
 790                  */
 791                 sdmmc_cd_disabled: sdmmc-cd-disabled {
 792                         rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
 793                 };
 794
 795                 /* This is where we actually hook up CD */
 796                 sdmmc_cd_gpio: sdmmc-cd-gpio {
 797                         rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
 798                 };
 799         };
 800
 801         tpm {
 802                 tpm_int_h: tpm-int-h {
 803                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 804                 };
 805         };
 806
 807         write-protect {
 808                 fw_wp_ap: fw-wp-ap {
 809                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 810                 };
 811         };
 812 };
 813
 814 &usbphy {
 815         status = "okay";
 816 };
 817
 818 &usb_host0_ehci {
 819         status = "okay";
 820         needs-reset-on-resume;
 821 };
 822
 823 &usb_host1 {
 824         status = "okay";
 825 };
 826
 827 &usb_otg {
 828         dr_mode = "host";
 829         status = "okay";
 830         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 831         assigned-clock-parents = <&cru SCLK_OTGPHY0>;
 832 };
 833
 834 &sdmmc {
 835         u-boot,dm-pre-reloc;
 836 };
 837
 838 &gpio3 {
 839         u-boot,dm-pre-reloc;
 840 };
 841
 842 &gpio8 {
 843         u-boot,dm-pre-reloc;
 844 };