1 // SPDX-License-Identifier: GPL-2.0
3 * Google Veyron (and derivatives) board device tree source
5 * Copyright 2014 Google, Inc
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
10 #include "rk3288.dtsi"
14 reg = <0x0 0x80000000>;
23 u-boot,boot0 = &spi_flash;
28 pinctrl-names = "default";
29 pinctrl-0 = <&fw_wp_ap>;
30 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
34 backlight: backlight {
35 compatible = "pwm-backlight";
39 16 17 18 19 20 21 22 23
40 24 25 26 27 28 29 30 31
41 32 33 34 35 36 37 38 39
42 40 41 42 43 44 45 46 47
43 48 49 50 51 52 53 54 55
44 56 57 58 59 60 61 62 63
45 64 65 66 67 68 69 70 71
46 72 73 74 75 76 77 78 79
47 80 81 82 83 84 85 86 87
48 88 89 90 91 92 93 94 95
49 96 97 98 99 100 101 102 103
50 104 105 106 107 108 109 110 111
51 112 113 114 115 116 117 118 119
52 120 121 122 123 124 125 126 127
53 128 129 130 131 132 133 134 135
54 136 137 138 139 140 141 142 143
55 144 145 146 147 148 149 150 151
56 152 153 154 155 156 157 158 159
57 160 161 162 163 164 165 166 167
58 168 169 170 171 172 173 174 175
59 176 177 178 179 180 181 182 183
60 184 185 186 187 188 189 190 191
61 192 193 194 195 196 197 198 199
62 200 201 202 203 204 205 206 207
63 208 209 210 211 212 213 214 215
64 216 217 218 219 220 221 222 223
65 224 225 226 227 228 229 230 231
66 232 233 234 235 236 237 238 239
67 240 241 242 243 244 245 246 247
68 248 249 250 251 252 253 254 255>;
69 default-brightness-level = <128>;
70 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
72 pinctrl-names = "default";
74 pwms = <&pwm0 0 1000000 0>;
78 compatible ="cnm,n116bgeea2","simple-panel";
80 power-supply = <&vcc33_lcd>;
81 backlight = <&backlight>;
84 gpio_keys: gpio-keys {
85 compatible = "gpio-keys";
89 pinctrl-names = "default";
90 pinctrl-0 = <&pwr_key_h>;
93 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
94 linux,code = <KEY_POWER>;
95 debounce-interval = <100>;
101 compatible = "gpio-restart";
102 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&ap_warm_reset_h>;
105 priority = /bits/ 8 <200>;
108 emmc_pwrseq: emmc-pwrseq {
109 compatible = "mmc-pwrseq-emmc";
110 pinctrl-0 = <&emmc_reset>;
111 pinctrl-names = "default";
112 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
116 compatible = "rockchip,rockchip-audio-max98090";
117 rockchip,model = "ROCKCHIP-I2S";
118 rockchip,i2s-controller = <&i2s>;
119 rockchip,audio-codec = <&max98090>;
120 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
121 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
122 rockchip,headset-codec = <&headsetcodec>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&mic_det>, <&hp_det>;
127 vdd_logic: pwm-regulator {
128 compatible = "pwm-regulator";
129 pwms = <&pwm1 0 2000 0>;
131 voltage-table = <1350000 0>,
141 regulator-min-microvolt = <950000>;
142 regulator-max-microvolt = <1350000>;
143 regulator-name = "vdd_logic";
144 regulator-ramp-delay = <4000>;
147 vcc33_sys: vcc33-sys {
148 compatible = "regulator-fixed";
149 regulator-name = "vcc33_sys";
152 regulator-min-microvolt = <3300000>;
153 regulator-max-microvolt = <3300000>;
154 vin-supply = <&vccsys>;
158 compatible = "regulator-fixed";
159 regulator-name = "vcc_5v";
162 regulator-min-microvolt = <5000000>;
163 regulator-max-microvolt = <5000000>;
166 vcc50_hdmi: vcc50-hdmi {
167 compatible = "regulator-fixed";
168 regulator-name = "vcc50_hdmi";
171 vin-supply = <&vcc_5v>;
174 bt_regulator: bt-regulator {
176 * On the module itself this is one of these (depending
177 * on the actual card pouplated):
178 * - BT_I2S_WS_BT_RFDISABLE_L
182 compatible = "regulator-fixed";
184 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&bt_enable_l>;
187 regulator-name = "bt_regulator";
190 wifi_regulator: wifi-regulator {
192 * On the module itself this is one of these (depending
193 * on the actual card populated):
194 * - SDIO_RESET_L_WL_REG_ON
195 * - PDN (power down when low)
198 compatible = "regulator-fixed";
200 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&wifi_enable_h>;
203 regulator-name = "wifi_regulator";
205 /* Faux input supply. See bt_regulator description. */
206 vin-supply = <&bt_regulator>;
210 compatible = "rockchip,rk3288-io-voltage-domain";
211 rockchip,grf = <&grf>;
213 audio-supply = <&vcc18_codec>;
214 bb-supply = <&vcc33_io>;
215 dvp-supply = <&vcc_18>;
216 flash0-supply = <&vcc18_flashio>;
217 gpio1830-supply = <&vcc33_io>;
218 gpio30-supply = <&vcc33_io>;
219 lcdc-supply = <&vcc33_lcd>;
220 sdcard-supply = <&vccio_sd>;
221 wifi-supply = <&vcc18_wl>;
226 cpu0-supply = <&vdd_cpu>;
230 logic-supply = <&vdd_logic>;
231 rockchip,odt-disable-freq = <333000000>;
232 rockchip,dll-disable-freq = <333000000>;
233 rockchip,sr-enable-freq = <333000000>;
234 rockchip,pd-enable-freq = <666000000>;
235 rockchip,auto-self-refresh-cnt = <0>;
236 rockchip,auto-power-down-cnt = <64>;
237 rockchip,ddr-speed-bin = <21>;
238 rockchip,trcd = <10>;
258 mmc-pwrseq = <&emmc_pwrseq>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
276 card-external-vcc-supply = <&wifi_regulator>;
277 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
278 <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
279 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
280 keep-power-in-suspend;
283 pinctrl-names = "default";
284 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
286 vmmc-supply = <&vcc33_sys>;
287 vqmmc-supply = <&vcc18_wl>;
298 card-detect-delay = <200>;
299 cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
302 vmmc-supply = <&vcc33_sd>;
303 vqmmc-supply = <&vccio_sd>;
310 spi_flash: spiflash@0 {
312 compatible = "spidev", "spi-flash";
313 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
321 clock-frequency = <400000>;
322 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
323 i2c-scl-rising-time-ns = <100>; /* 45ns measured */
327 compatible = "rockchip,rk808";
328 clock-output-names = "xin32k", "wifibt_32kin";
329 interrupt-parent = <&gpio0>;
330 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&pmic_int_l>;
334 rockchip,system-power-controller;
339 vcc1-supply = <&vcc33_sys>;
340 vcc2-supply = <&vcc33_sys>;
341 vcc3-supply = <&vcc33_sys>;
342 vcc4-supply = <&vcc33_sys>;
343 vcc6-supply = <&vcc_5v>;
344 vcc7-supply = <&vcc33_sys>;
345 vcc8-supply = <&vcc33_sys>;
346 vcc9-supply = <&vcc_5v>;
347 vcc10-supply = <&vcc33_sys>;
348 vcc11-supply = <&vcc_5v>;
349 vcc12-supply = <&vcc_18>;
351 vddio-supply = <&vcc33_io>;
357 regulator-min-microvolt = <750000>;
358 regulator-max-microvolt = <1450000>;
359 regulator-name = "vdd_arm";
360 regulator-ramp-delay = <6001>;
361 regulator-suspend-mem-disabled;
367 regulator-min-microvolt = <800000>;
368 regulator-max-microvolt = <1250000>;
369 regulator-name = "vdd_gpu";
370 regulator-ramp-delay = <6001>;
371 regulator-suspend-mem-disabled;
374 vcc135_ddr: DCDC_REG3 {
377 regulator-name = "vcc135_ddr";
378 regulator-suspend-mem-enabled;
382 * vcc_18 has several aliases. (vcc18_flashio and
383 * vcc18_wl). We'll add those aliases here just to
384 * make it easier to follow the schematic. The signals
385 * are actually hooked together and only separated for
386 * power measurement purposes).
388 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
391 regulator-min-microvolt = <1800000>;
392 regulator-max-microvolt = <1800000>;
393 regulator-name = "vcc_18";
394 regulator-suspend-mem-microvolt = <1800000>;
398 * Note that both vcc33_io and vcc33_pmuio are always
399 * powered together. To simplify the logic in the dts
400 * we just refer to vcc33_io every time something is
401 * powered from vcc33_pmuio. In fact, on later boards
402 * (such as danger) they're the same net.
407 regulator-min-microvolt = <3300000>;
408 regulator-max-microvolt = <3300000>;
409 regulator-name = "vcc33_io";
410 regulator-suspend-mem-microvolt = <3300000>;
416 regulator-min-microvolt = <1000000>;
417 regulator-max-microvolt = <1000000>;
418 regulator-name = "vdd_10";
419 regulator-suspend-mem-microvolt = <1000000>;
423 regulator-min-microvolt = <1800000>;
424 regulator-max-microvolt = <3300000>;
425 regulator-name = "vccio_sd";
426 regulator-suspend-mem-disabled;
430 regulator-min-microvolt = <3300000>;
431 regulator-max-microvolt = <3300000>;
432 regulator-name = "vcc33_sd";
433 regulator-suspend-mem-disabled;
436 vcc18_codec: LDO_REG6 {
439 regulator-min-microvolt = <1800000>;
440 regulator-max-microvolt = <1800000>;
441 regulator-name = "vcc18_codec";
442 regulator-suspend-mem-disabled;
445 vdd10_lcd_pwren_h: LDO_REG7 {
448 regulator-min-microvolt = <2500000>;
449 regulator-max-microvolt = <2500000>;
450 regulator-name = "vdd10_lcd_pwren_h";
451 regulator-suspend-mem-disabled;
454 vcc33_lcd: SWITCH_REG1 {
457 regulator-name = "vcc33_lcd";
458 regulator-suspend-mem-disabled;
467 clock-frequency = <400000>;
468 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
469 i2c-scl-rising-time-ns = <100>; /* 40ns measured */
472 compatible = "infineon,slb9645tt";
474 powered-while-suspended;
481 /* 100kHz since 4.7k resistors don't rise fast enough */
482 clock-frequency = <100000>;
483 i2c-scl-falling-time-ns = <50>; /* 10ns measured */
484 i2c-scl-rising-time-ns = <800>; /* 600ns measured */
486 max98090: max98090@10 {
487 compatible = "maxim,max98090";
489 interrupt-parent = <&gpio6>;
490 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&int_codec>;
499 clock-frequency = <400000>;
500 i2c-scl-falling-time-ns = <50>;
501 i2c-scl-rising-time-ns = <300>;
507 clock-frequency = <400000>;
508 i2c-scl-falling-time-ns = <50>; /* 11ns measured */
509 i2c-scl-rising-time-ns = <300>; /* 225ns measured */
511 headsetcodec: ts3a227e@3b {
512 compatible = "ti,ts3a227e";
514 interrupt-parent = <&gpio0>;
515 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
516 pinctrl-names = "default";
517 pinctrl-0 = <&ts3a227e_int_l>;
518 ti,micbias = <7>; /* MICBIAS = 2.8V */
525 clock-frequency = <100000>;
526 i2c-scl-falling-time-ns = <300>;
527 i2c-scl-rising-time-ns = <1000>;
532 clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
533 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
551 /* Pins don't include flow control by default; add that in */
552 pinctrl-names = "default";
553 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
554 /* We need to go faster than 24MHz, so adjust clock parents / rates */
555 assigned-clocks = <&cru SCLK_UART0>;
556 assigned-clock-rates = <48000000>;
587 rockchip,panel = <&panel>;
603 tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
604 tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
610 pinctrl-names = "default", "sleep";
612 /* Common for sleep and wake, but no owners */
621 /* Common for sleep and wake, but no owners */
630 /* Add this for sdmmc pins to SD card */
631 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
632 drive-strength = <8>;
635 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
637 drive-strength = <8>;
640 pcfg_output_high: pcfg-output-high {
644 pcfg_output_low: pcfg-output-low {
650 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
655 pwr_key_h: pwr-key-h {
656 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
662 rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
664 int_codec: int-codec {
665 rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
668 rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
673 emmc_reset: emmc-reset {
674 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
678 * We run eMMC at max speed; bump up drive strength.
679 * We also have external pulls, so disable the internal ones.
682 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
686 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
689 emmc_bus8: emmc-bus8 {
690 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
691 <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
692 <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
693 <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
694 <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
695 <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
696 <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
697 <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
702 ts3a227e_int_l: ts3a227e-int-l {
703 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
708 pmic_int_l: pmic-int-l {
710 * Causes jerry to hang when probing bus 0
711 * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
717 ap_warm_reset_h: ap-warm-reset-h {
718 rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
723 wifi_enable_h: wifienable-h {
724 rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
727 /* NOTE: mislabelled on schematic; should be bt_enable_h */
728 bt_enable_l: bt-enable-l {
729 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
733 * We run sdio0 at max speed; bump up drive strength.
734 * We also have external pulls, so disable the internal ones.
736 sdio0_bus4: sdio0-bus4 {
737 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
738 <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
739 <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
740 <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
743 sdio0_cmd: sdio0-cmd {
744 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
747 sdio0_clk: sdio0-clk {
748 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
752 * These pins are only present on very new veyron boards; on
753 * older boards bt_dev_wake is simply always high. Note that
754 * gpio4_26 is a NC on old veyron boards, so it doesn't hurt
755 * to map this pin everywhere
757 bt_dev_wake_sleep: bt-dev-wake-sleep {
758 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
761 bt_dev_wake_awake: bt-dev-wake-awake {
762 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
768 * We run sdmmc at max speed; bump up drive strength.
769 * We also have external pulls, so disable the internal ones.
771 sdmmc_bus4: sdmmc-bus4 {
772 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
773 <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
774 <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
775 <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
778 sdmmc_clk: sdmmc-clk {
779 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
782 sdmmc_cmd: sdmmc-cmd {
783 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
787 * Builtin CD line is hooked to ground to prevent JTAG at boot
788 * (and also to get the voltage rail correct). Make we
789 * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
790 * think there's a card inserted
792 sdmmc_cd_disabled: sdmmc-cd-disabled {
793 rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
796 /* This is where we actually hook up CD */
797 sdmmc_cd_gpio: sdmmc-cd-gpio {
798 rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
803 tpm_int_h: tpm-int-h {
804 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
810 rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
821 needs-reset-on-resume;
831 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
832 assigned-clock-parents = <&cru SCLK_OTGPHY0>;