arch/arm/dts/rk3288-veyron.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Google Veyron (and derivatives) board device tree source
   4  *
   5  * Copyright 2014 Google, Inc
   6  */
   7
   8 #include <dt-bindings/clock/rockchip,rk808.h>
   9 #include <dt-bindings/input/input.h>
  10 #include "rk3288.dtsi"
  11
  12 / {
  13         memory {
  14                 reg = <0x0 0x80000000>;
  15         };
  16
  17         chosen {
  18                 stdout-path = &uart2;
  19         };
  20
  21         config {
  22                 u-boot,dm-pre-reloc;
  23                 u-boot,boot0 = &spi_flash;
  24         };
  25
  26         firmware {
  27                 chromeos {
  28                         pinctrl-names = "default";
  29                         pinctrl-0 = <&fw_wp_ap>;
  30                         write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
  31                 };
  32         };
  33
  34         backlight: backlight {
  35                 compatible = "pwm-backlight";
  36                 brightness-levels = <
  37                           0   1   2   3   4   5   6   7
  38                           8   9  10  11  12  13  14  15
  39                          16  17  18  19  20  21  22  23
  40                          24  25  26  27  28  29  30  31
  41                          32  33  34  35  36  37  38  39
  42                          40  41  42  43  44  45  46  47
  43                          48  49  50  51  52  53  54  55
  44                          56  57  58  59  60  61  62  63
  45                          64  65  66  67  68  69  70  71
  46                          72  73  74  75  76  77  78  79
  47                          80  81  82  83  84  85  86  87
  48                          88  89  90  91  92  93  94  95
  49                          96  97  98  99 100 101 102 103
  50                         104 105 106 107 108 109 110 111
  51                         112 113 114 115 116 117 118 119
  52                         120 121 122 123 124 125 126 127
  53                         128 129 130 131 132 133 134 135
  54                         136 137 138 139 140 141 142 143
  55                         144 145 146 147 148 149 150 151
  56                         152 153 154 155 156 157 158 159
  57                         160 161 162 163 164 165 166 167
  58                         168 169 170 171 172 173 174 175
  59                         176 177 178 179 180 181 182 183
  60                         184 185 186 187 188 189 190 191
  61                         192 193 194 195 196 197 198 199
  62                         200 201 202 203 204 205 206 207
  63                         208 209 210 211 212 213 214 215
  64                         216 217 218 219 220 221 222 223
  65                         224 225 226 227 228 229 230 231
  66                         232 233 234 235 236 237 238 239
  67                         240 241 242 243 244 245 246 247
  68                         248 249 250 251 252 253 254 255>;
  69                 default-brightness-level = <128>;
  70                 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
  71                 backlight-boot-off;
  72                 pinctrl-names = "default";
  73                 pinctrl-0 = <&bl_en>;
  74                 pwms = <&pwm0 0 1000000 0>;
  75         };
  76
  77         panel: panel {
  78                 compatible ="cnm,n116bgeea2","simple-panel";
  79                 status = "okay";
  80                 power-supply = <&vcc33_lcd>;
  81                 backlight = <&backlight>;
  82         };
  83
  84         gpio_keys: gpio-keys {
  85                 compatible = "gpio-keys";
  86                 #address-cells = <1>;
  87                 #size-cells = <0>;
  88
  89                 pinctrl-names = "default";
  90                 pinctrl-0 = <&pwr_key_h>;
  91                 power {
  92                         label = "Power";
  93                         gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
  94                         linux,code = <KEY_POWER>;
  95                         debounce-interval = <100>;
  96                         gpio-key,wakeup;
  97                 };
  98         };
  99
 100         gpio-restart {
 101                 compatible = "gpio-restart";
 102                 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
 103                 pinctrl-names = "default";
 104                 pinctrl-0 = <&ap_warm_reset_h>;
 105                 priority = /bits/ 8 <200>;
 106         };
 107
 108         emmc_pwrseq: emmc-pwrseq {
 109                 compatible = "mmc-pwrseq-emmc";
 110                 pinctrl-0 = <&emmc_reset>;
 111                 pinctrl-names = "default";
 112                 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
 113         };
 114
 115         sound {
 116                 compatible = "rockchip,rockchip-audio-max98090";
 117                 rockchip,model = "ROCKCHIP-I2S";
 118                 rockchip,i2s-controller = <&i2s>;
 119                 rockchip,audio-codec = <&max98090>;
 120                 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
 121                 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 122                 rockchip,headset-codec = <&headsetcodec>;
 123                 pinctrl-names = "default";
 124                 pinctrl-0 = <&mic_det>, <&hp_det>;
 125         };
 126
 127         vdd_logic: pwm-regulator {
 128                 compatible = "pwm-regulator";
 129                 pwms = <&pwm1 0 2000 0>;
 130
 131                 voltage-table = <1350000 0>,
 132                                 <1300000 10>,
 133                                 <1250000 20>,
 134                                 <1200000 31>,
 135                                 <1150000 41>,
 136                                 <1100000 52>,
 137                                 <1050000 62>,
 138                                 <1000000 72>,
 139                                 < 950000 83>;
 140
 141                 regulator-min-microvolt = <950000>;
 142                 regulator-max-microvolt = <1350000>;
 143                 regulator-name = "vdd_logic";
 144                 regulator-ramp-delay = <4000>;
 145         };
 146
 147         vcc33_sys: vcc33-sys {
 148                 compatible = "regulator-fixed";
 149                 regulator-name = "vcc33_sys";
 150                 regulator-always-on;
 151                 regulator-boot-on;
 152                 regulator-min-microvolt = <3300000>;
 153                 regulator-max-microvolt = <3300000>;
 154                 vin-supply = <&vccsys>;
 155         };
 156
 157         vcc_5v: vcc-5v {
 158                 compatible = "regulator-fixed";
 159                 regulator-name = "vcc_5v";
 160                 regulator-always-on;
 161                 regulator-boot-on;
 162                 regulator-min-microvolt = <5000000>;
 163                 regulator-max-microvolt = <5000000>;
 164         };
 165
 166         vcc50_hdmi: vcc50-hdmi {
 167                 compatible = "regulator-fixed";
 168                 regulator-name = "vcc50_hdmi";
 169                 regulator-always-on;
 170                 regulator-boot-on;
 171                 vin-supply = <&vcc_5v>;
 172         };
 173
 174         bt_regulator: bt-regulator {
 175                 /*
 176                  * On the module itself this is one of these (depending
 177                  * on the actual card pouplated):
 178                  * - BT_I2S_WS_BT_RFDISABLE_L
 179                  * - No connect
 180                  */
 181
 182                 compatible = "regulator-fixed";
 183                 enable-active-high;
 184                 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
 185                 pinctrl-names = "default";
 186                 pinctrl-0 = <&bt_enable_l>;
 187                 regulator-name = "bt_regulator";
 188         };
 189
 190         wifi_regulator: wifi-regulator {
 191                 /*
 192                  * On the module itself this is one of these (depending
 193                  * on the actual card populated):
 194                  * - SDIO_RESET_L_WL_REG_ON
 195                  * - PDN (power down when low)
 196                  */
 197
 198                 compatible = "regulator-fixed";
 199                 enable-active-high;
 200                 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
 201                 pinctrl-names = "default";
 202                 pinctrl-0 = <&wifi_enable_h>;
 203                 regulator-name = "wifi_regulator";
 204
 205                 /* Faux input supply.  See bt_regulator description. */
 206                 vin-supply = <&bt_regulator>;
 207         };
 208
 209         io-domains {
 210                 compatible = "rockchip,rk3288-io-voltage-domain";
 211                 rockchip,grf = <&grf>;
 212
 213                 audio-supply = <&vcc18_codec>;
 214                 bb-supply = <&vcc33_io>;
 215                 dvp-supply = <&vcc_18>;
 216                 flash0-supply = <&vcc18_flashio>;
 217                 gpio1830-supply = <&vcc33_io>;
 218                 gpio30-supply = <&vcc33_io>;
 219                 lcdc-supply = <&vcc33_lcd>;
 220                 sdcard-supply = <&vccio_sd>;
 221                 wifi-supply = <&vcc18_wl>;
 222         };
 223 };
 224
 225 &cpu0 {
 226         cpu0-supply = <&vdd_cpu>;
 227 };
 228
 229 &dmc {
 230         logic-supply = <&vdd_logic>;
 231         rockchip,odt-disable-freq = <333000000>;
 232         rockchip,dll-disable-freq = <333000000>;
 233         rockchip,sr-enable-freq = <333000000>;
 234         rockchip,pd-enable-freq = <666000000>;
 235         rockchip,auto-self-refresh-cnt = <0>;
 236         rockchip,auto-power-down-cnt = <64>;
 237         rockchip,ddr-speed-bin = <21>;
 238         rockchip,trcd = <10>;
 239         rockchip,trp = <10>;
 240         operating-points = <
 241                 /* KHz    uV */
 242                 200000 1050000
 243                 333000 1100000
 244                 533000 1150000
 245                 666000 1200000
 246         >;
 247 };
 248
 249 &efuse {
 250         status = "okay";
 251 };
 252
 253 &emmc {
 254         broken-cd;
 255         bus-width = <8>;
 256         cap-mmc-highspeed;
 257         mmc-hs200-1_8v;
 258         mmc-pwrseq = <&emmc_pwrseq>;
 259         disable-wp;
 260         non-removable;
 261         num-slots = <1>;
 262         pinctrl-names = "default";
 263         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
 264         status = "okay";
 265 };
 266
 267 &sdio0 {
 268         broken-cd;
 269         bus-width = <4>;
 270         cap-sd-highspeed;
 271         sd-uhs-sdr12;
 272         sd-uhs-sdr25;
 273         sd-uhs-sdr50;
 274         sd-uhs-sdr104;
 275         cap-sdio-irq;
 276         card-external-vcc-supply = <&wifi_regulator>;
 277         clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
 278                  <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
 279         clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
 280         keep-power-in-suspend;
 281         non-removable;
 282         num-slots = <1>;
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 285         status = "okay";
 286         vmmc-supply = <&vcc33_sys>;
 287         vqmmc-supply = <&vcc18_wl>;
 288 };
 289
 290 &sdmmc {
 291         bus-width = <4>;
 292         cap-mmc-highspeed;
 293         cap-sd-highspeed;
 294         sd-uhs-sdr12;
 295         sd-uhs-sdr25;
 296         sd-uhs-sdr50;
 297         sd-uhs-sdr104;
 298         card-detect-delay = <200>;
 299         cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
 300         num-slots = <1>;
 301         status = "okay";
 302         vmmc-supply = <&vcc33_sd>;
 303         vqmmc-supply = <&vccio_sd>;
 304 };
 305
 306 &spi2 {
 307         status = "okay";
 308         u-boot,dm-pre-reloc;
 309
 310         spi_flash: spiflash@0 {
 311                 u-boot,dm-pre-reloc;
 312                 compatible = "spidev", "spi-flash";
 313                 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
 314                 reg = <0>;
 315         };
 316 };
 317
 318 &i2c0 {
 319         status = "okay";
 320
 321         clock-frequency = <400000>;
 322         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 323         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 324         u-boot,dm-pre-reloc;
 325
 326         rk808: pmic@1b {
 327                 compatible = "rockchip,rk808";
 328                 clock-output-names = "xin32k", "wifibt_32kin";
 329                 interrupt-parent = <&gpio0>;
 330                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&pmic_int_l>;
 333                 reg = <0x1b>;
 334                 rockchip,system-power-controller;
 335                 wakeup-source;
 336                 #clock-cells = <1>;
 337                 u-boot,dm-pre-reloc;
 338
 339                 vcc1-supply = <&vcc33_sys>;
 340                 vcc2-supply = <&vcc33_sys>;
 341                 vcc3-supply = <&vcc33_sys>;
 342                 vcc4-supply = <&vcc33_sys>;
 343                 vcc6-supply = <&vcc_5v>;
 344                 vcc7-supply = <&vcc33_sys>;
 345                 vcc8-supply = <&vcc33_sys>;
 346                 vcc9-supply = <&vcc_5v>;
 347                 vcc10-supply = <&vcc33_sys>;
 348                 vcc11-supply = <&vcc_5v>;
 349                 vcc12-supply = <&vcc_18>;
 350
 351                 vddio-supply = <&vcc33_io>;
 352
 353                 regulators {
 354                         vdd_cpu: DCDC_REG1 {
 355                                 regulator-always-on;
 356                                 regulator-boot-on;
 357                                 regulator-min-microvolt = <750000>;
 358                                 regulator-max-microvolt = <1450000>;
 359                                 regulator-name = "vdd_arm";
 360                                 regulator-ramp-delay = <6001>;
 361                                 regulator-suspend-mem-disabled;
 362                         };
 363
 364                         vdd_gpu: DCDC_REG2 {
 365                                 regulator-always-on;
 366                                 regulator-boot-on;
 367                                 regulator-min-microvolt = <800000>;
 368                                 regulator-max-microvolt = <1250000>;
 369                                 regulator-name = "vdd_gpu";
 370                                 regulator-ramp-delay = <6001>;
 371                                 regulator-suspend-mem-disabled;
 372                         };
 373
 374                         vcc135_ddr: DCDC_REG3 {
 375                                 regulator-always-on;
 376                                 regulator-boot-on;
 377                                 regulator-name = "vcc135_ddr";
 378                                 regulator-suspend-mem-enabled;
 379                         };
 380
 381                         /*
 382                          * vcc_18 has several aliases.  (vcc18_flashio and
 383                          * vcc18_wl).  We'll add those aliases here just to
 384                          * make it easier to follow the schematic.  The signals
 385                          * are actually hooked together and only separated for
 386                          * power measurement purposes).
 387                          */
 388                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 389                                 regulator-always-on;
 390                                 regulator-boot-on;
 391                                 regulator-min-microvolt = <1800000>;
 392                                 regulator-max-microvolt = <1800000>;
 393                                 regulator-name = "vcc_18";
 394                                 regulator-suspend-mem-microvolt = <1800000>;
 395                         };
 396
 397                         /*
 398                          * Note that both vcc33_io and vcc33_pmuio are always
 399                          * powered together. To simplify the logic in the dts
 400                          * we just refer to vcc33_io every time something is
 401                          * powered from vcc33_pmuio. In fact, on later boards
 402                          * (such as danger) they're the same net.
 403                          */
 404                         vcc33_io: LDO_REG1 {
 405                                 regulator-always-on;
 406                                 regulator-boot-on;
 407                                 regulator-min-microvolt = <3300000>;
 408                                 regulator-max-microvolt = <3300000>;
 409                                 regulator-name = "vcc33_io";
 410                                 regulator-suspend-mem-microvolt = <3300000>;
 411                         };
 412
 413                         vdd_10: LDO_REG3 {
 414                                 regulator-always-on;
 415                                 regulator-boot-on;
 416                                 regulator-min-microvolt = <1000000>;
 417                                 regulator-max-microvolt = <1000000>;
 418                                 regulator-name = "vdd_10";
 419                                 regulator-suspend-mem-microvolt = <1000000>;
 420                         };
 421
 422                         vccio_sd: LDO_REG4 {
 423                                 regulator-min-microvolt = <1800000>;
 424                                 regulator-max-microvolt = <3300000>;
 425                                 regulator-name = "vccio_sd";
 426                                 regulator-suspend-mem-disabled;
 427                         };
 428
 429                         vcc33_sd: LDO_REG5 {
 430                                 regulator-min-microvolt = <3300000>;
 431                                 regulator-max-microvolt = <3300000>;
 432                                 regulator-name = "vcc33_sd";
 433                                 regulator-suspend-mem-disabled;
 434                         };
 435
 436                         vcc18_codec: LDO_REG6 {
 437                                 regulator-always-on;
 438                                 regulator-boot-on;
 439                                 regulator-min-microvolt = <1800000>;
 440                                 regulator-max-microvolt = <1800000>;
 441                                 regulator-name = "vcc18_codec";
 442                                 regulator-suspend-mem-disabled;
 443                         };
 444
 445                         vdd10_lcd_pwren_h: LDO_REG7 {
 446                                 regulator-always-on;
 447                                 regulator-boot-on;
 448                                 regulator-min-microvolt = <2500000>;
 449                                 regulator-max-microvolt = <2500000>;
 450                                 regulator-name = "vdd10_lcd_pwren_h";
 451                                 regulator-suspend-mem-disabled;
 452                         };
 453
 454                         vcc33_lcd: SWITCH_REG1 {
 455                                 regulator-always-on;
 456                                 regulator-boot-on;
 457                                 regulator-name = "vcc33_lcd";
 458                                 regulator-suspend-mem-disabled;
 459                         };
 460                 };
 461         };
 462 };
 463
 464 &i2c1 {
 465         status = "okay";
 466
 467         clock-frequency = <400000>;
 468         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 469         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 470
 471         tpm: tpm@20 {
 472                 compatible = "infineon,slb9645tt";
 473                 reg = <0x20>;
 474                 powered-while-suspended;
 475         };
 476 };
 477
 478 &i2c2 {
 479         status = "okay";
 480
 481         /* 100kHz since 4.7k resistors don't rise fast enough */
 482         clock-frequency = <100000>;
 483         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 484         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 485
 486         max98090: max98090@10 {
 487                 compatible = "maxim,max98090";
 488                 reg = <0x10>;
 489                 interrupt-parent = <&gpio6>;
 490                 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
 491                 pinctrl-names = "default";
 492                 pinctrl-0 = <&int_codec>;
 493         };
 494 };
 495
 496 &i2c3 {
 497         status = "okay";
 498
 499         clock-frequency = <400000>;
 500         i2c-scl-falling-time-ns = <50>;
 501         i2c-scl-rising-time-ns = <300>;
 502 };
 503
 504 &i2c4 {
 505         status = "okay";
 506
 507         clock-frequency = <400000>;
 508         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 509         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 510
 511         headsetcodec: ts3a227e@3b {
 512                 compatible = "ti,ts3a227e";
 513                 reg = <0x3b>;
 514                 interrupt-parent = <&gpio0>;
 515                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&ts3a227e_int_l>;
 518                 ti,micbias = <7>;               /* MICBIAS = 2.8V */
 519         };
 520 };
 521
 522 &i2c5 {
 523         status = "okay";
 524
 525         clock-frequency = <100000>;
 526         i2c-scl-falling-time-ns = <300>;
 527         i2c-scl-rising-time-ns = <1000>;
 528 };
 529
 530 &i2s {
 531         status = "okay";
 532         clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
 533         clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
 534 };
 535
 536 &wdt {
 537         status = "okay";
 538 };
 539
 540 &pwm0 {
 541         status = "okay";
 542 };
 543
 544 &pwm1 {
 545         status = "okay";
 546 };
 547
 548 &uart0 {
 549         status = "okay";
 550
 551         /* Pins don't include flow control by default; add that in */
 552         pinctrl-names = "default";
 553         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 554         /* We need to go faster than 24MHz, so adjust clock parents / rates */
 555         assigned-clocks = <&cru SCLK_UART0>;
 556         assigned-clock-rates = <48000000>;
 557 };
 558
 559 &uart1 {
 560         status = "okay";
 561 };
 562
 563 &uart2 {
 564         status = "okay";
 565         u-boot,dm-pre-reloc;
 566         reg-shift = <2>;
 567 };
 568
 569 &vopb {
 570         status = "okay";
 571 };
 572
 573 &vopb_mmu {
 574         status = "okay";
 575 };
 576
 577 &vopl {
 578         status = "okay";
 579 };
 580
 581 &vopl_mmu {
 582         status = "okay";
 583 };
 584
 585 &edp {
 586         status = "okay";
 587         rockchip,panel = <&panel>;
 588 };
 589
 590 &hdmi {
 591         status = "okay";
 592 };
 593
 594 &hdmi_audio {
 595         status = "okay";
 596 };
 597
 598 &gpu {
 599         status = "okay";
 600 };
 601
 602 &tsadc {
 603         tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 604         tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 605         status = "okay";
 606 };
 607
 608 &pinctrl {
 609         u-boot,dm-pre-reloc;
 610         pinctrl-names = "default", "sleep";
 611         pinctrl-0 = <
 612                 /* Common for sleep and wake, but no owners */
 613                 &ddr0_retention
 614                 &ddrio_pwroff
 615                 &global_pwroff
 616
 617                 /* Wake only */
 618                 &bt_dev_wake_awake
 619         >;
 620         pinctrl-1 = <
 621                 /* Common for sleep and wake, but no owners */
 622                 &ddr0_retention
 623                 &ddrio_pwroff
 624                 &global_pwroff
 625
 626                 /* Sleep only */
 627                 &bt_dev_wake_sleep
 628         >;
 629
 630         /* Add this for sdmmc pins to SD card */
 631         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 632                 drive-strength = <8>;
 633         };
 634
 635         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 636                 bias-pull-up;
 637                 drive-strength = <8>;
 638         };
 639
 640         pcfg_output_high: pcfg-output-high {
 641                 output-high;
 642         };
 643
 644         pcfg_output_low: pcfg-output-low {
 645                 output-low;
 646         };
 647
 648         backlight {
 649                 bl_en: bl-en {
 650                         rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
 651                 };
 652         };
 653
 654         buttons {
 655                 pwr_key_h: pwr-key-h {
 656                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
 657                 };
 658         };
 659
 660         codec {
 661                 hp_det: hp-det {
 662                         rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
 663                 };
 664                 int_codec: int-codec {
 665                         rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
 666                 };
 667                 mic_det: mic-det {
 668                         rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
 669                 };
 670         };
 671
 672         emmc {
 673                 emmc_reset: emmc-reset {
 674                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 675                 };
 676
 677                 /*
 678                  * We run eMMC at max speed; bump up drive strength.
 679                  * We also have external pulls, so disable the internal ones.
 680                  */
 681                 emmc_clk: emmc-clk {
 682                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 683                 };
 684
 685                 emmc_cmd: emmc-cmd {
 686                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 687                 };
 688
 689                 emmc_bus8: emmc-bus8 {
 690                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 691                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 692                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 693                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 694                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 695                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 696                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 697                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 698                 };
 699         };
 700
 701         headset {
 702                 ts3a227e_int_l: ts3a227e-int-l {
 703                         rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
 704                 };
 705         };
 706
 707         pmic {
 708                 pmic_int_l: pmic-int-l {
 709                         /*
 710                          * Causes jerry to hang when probing bus 0
 711                          * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 712                          */
 713                 };
 714         };
 715
 716         reboot {
 717                 ap_warm_reset_h: ap-warm-reset-h {
 718                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 719                 };
 720         };
 721
 722         sdio0 {
 723                 wifi_enable_h: wifienable-h {
 724                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 725                 };
 726
 727                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 728                 bt_enable_l: bt-enable-l {
 729                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 730                 };
 731
 732                 /*
 733                  * We run sdio0 at max speed; bump up drive strength.
 734                  * We also have external pulls, so disable the internal ones.
 735                  */
 736                 sdio0_bus4: sdio0-bus4 {
 737                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 738                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 739                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 740                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 741                 };
 742
 743                 sdio0_cmd: sdio0-cmd {
 744                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 745                 };
 746
 747                 sdio0_clk: sdio0-clk {
 748                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 749                 };
 750
 751                 /*
 752                  * These pins are only present on very new veyron boards; on
 753                  * older boards bt_dev_wake is simply always high.  Note that
 754                  * gpio4_26 is a NC on old veyron boards, so it doesn't hurt
 755                  * to map this pin everywhere
 756                  */
 757                 bt_dev_wake_sleep: bt-dev-wake-sleep {
 758                         rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
 759                 };
 760
 761                 bt_dev_wake_awake: bt-dev-wake-awake {
 762                         rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
 763                 };
 764         };
 765
 766         sdmmc {
 767                 /*
 768                  * We run sdmmc at max speed; bump up drive strength.
 769                  * We also have external pulls, so disable the internal ones.
 770                  */
 771                 sdmmc_bus4: sdmmc-bus4 {
 772                         rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 773                                         <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 774                                         <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 775                                         <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 776                 };
 777
 778                 sdmmc_clk: sdmmc-clk {
 779                         rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 780                 };
 781
 782                 sdmmc_cmd: sdmmc-cmd {
 783                         rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 784                 };
 785
 786                 /*
 787                  * Builtin CD line is hooked to ground to prevent JTAG at boot
 788                  * (and also to get the voltage rail correct).  Make we
 789                  * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
 790                  * think there's a card inserted
 791                  */
 792                 sdmmc_cd_disabled: sdmmc-cd-disabled {
 793                         rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
 794                 };
 795
 796                 /* This is where we actually hook up CD */
 797                 sdmmc_cd_gpio: sdmmc-cd-gpio {
 798                         rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
 799                 };
 800         };
 801
 802         tpm {
 803                 tpm_int_h: tpm-int-h {
 804                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 805                 };
 806         };
 807
 808         write-protect {
 809                 fw_wp_ap: fw-wp-ap {
 810                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 811                 };
 812         };
 813 };
 814
 815 &usbphy {
 816         status = "okay";
 817 };
 818
 819 &usb_host0_ehci {
 820         status = "okay";
 821         needs-reset-on-resume;
 822 };
 823
 824 &usb_host1 {
 825         status = "okay";
 826 };
 827
 828 &usb_otg {
 829         dr_mode = "host";
 830         status = "okay";
 831         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 832         assigned-clock-parents = <&cru SCLK_OTGPHY0>;
 833 };
 834
 835 &sdmmc {
 836         u-boot,dm-pre-reloc;
 837 };
 838
 839 &gpio3 {
 840         u-boot,dm-pre-reloc;
 841 };
 842
 843 &gpio8 {
 844         u-boot,dm-pre-reloc;
 845 };