1 // SPDX-License-Identifier: GPL-2.0
3 * Google Veyron (and derivatives) board device tree source
5 * Copyright 2014 Google, Inc
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
10 #include "rk3288.dtsi"
14 reg = <0x0 0x80000000>;
23 u-boot,boot0 = &spi_flash;
28 pinctrl-names = "default";
29 pinctrl-0 = <&fw_wp_ap>;
30 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
34 backlight: backlight {
35 compatible = "pwm-backlight";
39 16 17 18 19 20 21 22 23
40 24 25 26 27 28 29 30 31
41 32 33 34 35 36 37 38 39
42 40 41 42 43 44 45 46 47
43 48 49 50 51 52 53 54 55
44 56 57 58 59 60 61 62 63
45 64 65 66 67 68 69 70 71
46 72 73 74 75 76 77 78 79
47 80 81 82 83 84 85 86 87
48 88 89 90 91 92 93 94 95
49 96 97 98 99 100 101 102 103
50 104 105 106 107 108 109 110 111
51 112 113 114 115 116 117 118 119
52 120 121 122 123 124 125 126 127
53 128 129 130 131 132 133 134 135
54 136 137 138 139 140 141 142 143
55 144 145 146 147 148 149 150 151
56 152 153 154 155 156 157 158 159
57 160 161 162 163 164 165 166 167
58 168 169 170 171 172 173 174 175
59 176 177 178 179 180 181 182 183
60 184 185 186 187 188 189 190 191
61 192 193 194 195 196 197 198 199
62 200 201 202 203 204 205 206 207
63 208 209 210 211 212 213 214 215
64 216 217 218 219 220 221 222 223
65 224 225 226 227 228 229 230 231
66 232 233 234 235 236 237 238 239
67 240 241 242 243 244 245 246 247
68 248 249 250 251 252 253 254 255>;
69 default-brightness-level = <128>;
70 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
72 pinctrl-names = "default";
74 pwms = <&pwm0 0 1000000 0>;
78 compatible ="cnm,n116bgeea2","simple-panel";
80 power-supply = <&vcc33_lcd>;
81 backlight = <&backlight>;
84 gpio_keys: gpio-keys {
85 compatible = "gpio-keys";
87 pinctrl-names = "default";
88 pinctrl-0 = <&pwr_key_h>;
91 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
92 linux,code = <KEY_POWER>;
93 debounce-interval = <100>;
99 compatible = "gpio-restart";
100 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&ap_warm_reset_h>;
103 priority = /bits/ 8 <200>;
106 emmc_pwrseq: emmc-pwrseq {
107 compatible = "mmc-pwrseq-emmc";
108 pinctrl-0 = <&emmc_reset>;
109 pinctrl-names = "default";
110 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
114 compatible = "rockchip,rockchip-audio-max98090";
115 rockchip,model = "ROCKCHIP-I2S";
116 rockchip,i2s-controller = <&i2s>;
117 rockchip,audio-codec = <&max98090>;
118 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
119 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
120 rockchip,headset-codec = <&headsetcodec>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&mic_det>, <&hp_det>;
125 vdd_logic: pwm-regulator {
126 compatible = "pwm-regulator";
127 pwms = <&pwm1 0 2000 0>;
129 voltage-table = <1350000 0>,
139 regulator-min-microvolt = <950000>;
140 regulator-max-microvolt = <1350000>;
141 regulator-name = "vdd_logic";
142 regulator-ramp-delay = <4000>;
145 vcc33_sys: vcc33-sys {
146 compatible = "regulator-fixed";
147 regulator-name = "vcc33_sys";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 vin-supply = <&vccsys>;
156 compatible = "regulator-fixed";
157 regulator-name = "vcc_5v";
160 regulator-min-microvolt = <5000000>;
161 regulator-max-microvolt = <5000000>;
164 vcc50_hdmi: vcc50-hdmi {
165 compatible = "regulator-fixed";
166 regulator-name = "vcc50_hdmi";
169 vin-supply = <&vcc_5v>;
172 bt_regulator: bt-regulator {
174 * On the module itself this is one of these (depending
175 * on the actual card pouplated):
176 * - BT_I2S_WS_BT_RFDISABLE_L
180 compatible = "regulator-fixed";
182 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&bt_enable_l>;
185 regulator-name = "bt_regulator";
188 wifi_regulator: wifi-regulator {
190 * On the module itself this is one of these (depending
191 * on the actual card populated):
192 * - SDIO_RESET_L_WL_REG_ON
193 * - PDN (power down when low)
196 compatible = "regulator-fixed";
198 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&wifi_enable_h>;
201 regulator-name = "wifi_regulator";
203 /* Faux input supply. See bt_regulator description. */
204 vin-supply = <&bt_regulator>;
208 compatible = "rockchip,rk3288-io-voltage-domain";
209 rockchip,grf = <&grf>;
211 audio-supply = <&vcc18_codec>;
212 bb-supply = <&vcc33_io>;
213 dvp-supply = <&vcc_18>;
214 flash0-supply = <&vcc18_flashio>;
215 gpio1830-supply = <&vcc33_io>;
216 gpio30-supply = <&vcc33_io>;
217 lcdc-supply = <&vcc33_lcd>;
218 sdcard-supply = <&vccio_sd>;
219 wifi-supply = <&vcc18_wl>;
224 cpu0-supply = <&vdd_cpu>;
228 logic-supply = <&vdd_logic>;
229 rockchip,odt-disable-freq = <333000000>;
230 rockchip,dll-disable-freq = <333000000>;
231 rockchip,sr-enable-freq = <333000000>;
232 rockchip,pd-enable-freq = <666000000>;
233 rockchip,auto-self-refresh-cnt = <0>;
234 rockchip,auto-power-down-cnt = <64>;
235 rockchip,ddr-speed-bin = <21>;
236 rockchip,trcd = <10>;
256 mmc-pwrseq = <&emmc_pwrseq>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
274 card-external-vcc-supply = <&wifi_regulator>;
275 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
276 <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
277 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
278 keep-power-in-suspend;
281 pinctrl-names = "default";
282 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
284 vmmc-supply = <&vcc33_sys>;
285 vqmmc-supply = <&vcc18_wl>;
296 card-detect-delay = <200>;
297 cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
300 vmmc-supply = <&vcc33_sd>;
301 vqmmc-supply = <&vccio_sd>;
308 spi_flash: spiflash@0 {
310 compatible = "spidev", "spi-flash";
311 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
319 clock-frequency = <400000>;
320 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
321 i2c-scl-rising-time-ns = <100>; /* 45ns measured */
325 compatible = "rockchip,rk808";
326 clock-output-names = "xin32k", "wifibt_32kin";
327 interrupt-parent = <&gpio0>;
328 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pmic_int_l>;
332 rockchip,system-power-controller;
337 vcc1-supply = <&vcc33_sys>;
338 vcc2-supply = <&vcc33_sys>;
339 vcc3-supply = <&vcc33_sys>;
340 vcc4-supply = <&vcc33_sys>;
341 vcc6-supply = <&vcc_5v>;
342 vcc7-supply = <&vcc33_sys>;
343 vcc8-supply = <&vcc33_sys>;
344 vcc9-supply = <&vcc_5v>;
345 vcc10-supply = <&vcc33_sys>;
346 vcc11-supply = <&vcc_5v>;
347 vcc12-supply = <&vcc_18>;
349 vddio-supply = <&vcc33_io>;
355 regulator-min-microvolt = <750000>;
356 regulator-max-microvolt = <1450000>;
357 regulator-name = "vdd_arm";
358 regulator-ramp-delay = <6001>;
359 regulator-suspend-mem-disabled;
365 regulator-min-microvolt = <800000>;
366 regulator-max-microvolt = <1250000>;
367 regulator-name = "vdd_gpu";
368 regulator-ramp-delay = <6001>;
369 regulator-suspend-mem-disabled;
372 vcc135_ddr: DCDC_REG3 {
375 regulator-name = "vcc135_ddr";
376 regulator-suspend-mem-enabled;
380 * vcc_18 has several aliases. (vcc18_flashio and
381 * vcc18_wl). We'll add those aliases here just to
382 * make it easier to follow the schematic. The signals
383 * are actually hooked together and only separated for
384 * power measurement purposes).
386 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
389 regulator-min-microvolt = <1800000>;
390 regulator-max-microvolt = <1800000>;
391 regulator-name = "vcc_18";
392 regulator-suspend-mem-microvolt = <1800000>;
396 * Note that both vcc33_io and vcc33_pmuio are always
397 * powered together. To simplify the logic in the dts
398 * we just refer to vcc33_io every time something is
399 * powered from vcc33_pmuio. In fact, on later boards
400 * (such as danger) they're the same net.
405 regulator-min-microvolt = <3300000>;
406 regulator-max-microvolt = <3300000>;
407 regulator-name = "vcc33_io";
408 regulator-suspend-mem-microvolt = <3300000>;
414 regulator-min-microvolt = <1000000>;
415 regulator-max-microvolt = <1000000>;
416 regulator-name = "vdd_10";
417 regulator-suspend-mem-microvolt = <1000000>;
421 regulator-min-microvolt = <1800000>;
422 regulator-max-microvolt = <3300000>;
423 regulator-name = "vccio_sd";
424 regulator-suspend-mem-disabled;
428 regulator-min-microvolt = <3300000>;
429 regulator-max-microvolt = <3300000>;
430 regulator-name = "vcc33_sd";
431 regulator-suspend-mem-disabled;
434 vcc18_codec: LDO_REG6 {
437 regulator-min-microvolt = <1800000>;
438 regulator-max-microvolt = <1800000>;
439 regulator-name = "vcc18_codec";
440 regulator-suspend-mem-disabled;
443 vdd10_lcd_pwren_h: LDO_REG7 {
446 regulator-min-microvolt = <2500000>;
447 regulator-max-microvolt = <2500000>;
448 regulator-name = "vdd10_lcd_pwren_h";
449 regulator-suspend-mem-disabled;
452 vcc33_lcd: SWITCH_REG1 {
455 regulator-name = "vcc33_lcd";
456 regulator-suspend-mem-disabled;
465 clock-frequency = <400000>;
466 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
467 i2c-scl-rising-time-ns = <100>; /* 40ns measured */
470 compatible = "infineon,slb9645tt";
472 powered-while-suspended;
479 /* 100kHz since 4.7k resistors don't rise fast enough */
480 clock-frequency = <100000>;
481 i2c-scl-falling-time-ns = <50>; /* 10ns measured */
482 i2c-scl-rising-time-ns = <800>; /* 600ns measured */
484 max98090: max98090@10 {
485 compatible = "maxim,max98090";
487 #sound-dai-cells = <0>;
488 interrupt-parent = <&gpio6>;
489 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&int_codec>;
498 clock-frequency = <400000>;
499 i2c-scl-falling-time-ns = <50>;
500 i2c-scl-rising-time-ns = <300>;
506 clock-frequency = <400000>;
507 i2c-scl-falling-time-ns = <50>; /* 11ns measured */
508 i2c-scl-rising-time-ns = <300>; /* 225ns measured */
510 headsetcodec: ts3a227e@3b {
511 compatible = "ti,ts3a227e";
513 interrupt-parent = <&gpio0>;
514 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&ts3a227e_int_l>;
517 ti,micbias = <7>; /* MICBIAS = 2.8V */
524 clock-frequency = <100000>;
525 i2c-scl-falling-time-ns = <300>;
526 i2c-scl-rising-time-ns = <1000>;
531 clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
532 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
550 /* Pins don't include flow control by default; add that in */
551 pinctrl-names = "default";
552 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
553 /* We need to go faster than 24MHz, so adjust clock parents / rates */
554 assigned-clocks = <&cru SCLK_UART0>;
555 assigned-clock-rates = <48000000>;
586 rockchip,panel = <&panel>;
602 tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
603 tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
609 pinctrl-names = "default", "sleep";
611 /* Common for sleep and wake, but no owners */
620 /* Common for sleep and wake, but no owners */
629 /* Add this for sdmmc pins to SD card */
630 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
631 drive-strength = <8>;
634 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
636 drive-strength = <8>;
639 pcfg_output_high: pcfg-output-high {
643 pcfg_output_low: pcfg-output-low {
649 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
654 pwr_key_h: pwr-key-h {
655 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
661 rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
663 int_codec: int-codec {
664 rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
667 rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
672 emmc_reset: emmc-reset {
673 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
677 * We run eMMC at max speed; bump up drive strength.
678 * We also have external pulls, so disable the internal ones.
681 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
685 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
688 emmc_bus8: emmc-bus8 {
689 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
690 <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
691 <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
692 <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
693 <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
694 <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
695 <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
696 <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
701 ts3a227e_int_l: ts3a227e-int-l {
702 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
707 pmic_int_l: pmic-int-l {
709 * Causes jerry to hang when probing bus 0
710 * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
716 ap_warm_reset_h: ap-warm-reset-h {
717 rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
722 wifi_enable_h: wifienable-h {
723 rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
726 /* NOTE: mislabelled on schematic; should be bt_enable_h */
727 bt_enable_l: bt-enable-l {
728 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
732 * We run sdio0 at max speed; bump up drive strength.
733 * We also have external pulls, so disable the internal ones.
735 sdio0_bus4: sdio0-bus4 {
736 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
737 <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
738 <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
739 <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
742 sdio0_cmd: sdio0-cmd {
743 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
746 sdio0_clk: sdio0-clk {
747 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
751 * These pins are only present on very new veyron boards; on
752 * older boards bt_dev_wake is simply always high. Note that
753 * gpio4_26 is a NC on old veyron boards, so it doesn't hurt
754 * to map this pin everywhere
756 bt_dev_wake_sleep: bt-dev-wake-sleep {
757 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
760 bt_dev_wake_awake: bt-dev-wake-awake {
761 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
767 * We run sdmmc at max speed; bump up drive strength.
768 * We also have external pulls, so disable the internal ones.
770 sdmmc_bus4: sdmmc-bus4 {
771 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
772 <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
773 <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
774 <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
777 sdmmc_clk: sdmmc-clk {
778 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
781 sdmmc_cmd: sdmmc-cmd {
782 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
786 * Builtin CD line is hooked to ground to prevent JTAG at boot
787 * (and also to get the voltage rail correct). Make we
788 * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
789 * think there's a card inserted
791 sdmmc_cd_disabled: sdmmc-cd-disabled {
792 rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
795 /* This is where we actually hook up CD */
796 sdmmc_cd_gpio: sdmmc-cd-gpio {
797 rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
802 tpm_int_h: tpm-int-h {
803 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
809 rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
820 needs-reset-on-resume;
830 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
831 assigned-clock-parents = <&cru SCLK_OTGPHY0>;