1 // SPDX-License-Identifier: GPL-2.0
3 * Google Veyron Jerry Rev 3+ board device tree source
5 * Copyright 2014 Google, Inc
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "cros-ec-sbs.dtsi"
13 model = "Google Jerry";
14 compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
15 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
16 "google,veyron-jerry-rev3", "google,veyron-jerry",
17 "google,veyron", "rockchip,rk3288";
23 panel_regulator: panel-regulator {
24 compatible = "regulator-fixed";
26 gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
27 pinctrl-names = "default";
28 pinctrl-0 = <&lcd_enable_h>;
29 regulator-name = "panel_regulator";
30 vin-supply = <&vcc33_sys>;
33 vcc18_lcd: vcc18-lcd {
34 compatible = "regulator-fixed";
36 gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
37 pinctrl-names = "default";
38 pinctrl-0 = <&avdd_1v8_disp_en>;
39 regulator-name = "vcc18_lcd";
42 vin-supply = <&vcc18_wl>;
45 backlight_regulator: backlight-regulator {
46 compatible = "regulator-fixed";
48 gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
49 pinctrl-names = "default";
50 pinctrl-0 = <&bl_pwr_en>;
51 regulator-name = "backlight_regulator";
52 vin-supply = <&vcc33_sys>;
53 startup-delay-us = <15000>;
57 compatible = "rockchip,audio-max98090-jerry";
64 sound-dai = <&max98090 0>;
70 rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
71 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
72 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
73 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
75 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
77 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
82 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
87 power-supply = <&backlight_regulator>;
91 power-supply= <&panel_regulator>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
97 dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
98 <&gpio7 15 GPIO_ACTIVE_HIGH>;
104 regulator-min-microvolt = <1800000>;
105 regulator-max-microvolt = <1800000>;
106 regulator-name = "mic_vcc";
107 regulator-suspend-mem-disabled;
113 pinctrl-names = "default";
114 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
121 gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&drv_5v>;
128 gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&vcc50_hdmi_en>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&edp_hpd>;
140 bl_pwr_en: bl_pwr_en {
141 rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
147 rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
153 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
158 /* Make sure eMMC is not in reset */
159 emmc_deassert_reset: emmc-deassert-reset {
160 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
165 vcc50_hdmi_en: vcc50-hdmi-en {
166 rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
171 lcd_enable_h: lcd-en {
172 rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
175 avdd_1v8_disp_en: avdd-1v8-disp-en {
176 rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
182 rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
186 rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
195 * Trackpad pin control is shared between Elan and Synaptics devices
196 * so we have to pull it up to the bus level.
198 pinctrl-names = "default";
199 pinctrl-0 = <&i2c4_xfer &trackpad_int>;
202 compatible = "elan,i2c_touchpad";
203 interrupt-parent = <&gpio7>;
204 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
206 * Remove the inherited pinctrl settings to avoid clashing
207 * with bus-wide ones.
209 /delete-property/pinctrl-names;
210 /delete-property/pinctrl-0;
212 vcc-supply = <&vcc33_io>;
217 compatible = "hid-over-i2c";
218 interrupt-parent = <&gpio7>;
219 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
221 hid-descr-addr = <0x0020>;
222 vcc-supply = <&vcc33_io>;