1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include "rk3xxx.dtsi"
13 compatible = "rockchip,rk3188";
18 enable-method = "rockchip,rk3066-smp";
22 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
36 clock-latency = <40000>;
37 clocks = <&cru ARMCLK>;
41 compatible = "arm,cortex-a9";
42 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
53 compatible = "arm,cortex-a9";
54 next-level-cache = <&L2>;
60 compatible = "mmio-sram";
61 reg = <0x10080000 0x8000>;
64 ranges = <0 0x10080000 0x8000>;
67 compatible = "rockchip,rk3066-smp-sram";
73 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
74 reg = <0x1011a000 0x2000>;
75 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&i2s0_bus>;
80 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
81 dma-names = "tx", "rx";
82 clock-names = "i2s_hclk", "i2s_clk";
83 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
84 rockchip,playback-channels = <2>;
85 rockchip,capture-channels = <2>;
89 spdif: sound@1011e000 {
90 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
91 reg = <0x1011e000 0x2000>;
92 #sound-dai-cells = <0>;
93 clock-names = "hclk", "mclk";
94 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
97 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
98 pinctrl-names = "default";
99 pinctrl-0 = <&spdif_tx>;
103 cru: clock-controller@20000000 {
104 compatible = "rockchip,rk3188-cru";
105 reg = <0x20000000 0x1000>;
106 rockchip,grf = <&grf>;
112 efuse: efuse@20010000 {
113 compatible = "rockchip,rockchip-efuse";
114 reg = <0x20010000 0x4000>;
115 #address-cells = <1>;
117 clocks = <&cru PCLK_EFUSE>;
118 clock-names = "pclk_efuse";
120 cpu_leakage: cpu_leakage@17 {
125 timer3: timer@2000e000 {
126 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
127 reg = <0x2000e000 0x20>;
128 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
132 compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
133 rockchip,grf = <&grf>;
134 #address-cells = <1>;
138 usbphy0: usb-phy@10c {
141 clocks = <&cru SCLK_OTGPHY0>;
142 clock-names = "phyclk";
146 usbphy1: usb-phy@11c {
149 clocks = <&cru SCLK_OTGPHY1>;
150 clock-names = "phyclk";
156 compatible = "rockchip,rk3188-pinctrl";
157 rockchip,grf = <&grf>;
158 rockchip,pmu = <&pmu>;
160 #address-cells = <1>;
164 gpio0: gpio0@2000a000 {
165 compatible = "rockchip,gpio-bank";
166 reg = <0x2000a000 0x100>;
167 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&cru PCLK_GPIO0>;
173 interrupt-controller;
174 #interrupt-cells = <2>;
177 gpio1: gpio1@2003c000 {
178 compatible = "rockchip,gpio-bank";
179 reg = <0x2003c000 0x100>;
180 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&cru PCLK_GPIO1>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
190 gpio2: gpio2@2003e000 {
191 compatible = "rockchip,gpio-bank";
192 reg = <0x2003e000 0x100>;
193 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&cru PCLK_GPIO2>;
199 interrupt-controller;
200 #interrupt-cells = <2>;
203 gpio3: gpio3@20080000 {
204 compatible = "rockchip,gpio-bank";
205 reg = <0x20080000 0x100>;
206 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&cru PCLK_GPIO3>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
216 pcfg_pull_up: pcfg_pull_up {
220 pcfg_pull_down: pcfg_pull_down {
224 pcfg_pull_none: pcfg_pull_none {
230 rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
234 rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
238 rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
242 * The data pins are shared between nandc and emmc and
243 * not accessible through pinctrl. Also they should've
244 * been already set correctly by firmware, as
245 * flash/emmc is the boot-device.
250 emac_xfer: emac-xfer {
251 rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
252 <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
253 <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
254 <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
255 <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
256 <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
257 <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
258 <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
261 emac_mdio: emac-mdio {
262 rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
263 <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
268 i2c0_xfer: i2c0-xfer {
269 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
270 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
275 i2c1_xfer: i2c1-xfer {
276 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
277 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
282 i2c2_xfer: i2c2-xfer {
283 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
284 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
289 i2c3_xfer: i2c3-xfer {
290 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
291 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
296 i2c4_xfer: i2c4-xfer {
297 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
298 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
304 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
310 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
316 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
322 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
328 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
331 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
334 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
337 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
340 rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
346 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
349 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
352 rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
355 rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
358 rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
363 uart0_xfer: uart0-xfer {
364 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
365 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
368 uart0_cts: uart0-cts {
369 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
372 uart0_rts: uart0-rts {
373 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
378 uart1_xfer: uart1-xfer {
379 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
380 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
383 uart1_cts: uart1-cts {
384 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
387 uart1_rts: uart1-rts {
388 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
393 uart2_xfer: uart2-xfer {
394 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
395 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
397 /* no rts / cts for uart2 */
401 uart3_xfer: uart3-xfer {
402 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
403 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
406 uart3_cts: uart3-cts {
407 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
410 uart3_rts: uart3-rts {
411 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
417 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
421 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
425 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
429 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
433 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
436 sd0_bus1: sd0-bus-width1 {
437 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
440 sd0_bus4: sd0-bus-width4 {
441 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
442 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
443 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
444 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
450 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
454 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
458 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
462 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
465 sd1_bus1: sd1-bus-width1 {
466 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
469 sd1_bus4: sd1-bus-width4 {
470 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
471 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
472 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
473 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
479 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
480 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
481 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
482 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
483 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
484 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
490 rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
497 compatible = "rockchip,rk3188-emac";
501 interrupts = <GIC_PPI 11 0xf04>;
505 compatible = "rockchip,rk3188-grf", "syscon";
509 interrupts = <GIC_PPI 13 0xf04>;
513 compatible = "rockchip,rk3188-i2c";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c0_xfer>;
519 compatible = "rockchip,rk3188-i2c";
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c1_xfer>;
525 compatible = "rockchip,rk3188-i2c";
526 pinctrl-names = "default";
527 pinctrl-0 = <&i2c2_xfer>;
531 compatible = "rockchip,rk3188-i2c";
532 pinctrl-names = "default";
533 pinctrl-0 = <&i2c3_xfer>;
537 compatible = "rockchip,rk3188-i2c";
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c4_xfer>;
543 compatible = "rockchip,rk3188-pmu", "syscon";
547 pinctrl-names = "default";
548 pinctrl-0 = <&pwm0_out>;
552 pinctrl-names = "default";
553 pinctrl-0 = <&pwm1_out>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&pwm2_out>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pwm3_out>;
567 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
568 pinctrl-names = "default";
569 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
573 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
574 pinctrl-names = "default";
575 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
579 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
580 pinctrl-names = "default";
581 pinctrl-0 = <&uart0_xfer>;
585 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
586 pinctrl-names = "default";
587 pinctrl-0 = <&uart1_xfer>;
591 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
592 pinctrl-names = "default";
593 pinctrl-0 = <&uart2_xfer>;
597 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
598 pinctrl-names = "default";
599 pinctrl-0 = <&uart3_xfer>;
603 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";