1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include "skeleton.dtsi"
11 compatible = "rockchip,rk3036";
13 interrupt-parent = <&gic>;
28 device_type = "memory";
29 reg = <0x60000000 0x40000000>;
33 compatible = "arm,cortex-a7-pmu";
34 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
35 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
36 interrupt-affinity = <&cpu0>, <&cpu1>;
42 enable-method = "rockchip,rk3036-smp";
46 compatible = "arm,cortex-a7";
52 #cooling-cells = <2>; /* min followed by max */
53 clock-latency = <40000>;
54 clocks = <&cru ARMCLK>;
55 resets = <&cru SRST_CORE0>;
59 compatible = "arm,cortex-a7";
61 resets = <&cru SRST_CORE1>;
66 compatible = "arm,amba-bus";
72 compatible = "arm,pl330", "arm,primecell";
73 reg = <0x20078000 0x4000>;
74 arm,pl330-broken-no-flushp;
75 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&cru ACLK_DMAC2>;
79 clock-names = "apb_pclk";
84 compatible = "fixed-clock";
85 clock-frequency = <24000000>;
86 clock-output-names = "xin24m";
91 compatible = "arm,armv7-timer";
92 arm,cpu-registers-not-fw-configured;
93 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
94 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
95 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
96 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
97 clock-frequency = <24000000>;
100 cru: clock-controller@20000000 {
101 compatible = "rockchip,rk3036-cru";
102 reg = <0x20000000 0x1000>;
103 rockchip,grf = <&grf>;
106 assigned-clocks = <&cru PLL_GPLL>;
107 assigned-clock-rates = <594000000>;
110 uart0: serial@20060000 {
111 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
112 reg = <0x20060000 0x100>;
113 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
116 clock-frequency = <24000000>;
117 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
118 clock-names = "baudclk", "apb_pclk";
119 pinctrl-names = "default";
120 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
123 uart1: serial@20064000 {
124 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
125 reg = <0x20064000 0x100>;
126 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
129 clock-frequency = <24000000>;
130 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
131 clock-names = "baudclk", "apb_pclk";
132 pinctrl-names = "default";
133 pinctrl-0 = <&uart1_xfer>;
136 uart2: serial@20068000 {
137 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
138 reg = <0x20068000 0x100>;
139 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
142 clock-frequency = <24000000>;
143 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
144 clock-names = "baudclk", "apb_pclk";
145 pinctrl-names = "default";
146 pinctrl-0 = <&uart2_xfer>;
150 compatible = "rockchip,rk2928-pwm";
151 reg = <0x20050000 0x10>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pwm0_pin>;
155 clocks = <&cru PCLK_PWM>;
161 compatible = "rockchip,rk2928-pwm";
162 reg = <0x20050010 0x10>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pwm1_pin>;
166 clocks = <&cru PCLK_PWM>;
172 compatible = "rockchip,rk2928-pwm";
173 reg = <0x20050020 0x10>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pwm2_pin>;
177 clocks = <&cru PCLK_PWM>;
183 compatible = "rockchip,rk2928-pwm";
184 reg = <0x20050030 0x10>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pwm3_pin>;
188 clocks = <&cru PCLK_PWM>;
193 sram: sram@10080000 {
194 compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
195 reg = <0x10080000 0x2000>;
198 gic: interrupt-controller@10139000 {
199 compatible = "arm,gic-400";
200 interrupt-controller;
201 #interrupt-cells = <3>;
202 #address-cells = <0>;
204 reg = <0x10139000 0x1000>,
208 interrupts = <GIC_PPI 9 0xf04>;
211 grf: syscon@20008000 {
212 compatible = "rockchip,rk3036-grf", "syscon";
213 reg = <0x20008000 0x1000>;
216 usb_otg: usb@10180000 {
217 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
219 reg = <0x10180000 0x40000>;
220 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cru HCLK_OTG0>;
224 g-np-tx-fifo-size = <16>;
225 g-rx-fifo-size = <275>;
226 g-tx-fifo-size = <256 128 128 64 64 32>;
231 usb_host: usb@101c0000 {
232 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
234 reg = <0x101c0000 0x40000>;
235 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&cru HCLK_OTG1>;
242 emmc: dwmmc@1021c000 {
243 compatible = "rockchip,rk3288-dw-mshc";
244 clock-frequency = <37500000>;
245 max-frequency = <37500000>;
246 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
247 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
248 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
251 fifo-depth = <0x100>;
252 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
253 reg = <0x1021c000 0x4000>;
262 default-sample-phase = <158>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
267 sdmmc: dwmmc@10214000 {
268 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
269 reg = <0x10214000 0x4000>;
270 clock-frequency = <37500000>;
271 max-frequency = <37500000>;
272 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
273 clock-names = "biu", "ciu";
274 fifo-depth = <0x100>;
275 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
280 compatible = "rockchip,rk3036-pinctrl";
281 rockchip,grf = <&grf>;
282 #address-cells = <1>;
286 gpio0: gpio0@2007c000 {
287 compatible = "rockchip,gpio-bank";
288 reg = <0x2007c000 0x100>;
289 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&cru PCLK_GPIO0>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
299 gpio1: gpio1@20080000 {
300 compatible = "rockchip,gpio-bank";
301 reg = <0x20080000 0x100>;
302 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&cru PCLK_GPIO1>;
308 interrupt-controller;
309 #interrupt-cells = <2>;
312 gpio2: gpio2@20084000 {
313 compatible = "rockchip,gpio-bank";
314 reg = <0x20084000 0x100>;
315 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&cru PCLK_GPIO2>;
321 interrupt-controller;
322 #interrupt-cells = <2>;
325 pcfg_pull_up: pcfg-pull-up {
329 pcfg_pull_down: pcfg-pull-down {
333 pcfg_pull_none: pcfg-pull-none {
339 * We run eMMC at max speed; bump up drive strength.
340 * We also have external pulls, so disable the internal ones.
343 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
347 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
350 emmc_bus8: emmc-bus8 {
351 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
352 <1 25 RK_FUNC_2 &pcfg_pull_none>,
353 <1 26 RK_FUNC_2 &pcfg_pull_none>,
354 <1 27 RK_FUNC_2 &pcfg_pull_none>;
356 <1 28 RK_FUNC_2 &pcfg_pull_up>,
357 <1 29 RK_FUNC_2 &pcfg_pull_up>,
358 <1 30 RK_FUNC_2 &pcfg_pull_up>,
359 <1 31 RK_FUNC_2 &pcfg_pull_up>;
365 uart0_xfer: uart0-xfer {
366 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
367 <0 17 RK_FUNC_1 &pcfg_pull_none>;
370 uart0_cts: uart0-cts {
371 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
374 uart0_rts: uart0-rts {
375 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
380 uart1_xfer: uart1-xfer {
381 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
382 <2 23 RK_FUNC_1 &pcfg_pull_none>;
384 /* no rts / cts for uart1 */
388 uart2_xfer: uart2-xfer {
389 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
390 <1 19 RK_FUNC_2 &pcfg_pull_none>;
392 /* no rts / cts for uart2 */
397 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
403 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
409 rockchip,pins = <0 1 2 &pcfg_pull_none>;
415 rockchip,pins = <0 27 1 &pcfg_pull_none>;
420 i2c1_xfer: i2c1-xfer {
421 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
422 <0 3 RK_FUNC_1 &pcfg_pull_none>;
428 compatible = "rockchip,rk3288-i2c";
429 reg = <0x20056000 0x1000>;
430 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
434 clocks = <&cru PCLK_I2C1>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&i2c1_xfer>;