arch/arm/dts/r8a77970.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a77970 SoC
   4  *
   5  * Copyright (C) 2016-2017 Renesas Electronics Corp.
   6  * Copyright (C) 2017 Cogent Embedded, Inc.
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  12
  13 / {
  14         compatible = "renesas,r8a77970";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         psci {
  19                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  20                 method = "smc";
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 a53_0: cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a53", "arm,armv8";
  30                         reg = <0>;
  31                         clocks = <&cpg CPG_CORE 0>;
  32                         power-domains = <&sysc 5>;
  33                         next-level-cache = <&L2_CA53>;
  34                         enable-method = "psci";
  35                 };
  36
  37                 L2_CA53: cache-controller {
  38                         compatible = "cache";
  39                         power-domains = <&sysc 21>;
  40                         cache-unified;
  41                         cache-level = <2>;
  42                 };
  43         };
  44
  45         extal_clk: extal {
  46                 compatible = "fixed-clock";
  47                 #clock-cells = <0>;
  48                 /* This value must be overridden by the board */
  49                 clock-frequency = <0>;
  50         };
  51
  52         extalr_clk: extalr {
  53                 compatible = "fixed-clock";
  54                 #clock-cells = <0>;
  55                 /* This value must be overridden by the board */
  56                 clock-frequency = <0>;
  57         };
  58
  59         /* External SCIF clock - to be overridden by boards that provide it */
  60         scif_clk: scif {
  61                 compatible = "fixed-clock";
  62                 #clock-cells = <0>;
  63                 clock-frequency = <0>;
  64         };
  65
  66         soc {
  67                 compatible = "simple-bus";
  68                 interrupt-parent = <&gic>;
  69
  70                 #address-cells = <2>;
  71                 #size-cells = <2>;
  72                 ranges;
  73
  74                 gic: interrupt-controller@f1010000 {
  75                         compatible = "arm,gic-400";
  76                         #interrupt-cells = <3>;
  77                         #address-cells = <0>;
  78                         interrupt-controller;
  79                         reg = <0 0xf1010000 0 0x1000>,
  80                               <0 0xf1020000 0 0x20000>,
  81                               <0 0xf1040000 0 0x20000>,
  82                               <0 0xf1060000 0 0x20000>;
  83                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
  84                                       IRQ_TYPE_LEVEL_HIGH)>;
  85                         clocks = <&cpg CPG_MOD 408>;
  86                         clock-names = "clk";
  87                         power-domains = <&sysc 32>;
  88                         resets = <&cpg 408>;
  89                 };
  90
  91                 timer {
  92                         compatible = "arm,armv8-timer";
  93                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
  94                                                   IRQ_TYPE_LEVEL_LOW)>,
  95                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
  96                                                   IRQ_TYPE_LEVEL_LOW)>,
  97                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
  98                                                   IRQ_TYPE_LEVEL_LOW)>,
  99                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
 100                                                   IRQ_TYPE_LEVEL_LOW)>;
 101                 };
 102
 103                 cpg: clock-controller@e6150000 {
 104                         compatible = "renesas,r8a77970-cpg-mssr";
 105                         reg = <0 0xe6150000 0 0x1000>;
 106                         clocks = <&extal_clk>, <&extalr_clk>;
 107                         clock-names = "extal", "extalr";
 108                         #clock-cells = <2>;
 109                         #power-domain-cells = <0>;
 110                         #reset-cells = <1>;
 111                 };
 112
 113                 rst: reset-controller@e6160000 {
 114                         compatible = "renesas,r8a77970-rst";
 115                         reg = <0 0xe6160000 0 0x200>;
 116                 };
 117
 118                 sysc: system-controller@e6180000 {
 119                         compatible = "renesas,r8a77970-sysc";
 120                         reg = <0 0xe6180000 0 0x440>;
 121                         #power-domain-cells = <1>;
 122                 };
 123
 124                 pfc: pfc@e6060000 {
 125                         compatible = "renesas,pfc-r8a77970";
 126                         reg = <0 0xe6060000 0 0x50c>;
 127                 };
 128
 129                 intc_ex: interrupt-controller@e61c0000 {
 130                         compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
 131                         #interrupt-cells = <2>;
 132                         interrupt-controller;
 133                         reg = <0 0xe61c0000 0 0x200>;
 134                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 135                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 136                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 137                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 138                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 139                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 140                         clocks = <&cpg CPG_MOD 407>;
 141                         power-domains = <&sysc 32>;
 142                         resets = <&cpg 407>;
 143                 };
 144
 145                 prr: chipid@fff00044 {
 146                         compatible = "renesas,prr";
 147                         reg = <0 0xfff00044 0 4>;
 148                 };
 149
 150                 dmac1: dma-controller@e7300000 {
 151                         compatible = "renesas,dmac-r8a77970",
 152                                      "renesas,rcar-dmac";
 153                         reg = <0 0xe7300000 0 0x10000>;
 154                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 155                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 156                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 157                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 158                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 159                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 160                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 161                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 162                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
 163                         interrupt-names = "error",
 164                                           "ch0", "ch1", "ch2", "ch3",
 165                                           "ch4", "ch5", "ch6", "ch7";
 166                         clocks = <&cpg CPG_MOD 218>;
 167                         clock-names = "fck";
 168                         power-domains = <&sysc 32>;
 169                         resets = <&cpg 218>;
 170                         #dma-cells = <1>;
 171                         dma-channels = <8>;
 172                 };
 173
 174                 dmac2: dma-controller@e7310000 {
 175                         compatible = "renesas,dmac-r8a77970",
 176                                      "renesas,rcar-dmac";
 177                         reg = <0 0xe7310000 0 0x10000>;
 178                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
 179                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 180                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 181                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 182                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 183                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 184                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 185                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 186                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 187                         interrupt-names = "error",
 188                                           "ch0", "ch1", "ch2", "ch3",
 189                                           "ch4", "ch5", "ch6", "ch7";
 190                         clocks = <&cpg CPG_MOD 217>;
 191                         clock-names = "fck";
 192                         power-domains = <&sysc 32>;
 193                         resets = <&cpg 217>;
 194                         #dma-cells = <1>;
 195                         dma-channels = <8>;
 196                 };
 197
 198                 hscif0: serial@e6540000 {
 199                         compatible = "renesas,hscif-r8a77970",
 200                                      "renesas,rcar-gen3-hscif",
 201                                      "renesas,hscif";
 202                         reg = <0 0xe6540000 0 96>;
 203                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 204                         clocks = <&cpg CPG_MOD 520>,
 205                                  <&cpg CPG_CORE 9>,
 206                                  <&scif_clk>;
 207                         clock-names = "fck", "brg_int", "scif_clk";
 208                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 209                                <&dmac2 0x31>, <&dmac2 0x30>;
 210                         dma-names = "tx", "rx", "tx", "rx";
 211                         power-domains = <&sysc 32>;
 212                         resets = <&cpg 520>;
 213                         status = "disabled";
 214                 };
 215
 216                 hscif1: serial@e6550000 {
 217                         compatible = "renesas,hscif-r8a77970",
 218                                      "renesas,rcar-gen3-hscif",
 219                                      "renesas,hscif";
 220                         reg = <0 0xe6550000 0 96>;
 221                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 222                         clocks = <&cpg CPG_MOD 519>,
 223                                  <&cpg CPG_CORE 9>,
 224                                  <&scif_clk>;
 225                         clock-names = "fck", "brg_int", "scif_clk";
 226                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 227                                <&dmac2 0x33>, <&dmac2 0x32>;
 228                         dma-names = "tx", "rx", "tx", "rx";
 229                         power-domains = <&sysc 32>;
 230                         resets = <&cpg 519>;
 231                         status = "disabled";
 232                 };
 233
 234                 hscif2: serial@e6560000 {
 235                         compatible = "renesas,hscif-r8a77970",
 236                                      "renesas,rcar-gen3-hscif",
 237                                      "renesas,hscif";
 238                         reg = <0 0xe6560000 0 96>;
 239                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 240                         clocks = <&cpg CPG_MOD 518>,
 241                                  <&cpg CPG_CORE 9>,
 242                                  <&scif_clk>;
 243                         clock-names = "fck", "brg_int", "scif_clk";
 244                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 245                                <&dmac2 0x35>, <&dmac2 0x34>;
 246                         dma-names = "tx", "rx", "tx", "rx";
 247                         power-domains = <&sysc 32>;
 248                         resets = <&cpg 518>;
 249                         status = "disabled";
 250                 };
 251
 252                 hscif3: serial@e66a0000 {
 253                         compatible = "renesas,hscif-r8a77970",
 254                                      "renesas,rcar-gen3-hscif", "renesas,hscif";
 255                         reg = <0 0xe66a0000 0 96>;
 256                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&cpg CPG_MOD 517>,
 258                                  <&cpg CPG_CORE 9>,
 259                                  <&scif_clk>;
 260                         clock-names = "fck", "brg_int", "scif_clk";
 261                         dmas = <&dmac1 0x37>, <&dmac1 0x36>,
 262                                <&dmac2 0x37>, <&dmac2 0x36>;
 263                         dma-names = "tx", "rx", "tx", "rx";
 264                         power-domains = <&sysc 32>;
 265                         resets = <&cpg 517>;
 266                         status = "disabled";
 267                 };
 268
 269                 scif0: serial@e6e60000 {
 270                         compatible = "renesas,scif-r8a77970",
 271                                      "renesas,rcar-gen3-scif",
 272                                      "renesas,scif";
 273                         reg = <0 0xe6e60000 0 64>;
 274                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&cpg CPG_MOD 207>,
 276                                  <&cpg CPG_CORE 9>,
 277                                  <&scif_clk>;
 278                         clock-names = "fck", "brg_int", "scif_clk";
 279                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 280                                <&dmac2 0x51>, <&dmac2 0x50>;
 281                         dma-names = "tx", "rx", "tx", "rx";
 282                         power-domains = <&sysc 32>;
 283                         resets = <&cpg 207>;
 284                         status = "disabled";
 285                 };
 286
 287                 scif1: serial@e6e68000 {
 288                         compatible = "renesas,scif-r8a77970",
 289                                      "renesas,rcar-gen3-scif",
 290                                      "renesas,scif";
 291                         reg = <0 0xe6e68000 0 64>;
 292                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 293                         clocks = <&cpg CPG_MOD 206>,
 294                                  <&cpg CPG_CORE 9>,
 295                                  <&scif_clk>;
 296                         clock-names = "fck", "brg_int", "scif_clk";
 297                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 298                                <&dmac2 0x53>, <&dmac2 0x52>;
 299                         dma-names = "tx", "rx", "tx", "rx";
 300                         power-domains = <&sysc 32>;
 301                         resets = <&cpg 206>;
 302                         status = "disabled";
 303                 };
 304
 305                 scif3: serial@e6c50000 {
 306                         compatible = "renesas,scif-r8a77970",
 307                                      "renesas,rcar-gen3-scif",
 308                                      "renesas,scif";
 309                         reg = <0 0xe6c50000 0 64>;
 310                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 311                         clocks = <&cpg CPG_MOD 204>,
 312                                  <&cpg CPG_CORE 9>,
 313                                  <&scif_clk>;
 314                         clock-names = "fck", "brg_int", "scif_clk";
 315                         dmas = <&dmac1 0x57>, <&dmac1 0x56>,
 316                                <&dmac2 0x57>, <&dmac2 0x56>;
 317                         dma-names = "tx", "rx", "tx", "rx";
 318                         power-domains = <&sysc 32>;
 319                         resets = <&cpg 204>;
 320                         status = "disabled";
 321                 };
 322
 323                 scif4: serial@e6c40000 {
 324                         compatible = "renesas,scif-r8a77970",
 325                                      "renesas,rcar-gen3-scif", "renesas,scif";
 326                         reg = <0 0xe6c40000 0 64>;
 327                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 328                         clocks = <&cpg CPG_MOD 203>,
 329                                  <&cpg CPG_CORE 9>,
 330                                  <&scif_clk>;
 331                         clock-names = "fck", "brg_int", "scif_clk";
 332                         dmas = <&dmac1 0x59>, <&dmac1 0x58>,
 333                                <&dmac2 0x59>, <&dmac2 0x58>;
 334                         dma-names = "tx", "rx", "tx", "rx";
 335                         power-domains = <&sysc 32>;
 336                         resets = <&cpg 203>;
 337                         status = "disabled";
 338                 };
 339
 340                 avb: ethernet@e6800000 {
 341                         compatible = "renesas,etheravb-r8a77970",
 342                                      "renesas,etheravb-rcar-gen3";
 343                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 344                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 345                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 346                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 347                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 348                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 349                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 350                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 351                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 352                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 353                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 354                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 355                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 356                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 357                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 358                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 359                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 360                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 361                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 362                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 363                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 364                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 365                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 366                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 367                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 368                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 369                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 370                                           "ch4", "ch5", "ch6", "ch7",
 371                                           "ch8", "ch9", "ch10", "ch11",
 372                                           "ch12", "ch13", "ch14", "ch15",
 373                                           "ch16", "ch17", "ch18", "ch19",
 374                                           "ch20", "ch21", "ch22", "ch23",
 375                                           "ch24";
 376                         clocks = <&cpg CPG_MOD 812>;
 377                         power-domains = <&sysc 32>;
 378                         resets = <&cpg 812>;
 379                         phy-mode = "rgmii-id";
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                 };
 383
 384                 rpc: rpc@0xee200000 {
 385                         compatible = "renesas,rpc-r8a77970", "renesas,rpc";
 386                         reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
 387                         clocks = <&cpg CPG_MOD 917>;
 388                         bank-width = <2>;
 389                         status = "disabled";
 390                 };
 391         };
 392 };