Merge git://git.denx.de/u-boot-spi
[oweals/u-boot.git] / arch / arm / dts / r8a77970-eagle.dts
1 /*
2  * Device Tree Source for the Eagle board
3  *
4  * Copyright (C) 2016-2017 Renesas Electronics Corp.
5  * Copyright (C) 2017 Cogent Embedded, Inc.
6  *
7  * SPDX-License-Identifier:     GPL-2.0
8  */
9
10 /dts-v1/;
11 #include "r8a77970.dtsi"
12
13 / {
14         model = "Renesas Eagle board based on r8a77970";
15         compatible = "renesas,eagle", "renesas,r8a77970";
16
17         aliases {
18                 serial0 = &scif0;
19                 ethernet0 = &avb;
20                 spi0 = &rpc;
21         };
22
23         chosen {
24                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
25                 stdout-path = "serial0:115200n8";
26         };
27
28         memory@48000000 {
29                 device_type = "memory";
30                 /* first 128MB is reserved for secure area. */
31                 reg = <0x0 0x48000000 0x0 0x38000000>;
32         };
33 };
34
35 &extal_clk {
36         clock-frequency = <16666666>;
37 };
38
39 &extalr_clk {
40         clock-frequency = <32768>;
41 };
42
43 &pfc {
44         pinctrl-0 = <&scif_clk_pins>;
45         pinctrl-names = "default";
46
47         scif0_pins: scif0 {
48                 groups = "scif0_data";
49                 function = "scif0";
50         };
51
52         scif_clk_pins: scif_clk {
53                 groups = "scif_clk_b";
54                 function = "scif_clk";
55         };
56
57         avb_pins: avb {
58                 groups = "avb0_mdc";
59                 function = "avb0";
60         };
61 };
62
63 &rpc {
64         num-cs = <1>;
65         status = "okay";
66         spi-max-frequency = <50000000>;
67         #address-cells = <1>;
68         #size-cells = <0>;
69
70         flash0: spi-flash@0 {
71                 #address-cells = <1>;
72                 #size-cells = <1>;
73                 compatible = "s25fs512s", "spi-flash", "jedec,spi-nor";
74                 spi-max-frequency = <50000000>;
75                 spi-tx-bus-width = <1>;
76                 spi-rx-bus-width = <1>;
77                 reg = <0>;
78                 status = "okay";
79         };
80 };
81
82 &scif0 {
83         pinctrl-0 = <&scif0_pins>;
84         pinctrl-names = "default";
85
86         status = "okay";
87 };
88
89 &scif_clk {
90         clock-frequency = <14745600>;
91         status = "okay";
92 };
93
94 &avb {
95         pinctrl-0 = <&avb_pins>;
96         pinctrl-names = "default";
97         renesas,no-ether-link;
98         phy-handle = <&phy0>;
99         status = "okay";
100
101         phy0: ethernet-phy@0 {
102                 rxc-skew-ps = <1500>;
103                 reg = <0>;
104         };
105 };