arch/arm/dts/r8a7794-alt.dts

   1 /*
   2  * Device Tree Source for the Alt board
   3  *
   4  * Copyright (C) 2014 Renesas Electronics Corporation
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0
   7  */
   8
   9 /dts-v1/;
  10 #include "r8a7794.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "Alt";
  15         compatible = "renesas,alt", "renesas,r8a7794";
  16
  17         aliases {
  18                 serial0 = &scif2;
  19                 i2c10 = &gpioi2c4;
  20                 i2c12 = &i2cexio4;
  21         };
  22
  23         chosen {
  24                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  25                 stdout-path = "serial0:115200n8";
  26         };
  27
  28         memory@40000000 {
  29                 device_type = "memory";
  30                 reg = <0 0x40000000 0 0x40000000>;
  31         };
  32
  33         d3_3v: regulator-d3-3v {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "D3.3V";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 regulator-boot-on;
  39                 regulator-always-on;
  40         };
  41
  42         vcc_sdhi0: regulator-vcc-sdhi0 {
  43                 compatible = "regulator-fixed";
  44
  45                 regulator-name = "SDHI0 Vcc";
  46                 regulator-min-microvolt = <3300000>;
  47                 regulator-max-microvolt = <3300000>;
  48
  49                 gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
  50                 enable-active-high;
  51         };
  52
  53         vccq_sdhi0: regulator-vccq-sdhi0 {
  54                 compatible = "regulator-gpio";
  55
  56                 regulator-name = "SDHI0 VccQ";
  57                 regulator-min-microvolt = <1800000>;
  58                 regulator-max-microvolt = <3300000>;
  59
  60                 gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
  61                 gpios-states = <1>;
  62                 states = <3300000 1
  63                           1800000 0>;
  64         };
  65
  66         vcc_sdhi1: regulator-vcc-sdhi1 {
  67                 compatible = "regulator-fixed";
  68
  69                 regulator-name = "SDHI1 Vcc";
  70                 regulator-min-microvolt = <3300000>;
  71                 regulator-max-microvolt = <3300000>;
  72
  73                 gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
  74                 enable-active-high;
  75         };
  76
  77         vccq_sdhi1: regulator-vccq-sdhi1 {
  78                 compatible = "regulator-gpio";
  79
  80                 regulator-name = "SDHI1 VccQ";
  81                 regulator-min-microvolt = <1800000>;
  82                 regulator-max-microvolt = <3300000>;
  83
  84                 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
  85                 gpios-states = <1>;
  86                 states = <3300000 1
  87                           1800000 0>;
  88         };
  89
  90         lbsc {
  91                 #address-cells = <1>;
  92                 #size-cells = <1>;
  93         };
  94
  95         vga-encoder {
  96                 compatible = "adi,adv7123";
  97
  98                 ports {
  99                         #address-cells = <1>;
 100                         #size-cells = <0>;
 101
 102                         port@0 {
 103                                 reg = <0>;
 104                                 adv7123_in: endpoint {
 105                                         remote-endpoint = <&du_out_rgb1>;
 106                                 };
 107                         };
 108                         port@1 {
 109                                 reg = <1>;
 110                                 adv7123_out: endpoint {
 111                                         remote-endpoint = <&vga_in>;
 112                                 };
 113                         };
 114                 };
 115         };
 116
 117         vga {
 118                 compatible = "vga-connector";
 119
 120                 port {
 121                         vga_in: endpoint {
 122                                 remote-endpoint = <&adv7123_out>;
 123                         };
 124                 };
 125         };
 126
 127         x2_clk: x2-clock {
 128                 compatible = "fixed-clock";
 129                 #clock-cells = <0>;
 130                 clock-frequency = <74250000>;
 131         };
 132
 133         x13_clk: x13-clock {
 134                 compatible = "fixed-clock";
 135                 #clock-cells = <0>;
 136                 clock-frequency = <148500000>;
 137         };
 138
 139         gpioi2c4: i2c-10 {
 140                 #address-cells = <1>;
 141                 #size-cells = <0>;
 142                 compatible = "i2c-gpio";
 143                 status = "disabled";
 144                 gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
 145                          &gpio4 8 GPIO_ACTIVE_HIGH /* scl */
 146                         >;
 147                 i2c-gpio,delay-us = <5>;
 148         };
 149
 150         /*
 151          * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
 152          * A fallback to GPIO is provided.
 153          */
 154         i2cexio4: i2c-14 {
 155                 compatible = "i2c-demux-pinctrl";
 156                 i2c-parent = <&i2c4>, <&gpioi2c4>;
 157                 i2c-bus-name = "i2c-exio4";
 158                 #address-cells = <1>;
 159                 #size-cells = <0>;
 160         };
 161 };
 162
 163 &du {
 164         pinctrl-0 = <&du_pins>;
 165         pinctrl-names = "default";
 166         status = "okay";
 167
 168         clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
 169                  <&x13_clk>, <&x2_clk>;
 170         clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
 171
 172         ports {
 173                 port@1 {
 174                         endpoint {
 175                                 remote-endpoint = <&adv7123_in>;
 176                         };
 177                 };
 178         };
 179 };
 180
 181 &extal_clk {
 182         clock-frequency = <20000000>;
 183 };
 184
 185 &pfc {
 186         pinctrl-0 = <&scif_clk_pins>;
 187         pinctrl-names = "default";
 188
 189         du_pins: du {
 190                 groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
 191                 function = "du1";
 192         };
 193
 194         scif2_pins: scif2 {
 195                 groups = "scif2_data";
 196                 function = "scif2";
 197         };
 198
 199         scif_clk_pins: scif_clk {
 200                 groups = "scif_clk";
 201                 function = "scif_clk";
 202         };
 203
 204         ether_pins: ether {
 205                 groups = "eth_link", "eth_mdio", "eth_rmii";
 206                 function = "eth";
 207         };
 208
 209         phy1_pins: phy1 {
 210                 groups = "intc_irq8";
 211                 function = "intc";
 212         };
 213
 214         i2c1_pins: i2c1 {
 215                 groups = "i2c1";
 216                 function = "i2c1";
 217         };
 218
 219         i2c4_pins: i2c4 {
 220                 groups = "i2c4";
 221                 function = "i2c4";
 222         };
 223
 224         vin0_pins: vin0 {
 225                 groups = "vin0_data8", "vin0_clk";
 226                 function = "vin0";
 227         };
 228
 229         mmcif0_pins: mmcif0 {
 230                 groups = "mmc_data8", "mmc_ctrl";
 231                 function = "mmc";
 232         };
 233
 234         sdhi0_pins: sd0 {
 235                 groups = "sdhi0_data4", "sdhi0_ctrl";
 236                 function = "sdhi0";
 237                 power-source = <3300>;
 238         };
 239
 240         sdhi0_pins_uhs: sd0_uhs {
 241                 groups = "sdhi0_data4", "sdhi0_ctrl";
 242                 function = "sdhi0";
 243                 power-source = <1800>;
 244         };
 245
 246         sdhi1_pins: sd1 {
 247                 groups = "sdhi1_data4", "sdhi1_ctrl";
 248                 function = "sdhi1";
 249                 power-source = <3300>;
 250         };
 251
 252         sdhi1_pins_uhs: sd1_uhs {
 253                 groups = "sdhi1_data4", "sdhi1_ctrl";
 254                 function = "sdhi1";
 255                 power-source = <1800>;
 256         };
 257 };
 258
 259 &cmt0 {
 260         status = "okay";
 261 };
 262
 263 &pfc {
 264         qspi_pins: qspi {
 265                 groups = "qspi_ctrl", "qspi_data4";
 266                 function = "qspi";
 267         };
 268 };
 269
 270 &ether {
 271         pinctrl-0 = <&ether_pins &phy1_pins>;
 272         pinctrl-names = "default";
 273
 274         phy-handle = <&phy1>;
 275         renesas,ether-link-active-low;
 276         status = "okay";
 277
 278         phy1: ethernet-phy@1 {
 279                 reg = <1>;
 280                 interrupt-parent = <&irqc0>;
 281                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 282                 micrel,led-mode = <1>;
 283         };
 284 };
 285
 286 &mmcif0 {
 287         pinctrl-0 = <&mmcif0_pins>;
 288         pinctrl-names = "default";
 289
 290         vmmc-supply = <&d3_3v>;
 291         vqmmc-supply = <&d3_3v>;
 292         bus-width = <8>;
 293         non-removable;
 294         status = "okay";
 295 };
 296
 297 &sdhi0 {
 298         pinctrl-0 = <&sdhi0_pins>;
 299         pinctrl-1 = <&sdhi0_pins_uhs>;
 300         pinctrl-names = "default", "state_uhs";
 301
 302         vmmc-supply = <&vcc_sdhi0>;
 303         vqmmc-supply = <&vccq_sdhi0>;
 304         cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
 305         wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
 306         sd-uhs-sdr50;
 307         sd-uhs-sdr104;
 308         status = "okay";
 309 };
 310
 311 &sdhi1 {
 312         pinctrl-0 = <&sdhi1_pins>;
 313         pinctrl-1 = <&sdhi1_pins_uhs>;
 314         pinctrl-names = "default", "state_uhs";
 315
 316         vmmc-supply = <&vcc_sdhi1>;
 317         vqmmc-supply = <&vccq_sdhi1>;
 318         cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
 319         wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
 320         sd-uhs-sdr50;
 321         status = "okay";
 322 };
 323
 324 &i2c1 {
 325         pinctrl-0 = <&i2c1_pins>;
 326         pinctrl-names = "default";
 327
 328         status = "okay";
 329         clock-frequency = <400000>;
 330
 331         composite-in@20 {
 332                 compatible = "adi,adv7180";
 333                 reg = <0x20>;
 334                 remote = <&vin0>;
 335
 336                 port {
 337                         adv7180: endpoint {
 338                                 bus-width = <8>;
 339                                 remote-endpoint = <&vin0ep>;
 340                         };
 341                 };
 342         };
 343 };
 344
 345 &i2c4 {
 346         pinctrl-0 = <&i2c4_pins>;
 347         pinctrl-names = "i2c-exio4";
 348 };
 349
 350 &vin0 {
 351         status = "okay";
 352         pinctrl-0 = <&vin0_pins>;
 353         pinctrl-names = "default";
 354
 355         port {
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358
 359                 vin0ep: endpoint {
 360                         remote-endpoint = <&adv7180>;
 361                         bus-width = <8>;
 362                 };
 363         };
 364 };
 365
 366 &scif2 {
 367         pinctrl-0 = <&scif2_pins>;
 368         pinctrl-names = "default";
 369
 370         status = "okay";
 371 };
 372
 373 &scif_clk {
 374         clock-frequency = <14745600>;
 375 };
 376
 377 &qspi {
 378         pinctrl-0 = <&qspi_pins>;
 379         pinctrl-names = "default";
 380
 381         status = "okay";
 382
 383         flash@0 {
 384                 compatible = "spansion,s25fl512s", "jedec,spi-nor";
 385                 reg = <0>;
 386                 spi-max-frequency = <30000000>;
 387                 spi-tx-bus-width = <4>;
 388                 spi-rx-bus-width = <4>;
 389                 spi-cpol;
 390                 spi-cpha;
 391                 m25p,fast-read;
 392
 393                 partitions {
 394                         compatible = "fixed-partitions";
 395                         #address-cells = <1>;
 396                         #size-cells = <1>;
 397
 398                         partition@0 {
 399                                 label = "loader";
 400                                 reg = <0x00000000 0x00040000>;
 401                                 read-only;
 402                         };
 403                         partition@40000 {
 404                                 label = "system";
 405                                 reg = <0x00040000 0x00040000>;
 406                                 read-only;
 407                         };
 408                         partition@80000 {
 409                                 label = "user";
 410                                 reg = <0x00080000 0x03f80000>;
 411                         };
 412                 };
 413         };
 414 };