arch/arm/dts/r8a7792.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a7792 SoC
   4  *
   5  * Copyright (C) 2016 Cogent Embedded Inc.
   6  */
   7
   8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/power/r8a7792-sysc.h>
  12
  13 / {
  14         compatible = "renesas,r8a7792";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 i2c5 = &i2c5;
  25                 spi0 = &qspi;
  26                 spi1 = &msiof0;
  27                 spi2 = &msiof1;
  28                 vin0 = &vin0;
  29                 vin1 = &vin1;
  30                 vin2 = &vin2;
  31                 vin3 = &vin3;
  32                 vin4 = &vin4;
  33                 vin5 = &vin5;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39                 enable-method = "renesas,apmu";
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0>;
  45                         clock-frequency = <1000000000>;
  46                         clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
  47                         power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
  48                         next-level-cache = <&L2_CA15>;
  49                 };
  50
  51                 cpu1: cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a15";
  54                         reg = <1>;
  55                         clock-frequency = <1000000000>;
  56                         clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
  57                         power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
  58                         next-level-cache = <&L2_CA15>;
  59                 };
  60
  61                 L2_CA15: cache-controller-0 {
  62                         compatible = "cache";
  63                         cache-unified;
  64                         cache-level = <2>;
  65                         power-domains = <&sysc R8A7792_PD_CA15_SCU>;
  66                 };
  67         };
  68
  69         soc {
  70                 compatible = "simple-bus";
  71                 interrupt-parent = <&gic>;
  72
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 apmu@e6152000 {
  78                         compatible = "renesas,r8a7792-apmu", "renesas,apmu";
  79                         reg = <0 0xe6152000 0 0x188>;
  80                         cpus = <&cpu0 &cpu1>;
  81                 };
  82
  83                 gic: interrupt-controller@f1001000 {
  84                         compatible = "arm,gic-400";
  85                         #interrupt-cells = <3>;
  86                         interrupt-controller;
  87                         reg = <0 0xf1001000 0 0x1000>,
  88                               <0 0xf1002000 0 0x2000>,
  89                               <0 0xf1004000 0 0x2000>,
  90                               <0 0xf1006000 0 0x2000>;
  91                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  92                                       IRQ_TYPE_LEVEL_HIGH)>;
  93                         clocks = <&cpg CPG_MOD 408>;
  94                         clock-names = "clk";
  95                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
  96                         resets = <&cpg 408>;
  97                 };
  98
  99                 irqc: interrupt-controller@e61c0000 {
 100                         compatible = "renesas,irqc-r8a7792", "renesas,irqc";
 101                         #interrupt-cells = <2>;
 102                         interrupt-controller;
 103                         reg = <0 0xe61c0000 0 0x200>;
 104                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 105                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 106                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 107                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 108                         clocks = <&cpg CPG_MOD 407>;
 109                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 110                         resets = <&cpg 407>;
 111                 };
 112
 113                 timer {
 114                         compatible = "arm,armv7-timer";
 115                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 116                                       IRQ_TYPE_LEVEL_LOW)>,
 117                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 118                                       IRQ_TYPE_LEVEL_LOW)>,
 119                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 120                                       IRQ_TYPE_LEVEL_LOW)>,
 121                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 122                                       IRQ_TYPE_LEVEL_LOW)>;
 123                 };
 124
 125                 rst: reset-controller@e6160000 {
 126                         compatible = "renesas,r8a7792-rst";
 127                         reg = <0 0xe6160000 0 0x0100>;
 128                 };
 129
 130                 prr: chipid@ff000044 {
 131                         compatible = "renesas,prr";
 132                         reg = <0 0xff000044 0 4>;
 133                 };
 134
 135                 sysc: system-controller@e6180000 {
 136                         compatible = "renesas,r8a7792-sysc";
 137                         reg = <0 0xe6180000 0 0x0200>;
 138                         #power-domain-cells = <1>;
 139                 };
 140
 141                 pfc: pin-controller@e6060000 {
 142                         compatible = "renesas,pfc-r8a7792";
 143                         reg = <0 0xe6060000 0 0x144>;
 144                 };
 145
 146                 gpio0: gpio@e6050000 {
 147                         compatible = "renesas,gpio-r8a7792",
 148                                      "renesas,rcar-gen2-gpio";
 149                         reg = <0 0xe6050000 0 0x50>;
 150                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 151                         #gpio-cells = <2>;
 152                         gpio-controller;
 153                         gpio-ranges = <&pfc 0 0 29>;
 154                         #interrupt-cells = <2>;
 155                         interrupt-controller;
 156                         clocks = <&cpg CPG_MOD 912>;
 157                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 158                         resets = <&cpg 912>;
 159                 };
 160
 161                 gpio1: gpio@e6051000 {
 162                         compatible = "renesas,gpio-r8a7792",
 163                                      "renesas,rcar-gen2-gpio";
 164                         reg = <0 0xe6051000 0 0x50>;
 165                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 166                         #gpio-cells = <2>;
 167                         gpio-controller;
 168                         gpio-ranges = <&pfc 0 32 23>;
 169                         #interrupt-cells = <2>;
 170                         interrupt-controller;
 171                         clocks = <&cpg CPG_MOD 911>;
 172                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 173                         resets = <&cpg 911>;
 174                 };
 175
 176                 gpio2: gpio@e6052000 {
 177                         compatible = "renesas,gpio-r8a7792",
 178                                      "renesas,rcar-gen2-gpio";
 179                         reg = <0 0xe6052000 0 0x50>;
 180                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 181                         #gpio-cells = <2>;
 182                         gpio-controller;
 183                         gpio-ranges = <&pfc 0 64 32>;
 184                         #interrupt-cells = <2>;
 185                         interrupt-controller;
 186                         clocks = <&cpg CPG_MOD 910>;
 187                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 188                         resets = <&cpg 910>;
 189                 };
 190
 191                 gpio3: gpio@e6053000 {
 192                         compatible = "renesas,gpio-r8a7792",
 193                                      "renesas,rcar-gen2-gpio";
 194                         reg = <0 0xe6053000 0 0x50>;
 195                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 196                         #gpio-cells = <2>;
 197                         gpio-controller;
 198                         gpio-ranges = <&pfc 0 96 28>;
 199                         #interrupt-cells = <2>;
 200                         interrupt-controller;
 201                         clocks = <&cpg CPG_MOD 909>;
 202                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 203                         resets = <&cpg 909>;
 204                 };
 205
 206                 gpio4: gpio@e6054000 {
 207                         compatible = "renesas,gpio-r8a7792",
 208                                      "renesas,rcar-gen2-gpio";
 209                         reg = <0 0xe6054000 0 0x50>;
 210                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 211                         #gpio-cells = <2>;
 212                         gpio-controller;
 213                         gpio-ranges = <&pfc 0 128 17>;
 214                         #interrupt-cells = <2>;
 215                         interrupt-controller;
 216                         clocks = <&cpg CPG_MOD 908>;
 217                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 218                         resets = <&cpg 908>;
 219                 };
 220
 221                 gpio5: gpio@e6055000 {
 222                         compatible = "renesas,gpio-r8a7792",
 223                                      "renesas,rcar-gen2-gpio";
 224                         reg = <0 0xe6055000 0 0x50>;
 225                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 226                         #gpio-cells = <2>;
 227                         gpio-controller;
 228                         gpio-ranges = <&pfc 0 160 17>;
 229                         #interrupt-cells = <2>;
 230                         interrupt-controller;
 231                         clocks = <&cpg CPG_MOD 907>;
 232                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 233                         resets = <&cpg 907>;
 234                 };
 235
 236                 gpio6: gpio@e6055100 {
 237                         compatible = "renesas,gpio-r8a7792",
 238                                      "renesas,rcar-gen2-gpio";
 239                         reg = <0 0xe6055100 0 0x50>;
 240                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 241                         #gpio-cells = <2>;
 242                         gpio-controller;
 243                         gpio-ranges = <&pfc 0 192 17>;
 244                         #interrupt-cells = <2>;
 245                         interrupt-controller;
 246                         clocks = <&cpg CPG_MOD 905>;
 247                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 248                         resets = <&cpg 905>;
 249                 };
 250
 251                 gpio7: gpio@e6055200 {
 252                         compatible = "renesas,gpio-r8a7792",
 253                                      "renesas,rcar-gen2-gpio";
 254                         reg = <0 0xe6055200 0 0x50>;
 255                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 256                         #gpio-cells = <2>;
 257                         gpio-controller;
 258                         gpio-ranges = <&pfc 0 224 17>;
 259                         #interrupt-cells = <2>;
 260                         interrupt-controller;
 261                         clocks = <&cpg CPG_MOD 904>;
 262                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 263                         resets = <&cpg 904>;
 264                 };
 265
 266                 gpio8: gpio@e6055300 {
 267                         compatible = "renesas,gpio-r8a7792",
 268                                      "renesas,rcar-gen2-gpio";
 269                         reg = <0 0xe6055300 0 0x50>;
 270                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 271                         #gpio-cells = <2>;
 272                         gpio-controller;
 273                         gpio-ranges = <&pfc 0 256 17>;
 274                         #interrupt-cells = <2>;
 275                         interrupt-controller;
 276                         clocks = <&cpg CPG_MOD 921>;
 277                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 278                         resets = <&cpg 921>;
 279                 };
 280
 281                 gpio9: gpio@e6055400 {
 282                         compatible = "renesas,gpio-r8a7792",
 283                                      "renesas,rcar-gen2-gpio";
 284                         reg = <0 0xe6055400 0 0x50>;
 285                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 286                         #gpio-cells = <2>;
 287                         gpio-controller;
 288                         gpio-ranges = <&pfc 0 288 17>;
 289                         #interrupt-cells = <2>;
 290                         interrupt-controller;
 291                         clocks = <&cpg CPG_MOD 919>;
 292                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 293                         resets = <&cpg 919>;
 294                 };
 295
 296                 gpio10: gpio@e6055500 {
 297                         compatible = "renesas,gpio-r8a7792",
 298                                      "renesas,rcar-gen2-gpio";
 299                         reg = <0 0xe6055500 0 0x50>;
 300                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 301                         #gpio-cells = <2>;
 302                         gpio-controller;
 303                         gpio-ranges = <&pfc 0 320 32>;
 304                         #interrupt-cells = <2>;
 305                         interrupt-controller;
 306                         clocks = <&cpg CPG_MOD 914>;
 307                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 308                         resets = <&cpg 914>;
 309                 };
 310
 311                 gpio11: gpio@e6055600 {
 312                         compatible = "renesas,gpio-r8a7792",
 313                                      "renesas,rcar-gen2-gpio";
 314                         reg = <0 0xe6055600 0 0x50>;
 315                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 316                         #gpio-cells = <2>;
 317                         gpio-controller;
 318                         gpio-ranges = <&pfc 0 352 30>;
 319                         #interrupt-cells = <2>;
 320                         interrupt-controller;
 321                         clocks = <&cpg CPG_MOD 913>;
 322                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 323                         resets = <&cpg 913>;
 324                 };
 325
 326                 dmac0: dma-controller@e6700000 {
 327                         compatible = "renesas,dmac-r8a7792",
 328                                      "renesas,rcar-dmac";
 329                         reg = <0 0xe6700000 0 0x20000>;
 330                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 331                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 332                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 333                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 334                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 335                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 336                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 337                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 338                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 339                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 340                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 341                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 342                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 343                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 344                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 345                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 346                         interrupt-names = "error",
 347                                           "ch0", "ch1", "ch2", "ch3",
 348                                           "ch4", "ch5", "ch6", "ch7",
 349                                           "ch8", "ch9", "ch10", "ch11",
 350                                           "ch12", "ch13", "ch14";
 351                         clocks = <&cpg CPG_MOD 219>;
 352                         clock-names = "fck";
 353                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 354                         resets = <&cpg 219>;
 355                         #dma-cells = <1>;
 356                         dma-channels = <15>;
 357                 };
 358
 359                 dmac1: dma-controller@e6720000 {
 360                         compatible = "renesas,dmac-r8a7792",
 361                                      "renesas,rcar-dmac";
 362                         reg = <0 0xe6720000 0 0x20000>;
 363                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 364                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 365                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 366                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 367                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 368                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 369                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 370                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 371                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 372                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 373                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 374                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 375                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 376                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 377                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 378                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 379                         interrupt-names = "error",
 380                                           "ch0", "ch1", "ch2", "ch3",
 381                                           "ch4", "ch5", "ch6", "ch7",
 382                                           "ch8", "ch9", "ch10", "ch11",
 383                                           "ch12", "ch13", "ch14";
 384                         clocks = <&cpg CPG_MOD 218>;
 385                         clock-names = "fck";
 386                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 387                         resets = <&cpg 218>;
 388                         #dma-cells = <1>;
 389                         dma-channels = <15>;
 390                 };
 391
 392                 scif0: serial@e6e60000 {
 393                         compatible = "renesas,scif-r8a7792",
 394                                      "renesas,rcar-gen2-scif", "renesas,scif";
 395                         reg = <0 0xe6e60000 0 64>;
 396                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 397                         clocks = <&cpg CPG_MOD 721>,
 398                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 399                         clock-names = "fck", "brg_int", "scif_clk";
 400                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 401                                <&dmac1 0x29>, <&dmac1 0x2a>;
 402                         dma-names = "tx", "rx", "tx", "rx";
 403                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 404                         resets = <&cpg 721>;
 405                         status = "disabled";
 406                 };
 407
 408                 scif1: serial@e6e68000 {
 409                         compatible = "renesas,scif-r8a7792",
 410                                      "renesas,rcar-gen2-scif", "renesas,scif";
 411                         reg = <0 0xe6e68000 0 64>;
 412                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 413                         clocks = <&cpg CPG_MOD 720>,
 414                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 415                         clock-names = "fck", "brg_int", "scif_clk";
 416                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 417                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 418                         dma-names = "tx", "rx", "tx", "rx";
 419                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 420                         resets = <&cpg 720>;
 421                         status = "disabled";
 422                 };
 423
 424                 scif2: serial@e6e58000 {
 425                         compatible = "renesas,scif-r8a7792",
 426                                      "renesas,rcar-gen2-scif", "renesas,scif";
 427                         reg = <0 0xe6e58000 0 64>;
 428                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&cpg CPG_MOD 719>,
 430                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 431                         clock-names = "fck", "brg_int", "scif_clk";
 432                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 433                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 434                         dma-names = "tx", "rx", "tx", "rx";
 435                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 436                         resets = <&cpg 719>;
 437                         status = "disabled";
 438                 };
 439
 440                 scif3: serial@e6ea8000 {
 441                         compatible = "renesas,scif-r8a7792",
 442                                      "renesas,rcar-gen2-scif", "renesas,scif";
 443                         reg = <0 0xe6ea8000 0 64>;
 444                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&cpg CPG_MOD 718>,
 446                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 447                         clock-names = "fck", "brg_int", "scif_clk";
 448                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 449                                <&dmac1 0x2f>, <&dmac1 0x30>;
 450                         dma-names = "tx", "rx", "tx", "rx";
 451                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 452                         resets = <&cpg 718>;
 453                         status = "disabled";
 454                 };
 455
 456                 hscif0: serial@e62c0000 {
 457                         compatible = "renesas,hscif-r8a7792",
 458                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 459                         reg = <0 0xe62c0000 0 96>;
 460                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 461                         clocks = <&cpg CPG_MOD 717>,
 462                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 463                         clock-names = "fck", "brg_int", "scif_clk";
 464                         dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 465                                <&dmac1 0x39>, <&dmac1 0x3a>;
 466                         dma-names = "tx", "rx", "tx", "rx";
 467                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 468                         resets = <&cpg 717>;
 469                         status = "disabled";
 470                 };
 471
 472                 hscif1: serial@e62c8000 {
 473                         compatible = "renesas,hscif-r8a7792",
 474                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 475                         reg = <0 0xe62c8000 0 96>;
 476                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 477                         clocks = <&cpg CPG_MOD 716>,
 478                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 479                         clock-names = "fck", "brg_int", "scif_clk";
 480                         dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 481                                <&dmac1 0x4d>, <&dmac1 0x4e>;
 482                         dma-names = "tx", "rx", "tx", "rx";
 483                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 484                         resets = <&cpg 716>;
 485                         status = "disabled";
 486                 };
 487
 488                 icram0: sram@e63a0000 {
 489                         compatible = "mmio-sram";
 490                         reg = <0 0xe63a0000 0 0x12000>;
 491                 };
 492
 493                 icram1: sram@e63c0000 {
 494                         compatible = "mmio-sram";
 495                         reg = <0 0xe63c0000 0 0x1000>;
 496                         #address-cells = <1>;
 497                         #size-cells = <1>;
 498                         ranges = <0 0 0xe63c0000 0x1000>;
 499
 500                         smp-sram@0 {
 501                                 compatible = "renesas,smp-sram";
 502                                 reg = <0 0x10>;
 503                         };
 504                 };
 505
 506                 sdhi0: sd@ee100000 {
 507                         compatible = "renesas,sdhi-r8a7792";
 508                         reg = <0 0xee100000 0 0x328>;
 509                         interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 510                         dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 511                                <&dmac1 0xcd>, <&dmac1 0xce>;
 512                         dma-names = "tx", "rx", "tx", "rx";
 513                         clocks = <&cpg CPG_MOD 314>;
 514                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 515                         resets = <&cpg 314>;
 516                         status = "disabled";
 517                 };
 518
 519                 jpu: jpeg-codec@fe980000 {
 520                         compatible = "renesas,jpu-r8a7792",
 521                                      "renesas,rcar-gen2-jpu";
 522                         reg = <0 0xfe980000 0 0x10300>;
 523                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&cpg CPG_MOD 106>;
 525                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 526                         resets = <&cpg 106>;
 527                 };
 528
 529                 avb: ethernet@e6800000 {
 530                         compatible = "renesas,etheravb-r8a7792",
 531                                      "renesas,etheravb-rcar-gen2";
 532                         reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 533                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 534                         clocks = <&cpg CPG_MOD 812>;
 535                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 536                         resets = <&cpg 812>;
 537                         #address-cells = <1>;
 538                         #size-cells = <0>;
 539                         status = "disabled";
 540                 };
 541
 542                 /* I2C doesn't need pinmux */
 543                 i2c0: i2c@e6508000 {
 544                         compatible = "renesas,i2c-r8a7792",
 545                                      "renesas,rcar-gen2-i2c";
 546                         reg = <0 0xe6508000 0 0x40>;
 547                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 548                         clocks = <&cpg CPG_MOD 931>;
 549                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 550                         resets = <&cpg 931>;
 551                         i2c-scl-internal-delay-ns = <6>;
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554                         status = "disabled";
 555                 };
 556
 557                 i2c1: i2c@e6518000 {
 558                         compatible = "renesas,i2c-r8a7792",
 559                                      "renesas,rcar-gen2-i2c";
 560                         reg = <0 0xe6518000 0 0x40>;
 561                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&cpg CPG_MOD 930>;
 563                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 564                         resets = <&cpg 930>;
 565                         i2c-scl-internal-delay-ns = <6>;
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         status = "disabled";
 569                 };
 570
 571                 i2c2: i2c@e6530000 {
 572                         compatible = "renesas,i2c-r8a7792",
 573                                      "renesas,rcar-gen2-i2c";
 574                         reg = <0 0xe6530000 0 0x40>;
 575                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&cpg CPG_MOD 929>;
 577                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 578                         resets = <&cpg 929>;
 579                         i2c-scl-internal-delay-ns = <6>;
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         status = "disabled";
 583                 };
 584
 585                 i2c3: i2c@e6540000 {
 586                         compatible = "renesas,i2c-r8a7792",
 587                                      "renesas,rcar-gen2-i2c";
 588                         reg = <0 0xe6540000 0 0x40>;
 589                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 590                         clocks = <&cpg CPG_MOD 928>;
 591                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 592                         resets = <&cpg 928>;
 593                         i2c-scl-internal-delay-ns = <6>;
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                         status = "disabled";
 597                 };
 598
 599                 i2c4: i2c@e6520000 {
 600                         compatible = "renesas,i2c-r8a7792",
 601                                      "renesas,rcar-gen2-i2c";
 602                         reg = <0 0xe6520000 0 0x40>;
 603                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 604                         clocks = <&cpg CPG_MOD 927>;
 605                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 606                         resets = <&cpg 927>;
 607                         i2c-scl-internal-delay-ns = <6>;
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610                         status = "disabled";
 611                 };
 612
 613                 i2c5: i2c@e6528000 {
 614                         compatible = "renesas,i2c-r8a7792",
 615                                      "renesas,rcar-gen2-i2c";
 616                         reg = <0 0xe6528000 0 0x40>;
 617                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 618                         clocks = <&cpg CPG_MOD 925>;
 619                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 620                         resets = <&cpg 925>;
 621                         i2c-scl-internal-delay-ns = <110>;
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624                         status = "disabled";
 625                 };
 626
 627                 qspi: spi@e6b10000 {
 628                         compatible = "renesas,qspi-r8a7792", "renesas,qspi";
 629                         reg = <0 0xe6b10000 0 0x2c>;
 630                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 631                         clocks = <&cpg CPG_MOD 917>;
 632                         dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 633                                <&dmac1 0x17>, <&dmac1 0x18>;
 634                         dma-names = "tx", "rx", "tx", "rx";
 635                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 636                         resets = <&cpg 917>;
 637                         num-cs = <1>;
 638                         #address-cells = <1>;
 639                         #size-cells = <0>;
 640                         status = "disabled";
 641                 };
 642
 643                 msiof0: spi@e6e20000 {
 644                         compatible = "renesas,msiof-r8a7792",
 645                                      "renesas,rcar-gen2-msiof";
 646                         reg = <0 0xe6e20000 0 0x0064>;
 647                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 648                         clocks = <&cpg CPG_MOD 000>;
 649                         dmas = <&dmac0 0x51>, <&dmac0 0x52>,
 650                                <&dmac1 0x51>, <&dmac1 0x52>;
 651                         dma-names = "tx", "rx", "tx", "rx";
 652                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 653                         resets = <&cpg 000>;
 654                         #address-cells = <1>;
 655                         #size-cells = <0>;
 656                         status = "disabled";
 657                 };
 658
 659                 msiof1: spi@e6e10000 {
 660                         compatible = "renesas,msiof-r8a7792",
 661                                      "renesas,rcar-gen2-msiof";
 662                         reg = <0 0xe6e10000 0 0x0064>;
 663                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 664                         clocks = <&cpg CPG_MOD 208>;
 665                         dmas = <&dmac0 0x55>, <&dmac0 0x56>,
 666                                <&dmac1 0x55>, <&dmac1 0x56>;
 667                         dma-names = "tx", "rx", "tx", "rx";
 668                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 669                         resets = <&cpg 208>;
 670                         #address-cells = <1>;
 671                         #size-cells = <0>;
 672                         status = "disabled";
 673                 };
 674
 675                 du: display@feb00000 {
 676                         compatible = "renesas,du-r8a7792";
 677                         reg = <0 0xfeb00000 0 0x40000>;
 678                         reg-names = "du";
 679                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 680                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 681                         clocks = <&cpg CPG_MOD 724>,
 682                                  <&cpg CPG_MOD 723>;
 683                         clock-names = "du.0", "du.1";
 684                         status = "disabled";
 685
 686                         ports {
 687                                 #address-cells = <1>;
 688                                 #size-cells = <0>;
 689
 690                                 port@0 {
 691                                         reg = <0>;
 692                                         du_out_rgb0: endpoint {
 693                                         };
 694                                 };
 695                                 port@1 {
 696                                         reg = <1>;
 697                                         du_out_rgb1: endpoint {
 698                                         };
 699                                 };
 700                         };
 701                 };
 702
 703                 can0: can@e6e80000 {
 704                         compatible = "renesas,can-r8a7792",
 705                                      "renesas,rcar-gen2-can";
 706                         reg = <0 0xe6e80000 0 0x1000>;
 707                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 708                         clocks = <&cpg CPG_MOD 916>,
 709                                  <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
 710                         clock-names = "clkp1", "clkp2", "can_clk";
 711                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 712                         resets = <&cpg 916>;
 713                         status = "disabled";
 714                 };
 715
 716                 can1: can@e6e88000 {
 717                         compatible = "renesas,can-r8a7792",
 718                                      "renesas,rcar-gen2-can";
 719                         reg = <0 0xe6e88000 0 0x1000>;
 720                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 721                         clocks = <&cpg CPG_MOD 915>,
 722                                  <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
 723                         clock-names = "clkp1", "clkp2", "can_clk";
 724                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 725                         resets = <&cpg 915>;
 726                         status = "disabled";
 727                 };
 728
 729                 vin0: video@e6ef0000 {
 730                         compatible = "renesas,vin-r8a7792",
 731                                      "renesas,rcar-gen2-vin";
 732                         reg = <0 0xe6ef0000 0 0x1000>;
 733                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 734                         clocks = <&cpg CPG_MOD 811>;
 735                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 736                         resets = <&cpg 811>;
 737                         status = "disabled";
 738                 };
 739
 740                 vin1: video@e6ef1000 {
 741                         compatible = "renesas,vin-r8a7792",
 742                                      "renesas,rcar-gen2-vin";
 743                         reg = <0 0xe6ef1000 0 0x1000>;
 744                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 745                         clocks = <&cpg CPG_MOD 810>;
 746                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 747                         resets = <&cpg 810>;
 748                         status = "disabled";
 749                 };
 750
 751                 vin2: video@e6ef2000 {
 752                         compatible = "renesas,vin-r8a7792",
 753                                      "renesas,rcar-gen2-vin";
 754                         reg = <0 0xe6ef2000 0 0x1000>;
 755                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 756                         clocks = <&cpg CPG_MOD 809>;
 757                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 758                         resets = <&cpg 809>;
 759                         status = "disabled";
 760                 };
 761
 762                 vin3: video@e6ef3000 {
 763                         compatible = "renesas,vin-r8a7792",
 764                                      "renesas,rcar-gen2-vin";
 765                         reg = <0 0xe6ef3000 0 0x1000>;
 766                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 767                         clocks = <&cpg CPG_MOD 808>;
 768                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 769                         resets = <&cpg 808>;
 770                         status = "disabled";
 771                 };
 772
 773                 vin4: video@e6ef4000 {
 774                         compatible = "renesas,vin-r8a7792",
 775                                      "renesas,rcar-gen2-vin";
 776                         reg = <0 0xe6ef4000 0 0x1000>;
 777                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 778                         clocks = <&cpg CPG_MOD 805>;
 779                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 780                         resets = <&cpg 805>;
 781                         status = "disabled";
 782                 };
 783
 784                 vin5: video@e6ef5000 {
 785                         compatible = "renesas,vin-r8a7792",
 786                                      "renesas,rcar-gen2-vin";
 787                         reg = <0 0xe6ef5000 0 0x1000>;
 788                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 789                         clocks = <&cpg CPG_MOD 804>;
 790                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 791                         resets = <&cpg 804>;
 792                         status = "disabled";
 793                 };
 794
 795                 vsp@fe928000 {
 796                         compatible = "renesas,vsp1";
 797                         reg = <0 0xfe928000 0 0x8000>;
 798                         interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 799                         clocks = <&cpg CPG_MOD 131>;
 800                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 801                         resets = <&cpg 131>;
 802                 };
 803
 804                 vsp@fe930000 {
 805                         compatible = "renesas,vsp1";
 806                         reg = <0 0xfe930000 0 0x8000>;
 807                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 808                         clocks = <&cpg CPG_MOD 128>;
 809                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 810                         resets = <&cpg 128>;
 811                 };
 812
 813                 vsp@fe938000 {
 814                         compatible = "renesas,vsp1";
 815                         reg = <0 0xfe938000 0 0x8000>;
 816                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 817                         clocks = <&cpg CPG_MOD 127>;
 818                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 819                         resets = <&cpg 127>;
 820                 };
 821
 822                 cpg: clock-controller@e6150000 {
 823                         compatible = "renesas,r8a7792-cpg-mssr";
 824                         reg = <0 0xe6150000 0 0x1000>;
 825                         clocks = <&extal_clk>;
 826                         clock-names = "extal";
 827                         #clock-cells = <2>;
 828                         #power-domain-cells = <0>;
 829                         #reset-cells = <1>;
 830                 };
 831         };
 832
 833         /* External root clock */
 834         extal_clk: extal {
 835                 compatible = "fixed-clock";
 836                 #clock-cells = <0>;
 837                 /* This value must be overridden by the board. */
 838                 clock-frequency = <0>;
 839         };
 840
 841         /* External SCIF clock */
 842         scif_clk: scif {
 843                 compatible = "fixed-clock";
 844                 #clock-cells = <0>;
 845                 /* This value must be overridden by the board. */
 846                 clock-frequency = <0>;
 847         };
 848
 849         /* External CAN clock */
 850         can_clk: can {
 851                 compatible = "fixed-clock";
 852                 #clock-cells = <0>;
 853                 /* This value must be overridden by the board. */
 854                 clock-frequency = <0>;
 855         };
 856 };