SPDX: Convert all of our single license tags to Linux Kernel style
[oweals/u-boot.git] / arch / arm / dts / r8a7791-porter.dts
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Device Tree Source for the Porter board
4  *
5  * Copyright (C) 2015 Cogent Embedded, Inc.
6  */
7
8 /*
9  * SSI-AK4642
10  *
11  * JP3: 2-1: AK4642
12  *      2-3: ADV7511
13  *
14  * This command is required before playback/capture:
15  *
16  *      amixer set "LINEOUT Mixer DACL" on
17  */
18
19 /dts-v1/;
20 #include "r8a7791.dtsi"
21 #include <dt-bindings/gpio/gpio.h>
22
23 / {
24         model = "Porter";
25         compatible = "renesas,porter", "renesas,r8a7791";
26
27         aliases {
28                 serial0 = &scif0;
29         };
30
31         chosen {
32                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
33                 stdout-path = "serial0:115200n8";
34         };
35
36         memory@40000000 {
37                 device_type = "memory";
38                 reg = <0 0x40000000 0 0x40000000>;
39         };
40
41         memory@200000000 {
42                 device_type = "memory";
43                 reg = <2 0x00000000 0 0x40000000>;
44         };
45
46         vcc_sdhi0: regulator-vcc-sdhi0 {
47                 compatible = "regulator-fixed";
48
49                 regulator-name = "SDHI0 Vcc";
50                 regulator-min-microvolt = <3300000>;
51                 regulator-max-microvolt = <3300000>;
52                 regulator-always-on;
53         };
54
55         vccq_sdhi0: regulator-vccq-sdhi0 {
56                 compatible = "regulator-gpio";
57
58                 regulator-name = "SDHI0 VccQ";
59                 regulator-min-microvolt = <1800000>;
60                 regulator-max-microvolt = <3300000>;
61
62                 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
63                 gpios-states = <1>;
64                 states = <3300000 1
65                           1800000 0>;
66         };
67
68         vcc_sdhi2: regulator-vcc-sdhi2 {
69                 compatible = "regulator-fixed";
70
71                 regulator-name = "SDHI2 Vcc";
72                 regulator-min-microvolt = <3300000>;
73                 regulator-max-microvolt = <3300000>;
74                 regulator-always-on;
75         };
76
77         vccq_sdhi2: regulator-vccq-sdhi2 {
78                 compatible = "regulator-gpio";
79
80                 regulator-name = "SDHI2 VccQ";
81                 regulator-min-microvolt = <1800000>;
82                 regulator-max-microvolt = <3300000>;
83
84                 gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
85                 gpios-states = <1>;
86                 states = <3300000 1
87                           1800000 0>;
88         };
89
90         hdmi-out {
91                 compatible = "hdmi-connector";
92                 type = "a";
93
94                 port {
95                         hdmi_con: endpoint {
96                                 remote-endpoint = <&adv7511_out>;
97                         };
98                 };
99         };
100
101         x3_clk: x3-clock {
102                 compatible = "fixed-clock";
103                 #clock-cells = <0>;
104                 clock-frequency = <148500000>;
105         };
106
107         x16_clk: x16-clock {
108                 compatible = "fixed-clock";
109                 #clock-cells = <0>;
110                 clock-frequency = <74250000>;
111         };
112
113         x14_clk: audio_clock {
114                 compatible = "fixed-clock";
115                 #clock-cells = <0>;
116                 clock-frequency = <11289600>;
117         };
118
119         sound {
120                 compatible = "simple-audio-card";
121
122                 simple-audio-card,format = "left_j";
123                 simple-audio-card,bitclock-master = <&soundcodec>;
124                 simple-audio-card,frame-master = <&soundcodec>;
125
126                 simple-audio-card,cpu {
127                         sound-dai = <&rcar_sound>;
128                 };
129
130                 soundcodec: simple-audio-card,codec {
131                         sound-dai = <&ak4642>;
132                         clocks = <&x14_clk>;
133                 };
134         };
135 };
136
137 &extal_clk {
138         clock-frequency = <20000000>;
139 };
140
141 &pfc {
142         scif0_pins: scif0 {
143                 groups = "scif0_data_d";
144                 function = "scif0";
145         };
146
147         ether_pins: ether {
148                 groups = "eth_link", "eth_mdio", "eth_rmii";
149                 function = "eth";
150         };
151
152         phy1_pins: phy1 {
153                 groups = "intc_irq0";
154                 function = "intc";
155         };
156
157         sdhi0_pins: sd0 {
158                 groups = "sdhi0_data4", "sdhi0_ctrl";
159                 function = "sdhi0";
160         };
161
162         sdhi2_pins: sd2 {
163                 groups = "sdhi2_data4", "sdhi2_ctrl";
164                 function = "sdhi2";
165         };
166
167         qspi_pins: qspi {
168                 groups = "qspi_ctrl", "qspi_data4";
169                 function = "qspi";
170         };
171
172         i2c2_pins: i2c2 {
173                 groups = "i2c2";
174                 function = "i2c2";
175         };
176
177         usb0_pins: usb0 {
178                 groups = "usb0";
179                 function = "usb0";
180         };
181
182         usb1_pins: usb1 {
183                 groups = "usb1";
184                 function = "usb1";
185         };
186
187         vin0_pins: vin0 {
188                 groups = "vin0_data8", "vin0_clk";
189                 function = "vin0";
190         };
191
192         can0_pins: can0 {
193                 groups = "can0_data";
194                 function = "can0";
195         };
196
197         du_pins: du {
198                 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
199                 function = "du";
200         };
201
202         ssi_pins: sound {
203                 groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
204                 function = "ssi";
205         };
206
207         audio_clk_pins: audio_clk {
208                 groups = "audio_clk_a";
209                 function = "audio_clk";
210         };
211 };
212
213 &scif0 {
214         pinctrl-0 = <&scif0_pins>;
215         pinctrl-names = "default";
216
217         status = "okay";
218 };
219
220 &ether {
221         pinctrl-0 = <&ether_pins &phy1_pins>;
222         pinctrl-names = "default";
223
224         phy-handle = <&phy1>;
225         renesas,ether-link-active-low;
226         status = "okay";
227
228         phy1: ethernet-phy@1 {
229                 reg = <1>;
230                 interrupt-parent = <&irqc0>;
231                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
232                 micrel,led-mode = <1>;
233         };
234 };
235
236 &sdhi0 {
237         pinctrl-0 = <&sdhi0_pins>;
238         pinctrl-names = "default";
239
240         vmmc-supply = <&vcc_sdhi0>;
241         vqmmc-supply = <&vccq_sdhi0>;
242         cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
243         wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
244         status = "okay";
245 };
246
247 &sdhi2 {
248         pinctrl-0 = <&sdhi2_pins>;
249         pinctrl-names = "default";
250
251         vmmc-supply = <&vcc_sdhi2>;
252         vqmmc-supply = <&vccq_sdhi2>;
253         cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
254         status = "okay";
255 };
256
257 &qspi {
258         pinctrl-0 = <&qspi_pins>;
259         pinctrl-names = "default";
260
261         status = "okay";
262
263         flash@0 {
264                 compatible = "spansion,s25fl512s", "jedec,spi-nor";
265                 reg = <0>;
266                 spi-max-frequency = <30000000>;
267                 spi-tx-bus-width = <4>;
268                 spi-rx-bus-width = <4>;
269                 m25p,fast-read;
270
271                 partitions {
272                         compatible = "fixed-partitions";
273                         #address-cells = <1>;
274                         #size-cells = <1>;
275
276                         partition@0 {
277                                 label = "loader_prg";
278                                 reg = <0x00000000 0x00040000>;
279                                 read-only;
280                         };
281                         partition@40000 {
282                                 label = "user_prg";
283                                 reg = <0x00040000 0x00400000>;
284                                 read-only;
285                         };
286                         partition@440000 {
287                                 label = "flash_fs";
288                                 reg = <0x00440000 0x03bc0000>;
289                         };
290                 };
291         };
292 };
293
294 &i2c2 {
295         pinctrl-0 = <&i2c2_pins>;
296         pinctrl-names = "default";
297
298         status = "okay";
299         clock-frequency = <400000>;
300
301         ak4642: codec@12 {
302                 compatible = "asahi-kasei,ak4642";
303                 #sound-dai-cells = <0>;
304                 reg = <0x12>;
305         };
306
307         composite-in@20 {
308                 compatible = "adi,adv7180";
309                 reg = <0x20>;
310                 remote = <&vin0>;
311
312                 port {
313                         adv7180: endpoint {
314                                 bus-width = <8>;
315                                 remote-endpoint = <&vin0ep>;
316                         };
317                 };
318         };
319
320         hdmi@39 {
321                 compatible = "adi,adv7511w";
322                 reg = <0x39>;
323                 interrupt-parent = <&gpio3>;
324                 interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
325
326                 adi,input-depth = <8>;
327                 adi,input-colorspace = "rgb";
328                 adi,input-clock = "1x";
329                 adi,input-style = <1>;
330                 adi,input-justification = "evenly";
331
332                 ports {
333                         #address-cells = <1>;
334                         #size-cells = <0>;
335
336                         port@0 {
337                                 reg = <0>;
338                                 adv7511_in: endpoint {
339                                         remote-endpoint = <&du_out_rgb>;
340                                 };
341                         };
342
343                         port@1 {
344                                 reg = <1>;
345                                 adv7511_out: endpoint {
346                                         remote-endpoint = <&hdmi_con>;
347                                 };
348                         };
349                 };
350         };
351 };
352
353 &i2c6 {
354         status = "okay";
355         clock-frequency = <400000>;
356 };
357
358 &sata0 {
359         status = "okay";
360 };
361
362 /* composite video input */
363 &vin0 {
364         status = "okay";
365         pinctrl-0 = <&vin0_pins>;
366         pinctrl-names = "default";
367
368         port {
369                 #address-cells = <1>;
370                 #size-cells = <0>;
371
372                 vin0ep: endpoint {
373                         remote-endpoint = <&adv7180>;
374                         bus-width = <8>;
375                 };
376         };
377 };
378
379 &pci0 {
380         pinctrl-0 = <&usb0_pins>;
381         pinctrl-names = "default";
382
383         status = "okay";
384 };
385
386 &pci1 {
387         pinctrl-0 = <&usb1_pins>;
388         pinctrl-names = "default";
389
390         status = "okay";
391 };
392
393 &hsusb {
394         pinctrl-0 = <&usb0_pins>;
395         pinctrl-names = "default";
396
397         status = "okay";
398 };
399
400 &usbphy {
401         status = "okay";
402 };
403
404 &pcie_bus_clk {
405         clock-frequency = <100000000>;
406 };
407
408 &pciec {
409         status = "okay";
410 };
411
412 &can0 {
413         pinctrl-0 = <&can0_pins>;
414         pinctrl-names = "default";
415
416         status = "okay";
417 };
418
419 &du {
420         pinctrl-0 = <&du_pins>;
421         pinctrl-names = "default";
422         status = "okay";
423
424         clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
425                  <&x3_clk>, <&x16_clk>;
426         clock-names = "du.0", "du.1", "lvds.0",
427                       "dclkin.0", "dclkin.1";
428
429         ports {
430                 port@1 {
431                         endpoint {
432                                 remote-endpoint = <&adv7511_in>;
433                         };
434                 };
435         };
436 };
437
438 &rcar_sound {
439         pinctrl-0 = <&ssi_pins &audio_clk_pins>;
440         pinctrl-names = "default";
441         status = "okay";
442
443         /* Single DAI */
444         #sound-dai-cells = <0>;
445
446         rcar_sound,dai {
447                 dai0 {
448                         playback = <&ssi0>;
449                         capture  = <&ssi1>;
450                 };
451         };
452 };
453
454 &ssi1 {
455         shared-pin;
456 };