arch/arm/dts/px30.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/px30-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/px30-power.h>
  12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         compatible = "rockchip,px30";
  17
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 ethernet0 = &gmac;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &uart2;
  31                 serial3 = &uart3;
  32                 serial4 = &uart4;
  33                 serial5 = &uart5;
  34                 spi0 = &spi0;
  35                 spi1 = &spi1;
  36         };
  37
  38         cpus {
  39                 #address-cells = <2>;
  40                 #size-cells = <0>;
  41
  42                 cpu0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a35";
  45                         reg = <0x0 0x0>;
  46                         enable-method = "psci";
  47                         clocks = <&cru ARMCLK>;
  48                         #cooling-cells = <2>;
  49                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  50                         dynamic-power-coefficient = <90>;
  51                         operating-points-v2 = <&cpu0_opp_table>;
  52                 };
  53
  54                 cpu1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a35";
  57                         reg = <0x0 0x1>;
  58                         enable-method = "psci";
  59                         clocks = <&cru ARMCLK>;
  60                         #cooling-cells = <2>;
  61                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  62                         dynamic-power-coefficient = <90>;
  63                         operating-points-v2 = <&cpu0_opp_table>;
  64                 };
  65
  66                 cpu2: cpu@2 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a35";
  69                         reg = <0x0 0x2>;
  70                         enable-method = "psci";
  71                         clocks = <&cru ARMCLK>;
  72                         #cooling-cells = <2>;
  73                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  74                         dynamic-power-coefficient = <90>;
  75                         operating-points-v2 = <&cpu0_opp_table>;
  76                 };
  77
  78                 cpu3: cpu@3 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a35";
  81                         reg = <0x0 0x3>;
  82                         enable-method = "psci";
  83                         clocks = <&cru ARMCLK>;
  84                         #cooling-cells = <2>;
  85                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  86                         dynamic-power-coefficient = <90>;
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88                 };
  89
  90                 idle-states {
  91                         entry-method = "psci";
  92
  93                         CPU_SLEEP: cpu-sleep {
  94                                 compatible = "arm,idle-state";
  95                                 local-timer-stop;
  96                                 arm,psci-suspend-param = <0x0010000>;
  97                                 entry-latency-us = <120>;
  98                                 exit-latency-us = <250>;
  99                                 min-residency-us = <900>;
 100                         };
 101
 102                         CLUSTER_SLEEP: cluster-sleep {
 103                                 compatible = "arm,idle-state";
 104                                 local-timer-stop;
 105                                 arm,psci-suspend-param = <0x1010000>;
 106                                 entry-latency-us = <400>;
 107                                 exit-latency-us = <500>;
 108                                 min-residency-us = <2000>;
 109                         };
 110                 };
 111         };
 112
 113         cpu0_opp_table: cpu0-opp-table {
 114                 compatible = "operating-points-v2";
 115                 opp-shared;
 116
 117                 opp-600000000 {
 118                         opp-hz = /bits/ 64 <600000000>;
 119                         opp-microvolt = <950000 950000 1350000>;
 120                         clock-latency-ns = <40000>;
 121                         opp-suspend;
 122                 };
 123                 opp-816000000 {
 124                         opp-hz = /bits/ 64 <816000000>;
 125                         opp-microvolt = <1050000 1050000 1350000>;
 126                         clock-latency-ns = <40000>;
 127                 };
 128                 opp-1008000000 {
 129                         opp-hz = /bits/ 64 <1008000000>;
 130                         opp-microvolt = <1175000 1175000 1350000>;
 131                         clock-latency-ns = <40000>;
 132                 };
 133                 opp-1200000000 {
 134                         opp-hz = /bits/ 64 <1200000000>;
 135                         opp-microvolt = <1300000 1300000 1350000>;
 136                         clock-latency-ns = <40000>;
 137                 };
 138                 opp-1296000000 {
 139                         opp-hz = /bits/ 64 <1296000000>;
 140                         opp-microvolt = <1350000 1350000 1350000>;
 141                         clock-latency-ns = <40000>;
 142                 };
 143         };
 144
 145         arm-pmu {
 146                 compatible = "arm,cortex-a53-pmu";
 147                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 151                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 152         };
 153
 154         dmc: dmc {
 155                 compatible = "rockchip,px30-dmc", "syscon";
 156                 reg = <0x0 0xff2a0000 0x0 0x1000>;
 157         };
 158
 159         display_subsystem: display-subsystem {
 160                 compatible = "rockchip,display-subsystem";
 161                 ports = <&vopb_out>, <&vopl_out>;
 162                 status = "disabled";
 163         };
 164
 165         gmac_clkin: external-gmac-clock {
 166                 compatible = "fixed-clock";
 167                 clock-frequency = <50000000>;
 168                 clock-output-names = "gmac_clkin";
 169                 #clock-cells = <0>;
 170         };
 171
 172         psci {
 173                 compatible = "arm,psci-1.0";
 174                 method = "smc";
 175         };
 176
 177         timer {
 178                 compatible = "arm,armv8-timer";
 179                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 180                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 181                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 182                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 183         };
 184
 185         thermal_zones: thermal-zones {
 186                 soc_thermal: soc-thermal {
 187                         polling-delay-passive = <20>;
 188                         polling-delay = <1000>;
 189                         sustainable-power = <750>;
 190                         thermal-sensors = <&tsadc 0>;
 191
 192                         trips {
 193                                 threshold: trip-point-0 {
 194                                         temperature = <70000>;
 195                                         hysteresis = <2000>;
 196                                         type = "passive";
 197                                 };
 198
 199                                 target: trip-point-1 {
 200                                         temperature = <85000>;
 201                                         hysteresis = <2000>;
 202                                         type = "passive";
 203                                 };
 204
 205                                 soc_crit: soc-crit {
 206                                         temperature = <115000>;
 207                                         hysteresis = <2000>;
 208                                         type = "critical";
 209                                 };
 210                         };
 211
 212                         cooling-maps {
 213                                 map0 {
 214                                         trip = <&target>;
 215                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 216                                         contribution = <4096>;
 217                                 };
 218
 219                                 map1 {
 220                                         trip = <&target>;
 221                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 222                                         contribution = <4096>;
 223                                 };
 224                         };
 225                 };
 226
 227                 gpu_thermal: gpu-thermal {
 228                         polling-delay-passive = <100>; /* milliseconds */
 229                         polling-delay = <1000>; /* milliseconds */
 230                         thermal-sensors = <&tsadc 1>;
 231                 };
 232         };
 233
 234         xin24m: xin24m {
 235                 compatible = "fixed-clock";
 236                 #clock-cells = <0>;
 237                 clock-frequency = <24000000>;
 238                 clock-output-names = "xin24m";
 239         };
 240
 241         pmu: power-management@ff000000 {
 242                 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
 243                 reg = <0x0 0xff000000 0x0 0x1000>;
 244
 245                 power: power-controller {
 246                         compatible = "rockchip,px30-power-controller";
 247                         #power-domain-cells = <1>;
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250
 251                         /* These power domains are grouped by VD_LOGIC */
 252                         pd_usb@PX30_PD_USB {
 253                                 reg = <PX30_PD_USB>;
 254                                 clocks = <&cru HCLK_HOST>,
 255                                          <&cru HCLK_OTG>,
 256                                          <&cru SCLK_OTG_ADP>;
 257                                 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
 258                         };
 259                         pd_sdcard@PX30_PD_SDCARD {
 260                                 reg = <PX30_PD_SDCARD>;
 261                                 clocks = <&cru HCLK_SDMMC>,
 262                                          <&cru SCLK_SDMMC>;
 263                                 pm_qos = <&qos_sdmmc>;
 264                         };
 265                         pd_gmac@PX30_PD_GMAC {
 266                                 reg = <PX30_PD_GMAC>;
 267                                 clocks = <&cru ACLK_GMAC>,
 268                                          <&cru PCLK_GMAC>,
 269                                          <&cru SCLK_MAC_REF>,
 270                                          <&cru SCLK_GMAC_RX_TX>;
 271                                 pm_qos = <&qos_gmac>;
 272                         };
 273                         pd_mmc_nand@PX30_PD_MMC_NAND {
 274                                 reg = <PX30_PD_MMC_NAND>;
 275                                 clocks =  <&cru HCLK_NANDC>,
 276                                           <&cru HCLK_EMMC>,
 277                                           <&cru HCLK_SDIO>,
 278                                           <&cru HCLK_SFC>,
 279                                           <&cru SCLK_EMMC>,
 280                                           <&cru SCLK_NANDC>,
 281                                           <&cru SCLK_SDIO>,
 282                                           <&cru SCLK_SFC>;
 283                                 pm_qos = <&qos_emmc>, <&qos_nand>,
 284                                          <&qos_sdio>, <&qos_sfc>;
 285                         };
 286                         pd_vpu@PX30_PD_VPU {
 287                                 reg = <PX30_PD_VPU>;
 288                                 clocks = <&cru ACLK_VPU>,
 289                                          <&cru HCLK_VPU>,
 290                                          <&cru SCLK_CORE_VPU>;
 291                                 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
 292                         };
 293                         pd_vo@PX30_PD_VO {
 294                                 reg = <PX30_PD_VO>;
 295                                 clocks = <&cru ACLK_RGA>,
 296                                          <&cru ACLK_VOPB>,
 297                                          <&cru ACLK_VOPL>,
 298                                          <&cru DCLK_VOPB>,
 299                                          <&cru DCLK_VOPL>,
 300                                          <&cru HCLK_RGA>,
 301                                          <&cru HCLK_VOPB>,
 302                                          <&cru HCLK_VOPL>,
 303                                          <&cru PCLK_MIPI_DSI>,
 304                                          <&cru SCLK_RGA_CORE>,
 305                                          <&cru SCLK_VOPB_PWM>;
 306                                 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
 307                                          <&qos_vop_m0>, <&qos_vop_m1>;
 308                         };
 309                         pd_vi@PX30_PD_VI {
 310                                 reg = <PX30_PD_VI>;
 311                                 clocks = <&cru ACLK_CIF>,
 312                                          <&cru ACLK_ISP>,
 313                                          <&cru HCLK_CIF>,
 314                                          <&cru HCLK_ISP>,
 315                                          <&cru SCLK_ISP>;
 316                                 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
 317                                          <&qos_isp_wr>, <&qos_isp_m1>,
 318                                          <&qos_vip>;
 319                         };
 320                         pd_gpu@PX30_PD_GPU {
 321                                 reg = <PX30_PD_GPU>;
 322                                 clocks = <&cru SCLK_GPU>;
 323                                 pm_qos = <&qos_gpu>;
 324                         };
 325                 };
 326         };
 327
 328         pmugrf: syscon@ff010000 {
 329                 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
 330                 reg = <0x0 0xff010000 0x0 0x1000>;
 331                 #address-cells = <1>;
 332                 #size-cells = <1>;
 333
 334                 pmu_io_domains: io-domains {
 335                         compatible = "rockchip,px30-pmu-io-voltage-domain";
 336                         status = "disabled";
 337                 };
 338
 339                 reboot-mode {
 340                         compatible = "syscon-reboot-mode";
 341                         offset = <0x200>;
 342                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 343                         mode-fastboot = <BOOT_FASTBOOT>;
 344                         mode-loader = <BOOT_BL_DOWNLOAD>;
 345                         mode-normal = <BOOT_NORMAL>;
 346                         mode-recovery = <BOOT_RECOVERY>;
 347                 };
 348         };
 349
 350         uart0: serial@ff030000 {
 351                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 352                 reg = <0x0 0xff030000 0x0 0x100>;
 353                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
 355                 clock-names = "baudclk", "apb_pclk";
 356                 dmas = <&dmac 0>, <&dmac 1>;
 357                 dma-names = "tx", "rx";
 358                 reg-shift = <2>;
 359                 reg-io-width = <4>;
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 362                 status = "disabled";
 363         };
 364
 365         i2s1_2ch: i2s@ff070000 {
 366                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 367                 reg = <0x0 0xff070000 0x0 0x1000>;
 368                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 369                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
 370                 clock-names = "i2s_clk", "i2s_hclk";
 371                 dmas = <&dmac 18>, <&dmac 19>;
 372                 dma-names = "tx", "rx";
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
 375                              &i2s1_2ch_sdi &i2s1_2ch_sdo>;
 376                 #sound-dai-cells = <0>;
 377                 status = "disabled";
 378         };
 379
 380         i2s2_2ch: i2s@ff080000 {
 381                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
 382                 reg = <0x0 0xff080000 0x0 0x1000>;
 383                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 384                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
 385                 clock-names = "i2s_clk", "i2s_hclk";
 386                 dmas = <&dmac 20>, <&dmac 21>;
 387                 dma-names = "tx", "rx";
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
 390                              &i2s2_2ch_sdi &i2s2_2ch_sdo>;
 391                 #sound-dai-cells = <0>;
 392                 status = "disabled";
 393         };
 394
 395         gic: interrupt-controller@ff131000 {
 396                 compatible = "arm,gic-400";
 397                 #interrupt-cells = <3>;
 398                 #address-cells = <0>;
 399                 interrupt-controller;
 400                 reg = <0x0 0xff131000 0 0x1000>,
 401                       <0x0 0xff132000 0 0x2000>,
 402                       <0x0 0xff134000 0 0x2000>,
 403                       <0x0 0xff136000 0 0x2000>;
 404                 interrupts = <GIC_PPI 9
 405                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 406         };
 407
 408         grf: syscon@ff140000 {
 409                 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
 410                 reg = <0x0 0xff140000 0x0 0x1000>;
 411                 #address-cells = <1>;
 412                 #size-cells = <1>;
 413
 414                 io_domains: io-domains {
 415                         compatible = "rockchip,px30-io-voltage-domain";
 416                         status = "disabled";
 417                 };
 418
 419                 lvds: lvds {
 420                         compatible = "rockchip,px30-lvds";
 421                         phys = <&dsi_dphy>;
 422                         phy-names = "dphy";
 423                         rockchip,grf = <&grf>;
 424                         rockchip,output = "lvds";
 425                         status = "disabled";
 426
 427                         ports {
 428                                 #address-cells = <1>;
 429                                 #size-cells = <0>;
 430
 431                                 port@0 {
 432                                         reg = <0>;
 433                                         #address-cells = <1>;
 434                                         #size-cells = <0>;
 435
 436                                         lvds_vopb_in: endpoint@0 {
 437                                                 reg = <0>;
 438                                                 remote-endpoint = <&vopb_out_lvds>;
 439                                         };
 440
 441                                         lvds_vopl_in: endpoint@1 {
 442                                                 reg = <1>;
 443                                                 remote-endpoint = <&vopl_out_lvds>;
 444                                         };
 445                                 };
 446                         };
 447                 };
 448         };
 449
 450         uart1: serial@ff158000 {
 451                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 452                 reg = <0x0 0xff158000 0x0 0x100>;
 453                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 455                 clock-names = "baudclk", "apb_pclk";
 456                 dmas = <&dmac 2>, <&dmac 3>;
 457                 dma-names = "tx", "rx";
 458                 reg-shift = <2>;
 459                 reg-io-width = <4>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 462                 status = "disabled";
 463         };
 464
 465         uart2: serial@ff160000 {
 466                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 467                 reg = <0x0 0xff160000 0x0 0x100>;
 468                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 469                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 470                 clock-names = "baudclk", "apb_pclk";
 471                 dmas = <&dmac 4>, <&dmac 5>;
 472                 dma-names = "tx", "rx";
 473                 reg-shift = <2>;
 474                 reg-io-width = <4>;
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&uart2m0_xfer>;
 477                 status = "disabled";
 478         };
 479
 480         uart3: serial@ff168000 {
 481                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 482                 reg = <0x0 0xff168000 0x0 0x100>;
 483                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 484                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 485                 clock-names = "baudclk", "apb_pclk";
 486                 dmas = <&dmac 6>, <&dmac 7>;
 487                 dma-names = "tx", "rx";
 488                 reg-shift = <2>;
 489                 reg-io-width = <4>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
 492                 status = "disabled";
 493         };
 494
 495         uart4: serial@ff170000 {
 496                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 497                 reg = <0x0 0xff170000 0x0 0x100>;
 498                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 499                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 500                 clock-names = "baudclk", "apb_pclk";
 501                 dmas = <&dmac 8>, <&dmac 9>;
 502                 dma-names = "tx", "rx";
 503                 reg-shift = <2>;
 504                 reg-io-width = <4>;
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 507                 status = "disabled";
 508         };
 509
 510         uart5: serial@ff178000 {
 511                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
 512                 reg = <0x0 0xff178000 0x0 0x100>;
 513                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 514                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 515                 clock-names = "baudclk", "apb_pclk";
 516                 dmas = <&dmac 10>, <&dmac 11>;
 517                 dma-names = "tx", "rx";
 518                 reg-shift = <2>;
 519                 reg-io-width = <4>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
 522                 status = "disabled";
 523         };
 524
 525         i2c0: i2c@ff180000 {
 526                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 527                 reg = <0x0 0xff180000 0x0 0x1000>;
 528                 clocks =  <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 529                 clock-names = "i2c", "pclk";
 530                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 531                 pinctrl-names = "default";
 532                 pinctrl-0 = <&i2c0_xfer>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 status = "disabled";
 536         };
 537
 538         i2c1: i2c@ff190000 {
 539                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 540                 reg = <0x0 0xff190000 0x0 0x1000>;
 541                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 542                 clock-names = "i2c", "pclk";
 543                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&i2c1_xfer>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 status = "disabled";
 549         };
 550
 551         i2c2: i2c@ff1a0000 {
 552                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 553                 reg = <0x0 0xff1a0000 0x0 0x1000>;
 554                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 555                 clock-names = "i2c", "pclk";
 556                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&i2c2_xfer>;
 559                 #address-cells = <1>;
 560                 #size-cells = <0>;
 561                 status = "disabled";
 562         };
 563
 564         i2c3: i2c@ff1b0000 {
 565                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
 566                 reg = <0x0 0xff1b0000 0x0 0x1000>;
 567                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 568                 clock-names = "i2c", "pclk";
 569                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 570                 pinctrl-names = "default";
 571                 pinctrl-0 = <&i2c3_xfer>;
 572                 #address-cells = <1>;
 573                 #size-cells = <0>;
 574                 status = "disabled";
 575         };
 576
 577         spi0: spi@ff1d0000 {
 578                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 579                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 580                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 581                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 582                 clock-names = "spiclk", "apb_pclk";
 583                 dmas = <&dmac 12>, <&dmac 13>;
 584                 dma-names = "tx", "rx";
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         spi1: spi@ff1d8000 {
 593                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
 594                 reg = <0x0 0xff1d8000 0x0 0x1000>;
 595                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 596                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 597                 clock-names = "spiclk", "apb_pclk";
 598                 dmas = <&dmac 14>, <&dmac 15>;
 599                 dma-names = "tx", "rx";
 600                 pinctrl-names = "default";
 601                 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 status = "disabled";
 605         };
 606
 607         wdt: watchdog@ff1e0000 {
 608                 compatible = "snps,dw-wdt";
 609                 reg = <0x0 0xff1e0000 0x0 0x100>;
 610                 clocks = <&cru PCLK_WDT_NS>;
 611                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 612                 status = "disabled";
 613         };
 614
 615         pwm0: pwm@ff200000 {
 616                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 617                 reg = <0x0 0xff200000 0x0 0x10>;
 618                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 619                 clock-names = "pwm", "pclk";
 620                 pinctrl-names = "default";
 621                 pinctrl-0 = <&pwm0_pin>;
 622                 #pwm-cells = <3>;
 623                 status = "disabled";
 624         };
 625
 626         pwm1: pwm@ff200010 {
 627                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 628                 reg = <0x0 0xff200010 0x0 0x10>;
 629                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 630                 clock-names = "pwm", "pclk";
 631                 pinctrl-names = "default";
 632                 pinctrl-0 = <&pwm1_pin>;
 633                 #pwm-cells = <3>;
 634                 status = "disabled";
 635         };
 636
 637         pwm2: pwm@ff200020 {
 638                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 639                 reg = <0x0 0xff200020 0x0 0x10>;
 640                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 641                 clock-names = "pwm", "pclk";
 642                 pinctrl-names = "default";
 643                 pinctrl-0 = <&pwm2_pin>;
 644                 #pwm-cells = <3>;
 645                 status = "disabled";
 646         };
 647
 648         pwm3: pwm@ff200030 {
 649                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 650                 reg = <0x0 0xff200030 0x0 0x10>;
 651                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
 652                 clock-names = "pwm", "pclk";
 653                 pinctrl-names = "default";
 654                 pinctrl-0 = <&pwm3_pin>;
 655                 #pwm-cells = <3>;
 656                 status = "disabled";
 657         };
 658
 659         pwm4: pwm@ff208000 {
 660                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 661                 reg = <0x0 0xff208000 0x0 0x10>;
 662                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 663                 clock-names = "pwm", "pclk";
 664                 pinctrl-names = "default";
 665                 pinctrl-0 = <&pwm4_pin>;
 666                 #pwm-cells = <3>;
 667                 status = "disabled";
 668         };
 669
 670         pwm5: pwm@ff208010 {
 671                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 672                 reg = <0x0 0xff208010 0x0 0x10>;
 673                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 674                 clock-names = "pwm", "pclk";
 675                 pinctrl-names = "default";
 676                 pinctrl-0 = <&pwm5_pin>;
 677                 #pwm-cells = <3>;
 678                 status = "disabled";
 679         };
 680
 681         pwm6: pwm@ff208020 {
 682                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 683                 reg = <0x0 0xff208020 0x0 0x10>;
 684                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 685                 clock-names = "pwm", "pclk";
 686                 pinctrl-names = "default";
 687                 pinctrl-0 = <&pwm6_pin>;
 688                 #pwm-cells = <3>;
 689                 status = "disabled";
 690         };
 691
 692         pwm7: pwm@ff208030 {
 693                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
 694                 reg = <0x0 0xff208030 0x0 0x10>;
 695                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
 696                 clock-names = "pwm", "pclk";
 697                 pinctrl-names = "default";
 698                 pinctrl-0 = <&pwm7_pin>;
 699                 #pwm-cells = <3>;
 700                 status = "disabled";
 701         };
 702
 703         rktimer: timer@ff210000 {
 704                 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
 705                 reg = <0x0 0xff210000 0x0 0x1000>;
 706                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 707                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 708                 clock-names = "pclk", "timer";
 709         };
 710
 711         amba {
 712                 compatible = "simple-bus";
 713                 #address-cells = <2>;
 714                 #size-cells = <2>;
 715                 ranges;
 716
 717                 dmac: dmac@ff240000 {
 718                         compatible = "arm,pl330", "arm,primecell";
 719                         reg = <0x0 0xff240000 0x0 0x4000>;
 720                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 721                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 722                         clocks = <&cru ACLK_DMAC>;
 723                         clock-names = "apb_pclk";
 724                         #dma-cells = <1>;
 725                 };
 726         };
 727
 728         tsadc: tsadc@ff280000 {
 729                 compatible = "rockchip,px30-tsadc";
 730                 reg = <0x0 0xff280000 0x0 0x100>;
 731                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 732                 assigned-clocks = <&cru SCLK_TSADC>;
 733                 assigned-clock-rates = <50000>;
 734                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 735                 clock-names = "tsadc", "apb_pclk";
 736                 resets = <&cru SRST_TSADC>;
 737                 reset-names = "tsadc-apb";
 738                 rockchip,grf = <&grf>;
 739                 rockchip,hw-tshut-temp = <120000>;
 740                 pinctrl-names = "init", "default", "sleep";
 741                 pinctrl-0 = <&tsadc_otp_gpio>;
 742                 pinctrl-1 = <&tsadc_otp_out>;
 743                 pinctrl-2 = <&tsadc_otp_gpio>;
 744                 #thermal-sensor-cells = <1>;
 745                 status = "disabled";
 746         };
 747
 748         saradc: saradc@ff288000 {
 749                 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
 750                 reg = <0x0 0xff288000 0x0 0x100>;
 751                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 752                 #io-channel-cells = <1>;
 753                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 754                 clock-names = "saradc", "apb_pclk";
 755                 resets = <&cru SRST_SARADC_P>;
 756                 reset-names = "saradc-apb";
 757                 status = "disabled";
 758         };
 759
 760         otp: nvmem@ff290000 {
 761                 compatible = "rockchip,px30-otp";
 762                 reg = <0x0 0xff290000 0x0 0x4000>;
 763                 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
 764                          <&cru PCLK_OTP_PHY>;
 765                 clock-names = "otp", "apb_pclk", "phy";
 766                 resets = <&cru SRST_OTP_PHY>;
 767                 reset-names = "phy";
 768                 #address-cells = <1>;
 769                 #size-cells = <1>;
 770
 771                 /* Data cells */
 772                 cpu_id: id@7 {
 773                         reg = <0x07 0x10>;
 774                 };
 775                 cpu_leakage: cpu-leakage@17 {
 776                         reg = <0x17 0x1>;
 777                 };
 778                 performance: performance@1e {
 779                         reg = <0x1e 0x1>;
 780                         bits = <4 3>;
 781                 };
 782         };
 783
 784         cru: clock-controller@ff2b0000 {
 785                 compatible = "rockchip,px30-cru";
 786                 reg = <0x0 0xff2b0000 0x0 0x1000>;
 787                 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
 788                 clock-names = "xin24m", "gpll";
 789                 rockchip,grf = <&grf>;
 790                 #clock-cells = <1>;
 791                 #reset-cells = <1>;
 792         };
 793
 794         pmucru: clock-controller@ff2bc000 {
 795                 compatible = "rockchip,px30-pmucru";
 796                 reg = <0x0 0xff2bc000 0x0 0x1000>;
 797                 clocks = <&xin24m>;
 798                 clock-names = "xin24m";
 799                 rockchip,grf = <&grf>;
 800                 #clock-cells = <1>;
 801                 #reset-cells = <1>;
 802         };
 803
 804         usb2phy_grf: syscon@ff2c0000 {
 805                 compatible = "rockchip,px30-usb2phy-grf", "syscon",
 806                              "simple-mfd";
 807                 reg = <0x0 0xff2c0000 0x0 0x10000>;
 808                 #address-cells = <1>;
 809                 #size-cells = <1>;
 810
 811                 u2phy: usb2-phy@100 {
 812                         compatible = "rockchip,px30-usb2phy";
 813                         reg = <0x100 0x20>;
 814                         clocks = <&pmucru SCLK_USBPHY_REF>;
 815                         clock-names = "phyclk";
 816                         #clock-cells = <0>;
 817                         assigned-clocks = <&cru USB480M>;
 818                         assigned-clock-parents = <&u2phy>;
 819                         clock-output-names = "usb480m_phy";
 820                         status = "disabled";
 821
 822                         u2phy_host: host-port {
 823                                 #phy-cells = <0>;
 824                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 825                                 interrupt-names = "linestate";
 826                                 status = "disabled";
 827                         };
 828
 829                         u2phy_otg: otg-port {
 830                                 #phy-cells = <0>;
 831                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 832                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 833                                              <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 834                                 interrupt-names = "otg-bvalid", "otg-id",
 835                                                   "linestate";
 836                                 status = "disabled";
 837                         };
 838                 };
 839         };
 840
 841         dsi_dphy: phy@ff2e0000 {
 842                 compatible = "rockchip,px30-dsi-dphy";
 843                 reg = <0x0 0xff2e0000 0x0 0x10000>;
 844                 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
 845                 clock-names = "ref", "pclk";
 846                 resets = <&cru SRST_MIPIDSIPHY_P>;
 847                 reset-names = "apb";
 848                 #phy-cells = <0>;
 849                 power-domains = <&power PX30_PD_VO>;
 850                 status = "disabled";
 851         };
 852
 853         usb20_otg: usb@ff300000 {
 854                 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
 855                              "snps,dwc2";
 856                 reg = <0x0 0xff300000 0x0 0x40000>;
 857                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 858                 clocks = <&cru HCLK_OTG>;
 859                 clock-names = "otg";
 860                 dr_mode = "otg";
 861                 g-np-tx-fifo-size = <16>;
 862                 g-rx-fifo-size = <280>;
 863                 g-tx-fifo-size = <256 128 128 64 32 16>;
 864                 g-use-dma;
 865                 phys = <&u2phy_otg>;
 866                 phy-names = "usb2-phy";
 867                 power-domains = <&power PX30_PD_USB>;
 868                 status = "disabled";
 869         };
 870
 871         usb_host0_ehci: usb@ff340000 {
 872                 compatible = "generic-ehci";
 873                 reg = <0x0 0xff340000 0x0 0x10000>;
 874                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 875                 clocks = <&cru HCLK_HOST>;
 876                 clock-names = "usbhost";
 877                 phys = <&u2phy_host>;
 878                 phy-names = "usb";
 879                 power-domains = <&power PX30_PD_USB>;
 880                 status = "disabled";
 881         };
 882
 883         usb_host0_ohci: usb@ff350000 {
 884                 compatible = "generic-ohci";
 885                 reg = <0x0 0xff350000 0x0 0x10000>;
 886                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 887                 clocks = <&cru HCLK_HOST>;
 888                 clock-names = "usbhost";
 889                 phys = <&u2phy_host>;
 890                 phy-names = "usb";
 891                 power-domains = <&power PX30_PD_USB>;
 892                 status = "disabled";
 893         };
 894
 895         gmac: ethernet@ff360000 {
 896                 compatible = "rockchip,px30-gmac";
 897                 reg = <0x0 0xff360000 0x0 0x10000>;
 898                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 899                 interrupt-names = "macirq";
 900                 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
 901                          <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
 902                          <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 903                          <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
 904                 clock-names = "stmmaceth", "mac_clk_rx",
 905                               "mac_clk_tx", "clk_mac_ref",
 906                               "clk_mac_refout", "aclk_mac",
 907                               "pclk_mac", "clk_mac_speed";
 908                 rockchip,grf = <&grf>;
 909                 phy-mode = "rmii";
 910                 pinctrl-names = "default";
 911                 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
 912                 power-domains = <&power PX30_PD_GMAC>;
 913                 resets = <&cru SRST_GMAC_A>;
 914                 reset-names = "stmmaceth";
 915                 status = "disabled";
 916         };
 917
 918         sdmmc: dwmmc@ff370000 {
 919                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 920                 reg = <0x0 0xff370000 0x0 0x4000>;
 921                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 922                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 923                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 924                 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
 925                 fifo-depth = <0x100>;
 926                 max-frequency = <150000000>;
 927                 pinctrl-names = "default";
 928                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
 929                 power-domains = <&power PX30_PD_SDCARD>;
 930                 status = "disabled";
 931         };
 932
 933         sdio: dwmmc@ff380000 {
 934                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 935                 reg = <0x0 0xff380000 0x0 0x4000>;
 936                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 937                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 938                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 939                 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
 940                 fifo-depth = <0x100>;
 941                 max-frequency = <150000000>;
 942                 pinctrl-names = "default";
 943                 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
 944                 power-domains = <&power PX30_PD_MMC_NAND>;
 945                 status = "disabled";
 946         };
 947
 948         emmc: dwmmc@ff390000 {
 949                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
 950                 reg = <0x0 0xff390000 0x0 0x4000>;
 951                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 952                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 953                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 954                 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
 955                 fifo-depth = <0x100>;
 956                 max-frequency = <150000000>;
 957                 pinctrl-names = "default";
 958                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 959                 power-domains = <&power PX30_PD_MMC_NAND>;
 960                 status = "disabled";
 961         };
 962
 963         gpu: gpu@ff400000 {
 964                 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
 965                 reg = <0x0 0xff400000 0x0 0x4000>;
 966                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 967                              <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 968                              <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 969                 interrupt-names = "job", "mmu", "gpu";
 970                 clocks = <&cru SCLK_GPU>;
 971                 #cooling-cells = <2>;
 972                 power-domains = <&power PX30_PD_GPU>;
 973                 status = "disabled";
 974         };
 975
 976         dsi: dsi@ff450000 {
 977                 compatible = "rockchip,px30-mipi-dsi";
 978                 reg = <0x0 0xff450000 0x0 0x10000>;
 979                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 980                 clocks = <&cru PCLK_MIPI_DSI>;
 981                 clock-names = "pclk";
 982                 phys = <&dsi_dphy>;
 983                 phy-names = "dphy";
 984                 power-domains = <&power PX30_PD_VO>;
 985                 resets = <&cru SRST_MIPIDSI_HOST_P>;
 986                 reset-names = "apb";
 987                 rockchip,grf = <&grf>;
 988                 #address-cells = <1>;
 989                 #size-cells = <0>;
 990                 status = "disabled";
 991
 992                 ports {
 993                         #address-cells = <1>;
 994                         #size-cells = <0>;
 995
 996                         port@0 {
 997                                 reg = <0>;
 998                                 #address-cells = <1>;
 999                                 #size-cells = <0>;
1000
1001                                 dsi_in_vopb: endpoint@0 {
1002                                         reg = <0>;
1003                                         remote-endpoint = <&vopb_out_dsi>;
1004                                 };
1005
1006                                 dsi_in_vopl: endpoint@1 {
1007                                         reg = <1>;
1008                                         remote-endpoint = <&vopl_out_dsi>;
1009                                 };
1010                         };
1011                 };
1012         };
1013
1014         vopb: vop@ff460000 {
1015                 compatible = "rockchip,px30-vop-big";
1016                 reg = <0x0 0xff460000 0x0 0xefc>;
1017                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1018                 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1019                          <&cru HCLK_VOPB>;
1020                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1021                 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1022                 reset-names = "axi", "ahb", "dclk";
1023                 iommus = <&vopb_mmu>;
1024                 power-domains = <&power PX30_PD_VO>;
1025                 rockchip,grf = <&grf>;
1026                 status = "disabled";
1027
1028                 vopb_out: port {
1029                         #address-cells = <1>;
1030                         #size-cells = <0>;
1031
1032                         vopb_out_dsi: endpoint@0 {
1033                                 reg = <0>;
1034                                 remote-endpoint = <&dsi_in_vopb>;
1035                         };
1036
1037                         vopb_out_lvds: endpoint@1 {
1038                                 reg = <1>;
1039                                 remote-endpoint = <&lvds_vopb_in>;
1040                         };
1041                 };
1042         };
1043
1044         vopb_mmu: iommu@ff460f00 {
1045                 compatible = "rockchip,iommu";
1046                 reg = <0x0 0xff460f00 0x0 0x100>;
1047                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1048                 interrupt-names = "vopb_mmu";
1049                 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1050                 clock-names = "aclk", "iface";
1051                 power-domains = <&power PX30_PD_VO>;
1052                 #iommu-cells = <0>;
1053                 status = "disabled";
1054         };
1055
1056         vopl: vop@ff470000 {
1057                 compatible = "rockchip,px30-vop-lit";
1058                 reg = <0x0 0xff470000 0x0 0xefc>;
1059                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1060                 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1061                          <&cru HCLK_VOPL>;
1062                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1063                 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1064                 reset-names = "axi", "ahb", "dclk";
1065                 iommus = <&vopl_mmu>;
1066                 power-domains = <&power PX30_PD_VO>;
1067                 rockchip,grf = <&grf>;
1068                 status = "disabled";
1069
1070                 vopl_out: port {
1071                         #address-cells = <1>;
1072                         #size-cells = <0>;
1073
1074                         vopl_out_dsi: endpoint@0 {
1075                                 reg = <0>;
1076                                 remote-endpoint = <&dsi_in_vopl>;
1077                         };
1078
1079                         vopl_out_lvds: endpoint@1 {
1080                                 reg = <1>;
1081                                 remote-endpoint = <&lvds_vopl_in>;
1082                         };
1083                 };
1084         };
1085
1086         vopl_mmu: iommu@ff470f00 {
1087                 compatible = "rockchip,iommu";
1088                 reg = <0x0 0xff470f00 0x0 0x100>;
1089                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1090                 interrupt-names = "vopl_mmu";
1091                 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1092                 clock-names = "aclk", "iface";
1093                 power-domains = <&power PX30_PD_VO>;
1094                 #iommu-cells = <0>;
1095                 status = "disabled";
1096         };
1097
1098         qos_gmac: qos@ff518000 {
1099                 compatible = "syscon";
1100                 reg = <0x0 0xff518000 0x0 0x20>;
1101         };
1102
1103         qos_gpu: qos@ff520000 {
1104                 compatible = "syscon";
1105                 reg = <0x0 0xff520000 0x0 0x20>;
1106         };
1107
1108         qos_sdmmc: qos@ff52c000 {
1109                 compatible = "syscon";
1110                 reg = <0x0 0xff52c000 0x0 0x20>;
1111         };
1112
1113         qos_emmc: qos@ff538000 {
1114                 compatible = "syscon";
1115                 reg = <0x0 0xff538000 0x0 0x20>;
1116         };
1117
1118         qos_nand: qos@ff538080 {
1119                 compatible = "syscon";
1120                 reg = <0x0 0xff538080 0x0 0x20>;
1121         };
1122
1123         qos_sdio: qos@ff538100 {
1124                 compatible = "syscon";
1125                 reg = <0x0 0xff538100 0x0 0x20>;
1126         };
1127
1128         qos_sfc: qos@ff538180 {
1129                 compatible = "syscon";
1130                 reg = <0x0 0xff538180 0x0 0x20>;
1131         };
1132
1133         qos_usb_host: qos@ff540000 {
1134                 compatible = "syscon";
1135                 reg = <0x0 0xff540000 0x0 0x20>;
1136         };
1137
1138         qos_usb_otg: qos@ff540080 {
1139                 compatible = "syscon";
1140                 reg = <0x0 0xff540080 0x0 0x20>;
1141         };
1142
1143         qos_isp_128: qos@ff548000 {
1144                 compatible = "syscon";
1145                 reg = <0x0 0xff548000 0x0 0x20>;
1146         };
1147
1148         qos_isp_rd: qos@ff548080 {
1149                 compatible = "syscon";
1150                 reg = <0x0 0xff548080 0x0 0x20>;
1151         };
1152
1153         qos_isp_wr: qos@ff548100 {
1154                 compatible = "syscon";
1155                 reg = <0x0 0xff548100 0x0 0x20>;
1156         };
1157
1158         qos_isp_m1: qos@ff548180 {
1159                 compatible = "syscon";
1160                 reg = <0x0 0xff548180 0x0 0x20>;
1161         };
1162
1163         qos_vip: qos@ff548200 {
1164                 compatible = "syscon";
1165                 reg = <0x0 0xff548200 0x0 0x20>;
1166         };
1167
1168         qos_rga_rd: qos@ff550000 {
1169                 compatible = "syscon";
1170                 reg = <0x0 0xff550000 0x0 0x20>;
1171         };
1172
1173         qos_rga_wr: qos@ff550080 {
1174                 compatible = "syscon";
1175                 reg = <0x0 0xff550080 0x0 0x20>;
1176         };
1177
1178         qos_vop_m0: qos@ff550100 {
1179                 compatible = "syscon";
1180                 reg = <0x0 0xff550100 0x0 0x20>;
1181         };
1182
1183         qos_vop_m1: qos@ff550180 {
1184                 compatible = "syscon";
1185                 reg = <0x0 0xff550180 0x0 0x20>;
1186         };
1187
1188         qos_vpu: qos@ff558000 {
1189                 compatible = "syscon";
1190                 reg = <0x0 0xff558000 0x0 0x20>;
1191         };
1192
1193         qos_vpu_r128: qos@ff558080 {
1194                 compatible = "syscon";
1195                 reg = <0x0 0xff558080 0x0 0x20>;
1196         };
1197
1198         pinctrl: pinctrl {
1199                 compatible = "rockchip,px30-pinctrl";
1200                 rockchip,grf = <&grf>;
1201                 rockchip,pmu = <&pmugrf>;
1202                 #address-cells = <2>;
1203                 #size-cells = <2>;
1204                 ranges;
1205
1206                 gpio0: gpio0@ff040000 {
1207                         compatible = "rockchip,gpio-bank";
1208                         reg = <0x0 0xff040000 0x0 0x100>;
1209                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1210                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1211                         gpio-controller;
1212                         #gpio-cells = <2>;
1213
1214                         interrupt-controller;
1215                         #interrupt-cells = <2>;
1216                 };
1217
1218                 gpio1: gpio1@ff250000 {
1219                         compatible = "rockchip,gpio-bank";
1220                         reg = <0x0 0xff250000 0x0 0x100>;
1221                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1222                         clocks = <&cru PCLK_GPIO1>;
1223                         gpio-controller;
1224                         #gpio-cells = <2>;
1225
1226                         interrupt-controller;
1227                         #interrupt-cells = <2>;
1228                 };
1229
1230                 gpio2: gpio2@ff260000 {
1231                         compatible = "rockchip,gpio-bank";
1232                         reg = <0x0 0xff260000 0x0 0x100>;
1233                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1234                         clocks = <&cru PCLK_GPIO2>;
1235                         gpio-controller;
1236                         #gpio-cells = <2>;
1237
1238                         interrupt-controller;
1239                         #interrupt-cells = <2>;
1240                 };
1241
1242                 gpio3: gpio3@ff270000 {
1243                         compatible = "rockchip,gpio-bank";
1244                         reg = <0x0 0xff270000 0x0 0x100>;
1245                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1246                         clocks = <&cru PCLK_GPIO3>;
1247                         gpio-controller;
1248                         #gpio-cells = <2>;
1249
1250                         interrupt-controller;
1251                         #interrupt-cells = <2>;
1252                 };
1253
1254                 pcfg_pull_up: pcfg-pull-up {
1255                         bias-pull-up;
1256                 };
1257
1258                 pcfg_pull_down: pcfg-pull-down {
1259                         bias-pull-down;
1260                 };
1261
1262                 pcfg_pull_none: pcfg-pull-none {
1263                         bias-disable;
1264                 };
1265
1266                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1267                         bias-disable;
1268                         drive-strength = <2>;
1269                 };
1270
1271                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1272                         bias-pull-up;
1273                         drive-strength = <2>;
1274                 };
1275
1276                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1277                         bias-pull-up;
1278                         drive-strength = <4>;
1279                 };
1280
1281                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1282                         bias-disable;
1283                         drive-strength = <4>;
1284                 };
1285
1286                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1287                         bias-pull-down;
1288                         drive-strength = <4>;
1289                 };
1290
1291                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1292                         bias-disable;
1293                         drive-strength = <8>;
1294                 };
1295
1296                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1297                         bias-pull-up;
1298                         drive-strength = <8>;
1299                 };
1300
1301                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1302                         bias-disable;
1303                         drive-strength = <12>;
1304                 };
1305
1306                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1307                         bias-pull-up;
1308                         drive-strength = <12>;
1309                 };
1310
1311                 pcfg_pull_none_smt: pcfg-pull-none-smt {
1312                         bias-disable;
1313                         input-schmitt-enable;
1314                 };
1315
1316                 pcfg_output_high: pcfg-output-high {
1317                         output-high;
1318                 };
1319
1320                 pcfg_output_low: pcfg-output-low {
1321                         output-low;
1322                 };
1323
1324                 pcfg_input_high: pcfg-input-high {
1325                         bias-pull-up;
1326                         input-enable;
1327                 };
1328
1329                 pcfg_input: pcfg-input {
1330                         input-enable;
1331                 };
1332
1333                 i2c0 {
1334                         i2c0_xfer: i2c0-xfer {
1335                                 rockchip,pins =
1336                                         <0 RK_PB0 1 &pcfg_pull_none_smt>,
1337                                         <0 RK_PB1 1 &pcfg_pull_none_smt>;
1338                         };
1339                 };
1340
1341                 i2c1 {
1342                         i2c1_xfer: i2c1-xfer {
1343                                 rockchip,pins =
1344                                         <0 RK_PC2 1 &pcfg_pull_none_smt>,
1345                                         <0 RK_PC3 1 &pcfg_pull_none_smt>;
1346                         };
1347                 };
1348
1349                 i2c2 {
1350                         i2c2_xfer: i2c2-xfer {
1351                                 rockchip,pins =
1352                                         <2 RK_PB7 2 &pcfg_pull_none_smt>,
1353                                         <2 RK_PC0 2 &pcfg_pull_none_smt>;
1354                         };
1355                 };
1356
1357                 i2c3 {
1358                         i2c3_xfer: i2c3-xfer {
1359                                 rockchip,pins =
1360                                         <1 RK_PB4 4 &pcfg_pull_none_smt>,
1361                                         <1 RK_PB5 4 &pcfg_pull_none_smt>;
1362                         };
1363                 };
1364
1365                 tsadc {
1366                         tsadc_otp_gpio: tsadc-otp-gpio {
1367                                 rockchip,pins =
1368                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1369                         };
1370
1371                         tsadc_otp_out: tsadc-otp-out {
1372                                 rockchip,pins =
1373                                         <0 RK_PA6 1 &pcfg_pull_none>;
1374                         };
1375                 };
1376
1377                 uart0 {
1378                         uart0_xfer: uart0-xfer {
1379                                 rockchip,pins =
1380                                         <0 RK_PB2 1 &pcfg_pull_up>,
1381                                         <0 RK_PB3 1 &pcfg_pull_up>;
1382                         };
1383
1384                         uart0_cts: uart0-cts {
1385                                 rockchip,pins =
1386                                         <0 RK_PB4 1 &pcfg_pull_none>;
1387                         };
1388
1389                         uart0_rts: uart0-rts {
1390                                 rockchip,pins =
1391                                         <0 RK_PB5 1 &pcfg_pull_none>;
1392                         };
1393                 };
1394
1395                 uart1 {
1396                         uart1_xfer: uart1-xfer {
1397                                 rockchip,pins =
1398                                         <1 RK_PC1 1 &pcfg_pull_up>,
1399                                         <1 RK_PC0 1 &pcfg_pull_up>;
1400                         };
1401
1402                         uart1_cts: uart1-cts {
1403                                 rockchip,pins =
1404                                         <1 RK_PC2 1 &pcfg_pull_none>;
1405                         };
1406
1407                         uart1_rts: uart1-rts {
1408                                 rockchip,pins =
1409                                         <1 RK_PC3 1 &pcfg_pull_none>;
1410                         };
1411                 };
1412
1413                 uart2-m0 {
1414                         uart2m0_xfer: uart2m0-xfer {
1415                                 rockchip,pins =
1416                                         <1 RK_PD2 2 &pcfg_pull_up>,
1417                                         <1 RK_PD3 2 &pcfg_pull_up>;
1418                         };
1419                 };
1420
1421                 uart2-m1 {
1422                         uart2m1_xfer: uart2m1-xfer {
1423                                 rockchip,pins =
1424                                         <2 RK_PB4 2 &pcfg_pull_up>,
1425                                         <2 RK_PB6 2 &pcfg_pull_up>;
1426                         };
1427                 };
1428
1429                 uart3-m0 {
1430                         uart3m0_xfer: uart3m0-xfer {
1431                                 rockchip,pins =
1432                                         <0 RK_PC0 2 &pcfg_pull_up>,
1433                                         <0 RK_PC1 2 &pcfg_pull_up>;
1434                         };
1435
1436                         uart3m0_cts: uart3m0-cts {
1437                                 rockchip,pins =
1438                                         <0 RK_PC2 2 &pcfg_pull_none>;
1439                         };
1440
1441                         uart3m0_rts: uart3m0-rts {
1442                                 rockchip,pins =
1443                                         <0 RK_PC3 2 &pcfg_pull_none>;
1444                         };
1445                 };
1446
1447                 uart3-m1 {
1448                         uart3m1_xfer: uart3m1-xfer {
1449                                 rockchip,pins =
1450                                         <1 RK_PB6 2 &pcfg_pull_up>,
1451                                         <1 RK_PB7 2 &pcfg_pull_up>;
1452                         };
1453
1454                         uart3m1_cts: uart3m1-cts {
1455                                 rockchip,pins =
1456                                         <1 RK_PB4 2 &pcfg_pull_none>;
1457                         };
1458
1459                         uart3m1_rts: uart3m1-rts {
1460                                 rockchip,pins =
1461                                         <1 RK_PB5 2 &pcfg_pull_none>;
1462                         };
1463                 };
1464
1465                 uart4 {
1466                         uart4_xfer: uart4-xfer {
1467                                 rockchip,pins =
1468                                         <1 RK_PD4 2 &pcfg_pull_up>,
1469                                         <1 RK_PD5 2 &pcfg_pull_up>;
1470                         };
1471
1472                         uart4_cts: uart4-cts {
1473                                 rockchip,pins =
1474                                         <1 RK_PD6 2 &pcfg_pull_none>;
1475                         };
1476
1477                         uart4_rts: uart4-rts {
1478                                 rockchip,pins =
1479                                         <1 RK_PD7 2 &pcfg_pull_none>;
1480                         };
1481                 };
1482
1483                 uart5 {
1484                         uart5_xfer: uart5-xfer {
1485                                 rockchip,pins =
1486                                         <3 RK_PA2 4 &pcfg_pull_up>,
1487                                         <3 RK_PA1 4 &pcfg_pull_up>;
1488                         };
1489
1490                         uart5_cts: uart5-cts {
1491                                 rockchip,pins =
1492                                         <3 RK_PA3 4 &pcfg_pull_none>;
1493                         };
1494
1495                         uart5_rts: uart5-rts {
1496                                 rockchip,pins =
1497                                         <3 RK_PA5 4 &pcfg_pull_none>;
1498                         };
1499                 };
1500
1501                 spi0 {
1502                         spi0_clk: spi0-clk {
1503                                 rockchip,pins =
1504                                         <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1505                         };
1506
1507                         spi0_csn: spi0-csn {
1508                                 rockchip,pins =
1509                                         <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1510                         };
1511
1512                         spi0_miso: spi0-miso {
1513                                 rockchip,pins =
1514                                         <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1515                         };
1516
1517                         spi0_mosi: spi0-mosi {
1518                                 rockchip,pins =
1519                                         <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1520                         };
1521
1522                         spi0_clk_hs: spi0-clk-hs {
1523                                 rockchip,pins =
1524                                         <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1525                         };
1526
1527                         spi0_miso_hs: spi0-miso-hs {
1528                                 rockchip,pins =
1529                                         <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1530                         };
1531
1532                         spi0_mosi_hs: spi0-mosi-hs {
1533                                 rockchip,pins =
1534                                         <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1535                         };
1536                 };
1537
1538                 spi1 {
1539                         spi1_clk: spi1-clk {
1540                                 rockchip,pins =
1541                                         <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1542                         };
1543
1544                         spi1_csn0: spi1-csn0 {
1545                                 rockchip,pins =
1546                                         <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1547                         };
1548
1549                         spi1_csn1: spi1-csn1 {
1550                                 rockchip,pins =
1551                                         <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1552                         };
1553
1554                         spi1_miso: spi1-miso {
1555                                 rockchip,pins =
1556                                         <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1557                         };
1558
1559                         spi1_mosi: spi1-mosi {
1560                                 rockchip,pins =
1561                                         <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1562                         };
1563
1564                         spi1_clk_hs: spi1-clk-hs {
1565                                 rockchip,pins =
1566                                         <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1567                         };
1568
1569                         spi1_miso_hs: spi1-miso-hs {
1570                                 rockchip,pins =
1571                                         <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1572                         };
1573
1574                         spi1_mosi_hs: spi1-mosi-hs {
1575                                 rockchip,pins =
1576                                         <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1577                         };
1578                 };
1579
1580                 pdm {
1581                         pdm_clk0m0: pdm-clk0m0 {
1582                                 rockchip,pins =
1583                                         <3 RK_PC6 2 &pcfg_pull_none>;
1584                         };
1585
1586                         pdm_clk0m1: pdm-clk0m1 {
1587                                 rockchip,pins =
1588                                         <2 RK_PC6 1 &pcfg_pull_none>;
1589                         };
1590
1591                         pdm_clk1: pdm-clk1 {
1592                                 rockchip,pins =
1593                                         <3 RK_PC7 2 &pcfg_pull_none>;
1594                         };
1595
1596                         pdm_sdi0m0: pdm-sdi0m0 {
1597                                 rockchip,pins =
1598                                         <3 RK_PD3 2 &pcfg_pull_none>;
1599                         };
1600
1601                         pdm_sdi0m1: pdm-sdi0m1 {
1602                                 rockchip,pins =
1603                                         <2 RK_PC5 2 &pcfg_pull_none>;
1604                         };
1605
1606                         pdm_sdi1: pdm-sdi1 {
1607                                 rockchip,pins =
1608                                         <3 RK_PD0 2 &pcfg_pull_none>;
1609                         };
1610
1611                         pdm_sdi2: pdm-sdi2 {
1612                                 rockchip,pins =
1613                                         <3 RK_PD1 2 &pcfg_pull_none>;
1614                         };
1615
1616                         pdm_sdi3: pdm-sdi3 {
1617                                 rockchip,pins =
1618                                         <3 RK_PD2 2 &pcfg_pull_none>;
1619                         };
1620
1621                         pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1622                                 rockchip,pins =
1623                                         <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1624                         };
1625
1626                         pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1627                                 rockchip,pins =
1628                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1629                         };
1630
1631                         pdm_clk1_sleep: pdm-clk1-sleep {
1632                                 rockchip,pins =
1633                                         <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1634                         };
1635
1636                         pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1637                                 rockchip,pins =
1638                                         <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1639                         };
1640
1641                         pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1642                                 rockchip,pins =
1643                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1644                         };
1645
1646                         pdm_sdi1_sleep: pdm-sdi1-sleep {
1647                                 rockchip,pins =
1648                                         <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1649                         };
1650
1651                         pdm_sdi2_sleep: pdm-sdi2-sleep {
1652                                 rockchip,pins =
1653                                         <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1654                         };
1655
1656                         pdm_sdi3_sleep: pdm-sdi3-sleep {
1657                                 rockchip,pins =
1658                                         <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1659                         };
1660                 };
1661
1662                 i2s0 {
1663                         i2s0_8ch_mclk: i2s0-8ch-mclk {
1664                                 rockchip,pins =
1665                                         <3 RK_PC1 2 &pcfg_pull_none>;
1666                         };
1667
1668                         i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1669                                 rockchip,pins =
1670                                         <3 RK_PC3 2 &pcfg_pull_none>;
1671                         };
1672
1673                         i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1674                                 rockchip,pins =
1675                                         <3 RK_PB4 2 &pcfg_pull_none>;
1676                         };
1677
1678                         i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1679                                 rockchip,pins =
1680                                         <3 RK_PC2 2 &pcfg_pull_none>;
1681                         };
1682
1683                         i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1684                                 rockchip,pins =
1685                                         <3 RK_PB5 2 &pcfg_pull_none>;
1686                         };
1687
1688                         i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1689                                 rockchip,pins =
1690                                         <3 RK_PC4 2 &pcfg_pull_none>;
1691                         };
1692
1693                         i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1694                                 rockchip,pins =
1695                                         <3 RK_PC0 2 &pcfg_pull_none>;
1696                         };
1697
1698                         i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1699                                 rockchip,pins =
1700                                         <3 RK_PB7 2 &pcfg_pull_none>;
1701                         };
1702
1703                         i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1704                                 rockchip,pins =
1705                                         <3 RK_PB6 2 &pcfg_pull_none>;
1706                         };
1707
1708                         i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1709                                 rockchip,pins =
1710                                         <3 RK_PC5 2 &pcfg_pull_none>;
1711                         };
1712
1713                         i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1714                                 rockchip,pins =
1715                                         <3 RK_PB3 2 &pcfg_pull_none>;
1716                         };
1717
1718                         i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1719                                 rockchip,pins =
1720                                         <3 RK_PB1 2 &pcfg_pull_none>;
1721                         };
1722
1723                         i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1724                                 rockchip,pins =
1725                                         <3 RK_PB0 2 &pcfg_pull_none>;
1726                         };
1727                 };
1728
1729                 i2s1 {
1730                         i2s1_2ch_mclk: i2s1-2ch-mclk {
1731                                 rockchip,pins =
1732                                         <2 RK_PC3 1 &pcfg_pull_none>;
1733                         };
1734
1735                         i2s1_2ch_sclk: i2s1-2ch-sclk {
1736                                 rockchip,pins =
1737                                         <2 RK_PC2 1 &pcfg_pull_none>;
1738                         };
1739
1740                         i2s1_2ch_lrck: i2s1-2ch-lrck {
1741                                 rockchip,pins =
1742                                         <2 RK_PC1 1 &pcfg_pull_none>;
1743                         };
1744
1745                         i2s1_2ch_sdi: i2s1-2ch-sdi {
1746                                 rockchip,pins =
1747                                         <2 RK_PC5 1 &pcfg_pull_none>;
1748                         };
1749
1750                         i2s1_2ch_sdo: i2s1-2ch-sdo {
1751                                 rockchip,pins =
1752                                         <2 RK_PC4 1 &pcfg_pull_none>;
1753                         };
1754                 };
1755
1756                 i2s2 {
1757                         i2s2_2ch_mclk: i2s2-2ch-mclk {
1758                                 rockchip,pins =
1759                                         <3 RK_PA1 2 &pcfg_pull_none>;
1760                         };
1761
1762                         i2s2_2ch_sclk: i2s2-2ch-sclk {
1763                                 rockchip,pins =
1764                                         <3 RK_PA2 2 &pcfg_pull_none>;
1765                         };
1766
1767                         i2s2_2ch_lrck: i2s2-2ch-lrck {
1768                                 rockchip,pins =
1769                                         <3 RK_PA3 2 &pcfg_pull_none>;
1770                         };
1771
1772                         i2s2_2ch_sdi: i2s2-2ch-sdi {
1773                                 rockchip,pins =
1774                                         <3 RK_PA5 2 &pcfg_pull_none>;
1775                         };
1776
1777                         i2s2_2ch_sdo: i2s2-2ch-sdo {
1778                                 rockchip,pins =
1779                                         <3 RK_PA7 2 &pcfg_pull_none>;
1780                         };
1781                 };
1782
1783                 sdmmc {
1784                         sdmmc_clk: sdmmc-clk {
1785                                 rockchip,pins =
1786                                         <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1787                         };
1788
1789                         sdmmc_cmd: sdmmc-cmd {
1790                                 rockchip,pins =
1791                                         <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1792                         };
1793
1794                         sdmmc_det: sdmmc-det {
1795                                 rockchip,pins =
1796                                         <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1797                         };
1798
1799                         sdmmc_bus1: sdmmc-bus1 {
1800                                 rockchip,pins =
1801                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1802                         };
1803
1804                         sdmmc_bus4: sdmmc-bus4 {
1805                                 rockchip,pins =
1806                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1807                                         <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1808                                         <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1809                                         <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1810                         };
1811                 };
1812
1813                 sdio {
1814                         sdio_clk: sdio-clk {
1815                                 rockchip,pins =
1816                                         <1 RK_PC5 1 &pcfg_pull_none>;
1817                         };
1818
1819                         sdio_cmd: sdio-cmd {
1820                                 rockchip,pins =
1821                                         <1 RK_PC4 1 &pcfg_pull_up>;
1822                         };
1823
1824                         sdio_bus4: sdio-bus4 {
1825                                 rockchip,pins =
1826                                         <1 RK_PC6 1 &pcfg_pull_up>,
1827                                         <1 RK_PC7 1 &pcfg_pull_up>,
1828                                         <1 RK_PD0 1 &pcfg_pull_up>,
1829                                         <1 RK_PD1 1 &pcfg_pull_up>;
1830                         };
1831                 };
1832
1833                 emmc {
1834                         emmc_clk: emmc-clk {
1835                                 rockchip,pins =
1836                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>;
1837                         };
1838
1839                         emmc_cmd: emmc-cmd {
1840                                 rockchip,pins =
1841                                         <1 RK_PB2 2 &pcfg_pull_up_8ma>;
1842                         };
1843
1844                         emmc_rstnout: emmc-rstnout {
1845                                 rockchip,pins =
1846                                         <1 RK_PB3 2 &pcfg_pull_none>;
1847                         };
1848
1849                         emmc_bus1: emmc-bus1 {
1850                                 rockchip,pins =
1851                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>;
1852                         };
1853
1854                         emmc_bus4: emmc-bus4 {
1855                                 rockchip,pins =
1856                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1857                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1858                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1859                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>;
1860                         };
1861
1862                         emmc_bus8: emmc-bus8 {
1863                                 rockchip,pins =
1864                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1865                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1866                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1867                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>,
1868                                         <1 RK_PA4 2 &pcfg_pull_up_8ma>,
1869                                         <1 RK_PA5 2 &pcfg_pull_up_8ma>,
1870                                         <1 RK_PA6 2 &pcfg_pull_up_8ma>,
1871                                         <1 RK_PA7 2 &pcfg_pull_up_8ma>;
1872                         };
1873                 };
1874
1875                 flash {
1876                         flash_cs0: flash-cs0 {
1877                                 rockchip,pins =
1878                                         <1 RK_PB0 1 &pcfg_pull_none>;
1879                         };
1880
1881                         flash_rdy: flash-rdy {
1882                                 rockchip,pins =
1883                                         <1 RK_PB1 1 &pcfg_pull_none>;
1884                         };
1885
1886                         flash_dqs: flash-dqs {
1887                                 rockchip,pins =
1888                                         <1 RK_PB2 1 &pcfg_pull_none>;
1889                         };
1890
1891                         flash_ale: flash-ale {
1892                                 rockchip,pins =
1893                                         <1 RK_PB3 1 &pcfg_pull_none>;
1894                         };
1895
1896                         flash_cle: flash-cle {
1897                                 rockchip,pins =
1898                                         <1 RK_PB4 1 &pcfg_pull_none>;
1899                         };
1900
1901                         flash_wrn: flash-wrn {
1902                                 rockchip,pins =
1903                                         <1 RK_PB5 1 &pcfg_pull_none>;
1904                         };
1905
1906                         flash_csl: flash-csl {
1907                                 rockchip,pins =
1908                                         <1 RK_PB6 1 &pcfg_pull_none>;
1909                         };
1910
1911                         flash_rdn: flash-rdn {
1912                                 rockchip,pins =
1913                                         <1 RK_PB7 1 &pcfg_pull_none>;
1914                         };
1915
1916                         flash_bus8: flash-bus8 {
1917                                 rockchip,pins =
1918                                         <1 RK_PA0 1 &pcfg_pull_up_12ma>,
1919                                         <1 RK_PA1 1 &pcfg_pull_up_12ma>,
1920                                         <1 RK_PA2 1 &pcfg_pull_up_12ma>,
1921                                         <1 RK_PA3 1 &pcfg_pull_up_12ma>,
1922                                         <1 RK_PA4 1 &pcfg_pull_up_12ma>,
1923                                         <1 RK_PA5 1 &pcfg_pull_up_12ma>,
1924                                         <1 RK_PA6 1 &pcfg_pull_up_12ma>,
1925                                         <1 RK_PA7 1 &pcfg_pull_up_12ma>;
1926                         };
1927                 };
1928
1929                 lcdc {
1930                         lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1931                                 rockchip,pins =
1932                                         <3 RK_PA0 1 &pcfg_pull_none_12ma>;
1933                         };
1934
1935                         lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1936                                 rockchip,pins =
1937                                         <3 RK_PA1 1 &pcfg_pull_none_12ma>;
1938                         };
1939
1940                         lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1941                                 rockchip,pins =
1942                                         <3 RK_PA2 1 &pcfg_pull_none_12ma>;
1943                         };
1944
1945                         lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1946                                 rockchip,pins =
1947                                         <3 RK_PA3 1 &pcfg_pull_none_12ma>;
1948                         };
1949
1950                         lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1951                                 rockchip,pins =
1952                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1953                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1954                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1955                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1956                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1957                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1958                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1959                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1960                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1961                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1962                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1963                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1964                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1965                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1966                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1967                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1968                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1969                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1970                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1971                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1972                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1973                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1974                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1975                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1976                         };
1977
1978                         lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
1979                                 rockchip,pins =
1980                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1981                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1982                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1983                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1984                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1985                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1986                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1987                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1988                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1989                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1990                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1991                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1992                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1993                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1994                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1995                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1996                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1997                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1998                         };
1999
2000                         lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2001                                 rockchip,pins =
2002                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2003                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2004                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2005                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2006                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2007                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2008                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2009                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2010                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2011                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2012                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2013                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2014                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2015                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2016                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2017                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2018                         };
2019
2020                         lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2021                                 rockchip,pins =
2022                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2023                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2024                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2025                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2026                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2027                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2028                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2029                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2030                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2031                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2032                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2033                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2034                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2035                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2036                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2037                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2038                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2039                         };
2040
2041                         lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2042                                 rockchip,pins =
2043                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2044                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2045                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2046                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2047                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2048                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2049                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2050                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2051                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2052                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2053                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2054                         };
2055
2056                         lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2057                                 rockchip,pins =
2058                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2059                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2060                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2061                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2062                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2063                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2064                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2065                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2066                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2067                         };
2068                 };
2069
2070                 pwm0 {
2071                         pwm0_pin: pwm0-pin {
2072                                 rockchip,pins =
2073                                         <0 RK_PB7 1 &pcfg_pull_none>;
2074                         };
2075                 };
2076
2077                 pwm1 {
2078                         pwm1_pin: pwm1-pin {
2079                                 rockchip,pins =
2080                                         <0 RK_PC0 1 &pcfg_pull_none>;
2081                         };
2082                 };
2083
2084                 pwm2 {
2085                         pwm2_pin: pwm2-pin {
2086                                 rockchip,pins =
2087                                         <2 RK_PB5 1 &pcfg_pull_none>;
2088                         };
2089                 };
2090
2091                 pwm3 {
2092                         pwm3_pin: pwm3-pin {
2093                                 rockchip,pins =
2094                                         <0 RK_PC1 1 &pcfg_pull_none>;
2095                         };
2096                 };
2097
2098                 pwm4 {
2099                         pwm4_pin: pwm4-pin {
2100                                 rockchip,pins =
2101                                         <3 RK_PC2 3 &pcfg_pull_none>;
2102                         };
2103                 };
2104
2105                 pwm5 {
2106                         pwm5_pin: pwm5-pin {
2107                                 rockchip,pins =
2108                                         <3 RK_PC3 3 &pcfg_pull_none>;
2109                         };
2110                 };
2111
2112                 pwm6 {
2113                         pwm6_pin: pwm6-pin {
2114                                 rockchip,pins =
2115                                         <3 RK_PC4 3 &pcfg_pull_none>;
2116                         };
2117                 };
2118
2119                 pwm7 {
2120                         pwm7_pin: pwm7-pin {
2121                                 rockchip,pins =
2122                                         <3 RK_PC5 3 &pcfg_pull_none>;
2123                         };
2124                 };
2125
2126                 gmac {
2127                         rmii_pins: rmii-pins {
2128                                 rockchip,pins =
2129                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2130                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2131                                         <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2132                                         <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2133                                         <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2134                                         <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2135                                         <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2136                                         <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2137                                         <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2138                         };
2139
2140                         mac_refclk_12ma: mac-refclk-12ma {
2141                                 rockchip,pins =
2142                                         <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2143                         };
2144
2145                         mac_refclk: mac-refclk {
2146                                 rockchip,pins =
2147                                         <2 RK_PB2 2 &pcfg_pull_none>;
2148                         };
2149                 };
2150
2151                 cif-m0 {
2152                         cif_clkout_m0: cif-clkout-m0 {
2153                                 rockchip,pins =
2154                                         <2 RK_PB3 1 &pcfg_pull_none>;
2155                         };
2156
2157                         dvp_d2d9_m0: dvp-d2d9-m0 {
2158                                 rockchip,pins =
2159                                         <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2160                                         <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2161                                         <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2162                                         <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2163                                         <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2164                                         <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2165                                         <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2166                                         <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2167                                         <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2168                                         <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2169                                         <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2170                                         <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2171                         };
2172
2173                         dvp_d0d1_m0: dvp-d0d1-m0 {
2174                                 rockchip,pins =
2175                                         <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2176                                         <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2177                         };
2178
2179                         dvp_d10d11_m0:d10-d11-m0 {
2180                                 rockchip,pins =
2181                                         <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2182                                         <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2183                         };
2184                 };
2185
2186                 cif-m1 {
2187                         cif_clkout_m1: cif-clkout-m1 {
2188                                 rockchip,pins =
2189                                         <3 RK_PD0 3 &pcfg_pull_none>;
2190                         };
2191
2192                         dvp_d2d9_m1: dvp-d2d9-m1 {
2193                                 rockchip,pins =
2194                                         <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2195                                         <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2196                                         <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2197                                         <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2198                                         <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2199                                         <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2200                                         <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2201                                         <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2202                                         <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2203                                         <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2204                                         <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2205                                         <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2206                         };
2207
2208                         dvp_d0d1_m1: dvp-d0d1-m1 {
2209                                 rockchip,pins =
2210                                         <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2211                                         <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2212                         };
2213
2214                         dvp_d10d11_m1:d10-d11-m1 {
2215                                 rockchip,pins =
2216                                         <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2217                                         <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2218                         };
2219                 };
2220
2221                 isp {
2222                         isp_prelight: isp-prelight {
2223                                 rockchip,pins =
2224                                         <3 RK_PD1 4 &pcfg_pull_none>;
2225                         };
2226                 };
2227         };
2228 };