arch/arm/dts/pcl063-common.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Collabora Ltd.
   4  *
   5  * Based on dts[i] from Phytec barebox port:
   6  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
   7  * Author: Christian Hemp <c.hemp@phytec.de>
   8  */
   9
  10 / {
  11         model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
  12         compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
  13
  14         memory {
  15                 reg = <0x80000000 0x20000000>;
  16         };
  17
  18         chosen {
  19                 stdout-path = &uart1;
  20         };
  21 };
  22
  23 &fec1 {
  24         pinctrl-names = "default";
  25         pinctrl-0 = <&pinctrl_enet1>;
  26         phy-mode = "rmii";
  27         phy-handle = <&ethphy0>;
  28         status = "okay";
  29
  30         mdio: mdio {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 ethphy0: ethernet-phy@1 {
  35                         reg = <1>;
  36                         micrel,led-mode = <1>;
  37                 };
  38         };
  39 };
  40
  41 &gpmi {
  42         pinctrl-names = "default";
  43         pinctrl-0 = <&pinctrl_gpmi_nand>;
  44         nand-on-flash-bbt;
  45         fsl,no-blockmark-swap;
  46         status = "disabled";
  47
  48         #address-cells = <1>;
  49         #size-cells = <1>;
  50
  51         partition@0 {
  52                 label = "uboot";
  53                 reg = <0x0 0x400000>;
  54         };
  55
  56         partition@400000 {
  57                 label = "uboot-env";
  58                 reg = <0x400000 0x100000>;
  59         };
  60
  61         partition@500000 {
  62                 label = "root";
  63                 reg = <0x500000 0x0>;
  64         };
  65 };
  66
  67 &i2c1 {
  68         clock-frequency = <100000>;
  69         pinctrl-names = "default", "gpio";
  70         pinctrl-0 = <&pinctrl_i2c1>;
  71         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  72         scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  73         sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
  74         status = "okay";
  75
  76         eeprom@52 {
  77                 compatible = "cat,24c32";
  78                 reg = <0x52>;
  79         };
  80 };
  81
  82 &uart1 {
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_uart1>;
  85         status = "okay";
  86 };
  87
  88 &usdhc1 {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_usdhc1>;
  91         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
  92         bus-width = <0x4>;
  93         pinctrl-0 = <&pinctrl_usdhc1>;
  94         no-1-8-v;
  95         status = "okay";
  96 };
  97
  98 &usdhc2 {
  99         u-boot,dm-spl;
 100         u-boot,dm-pre-reloc;
 101         pinctrl-names = "default";
 102         pinctrl-0 = <&pinctrl_usdhc2>;
 103         bus-width = <8>;
 104         no-1-8-v;
 105         non-removable;
 106         keep-power-in-suspend;
 107         status = "disabled";
 108 };
 109
 110 &iomuxc {
 111         pinctrl-names = "default";
 112
 113         pinctrl_enet1: enet1grp {
 114                 fsl,pins = <
 115                         MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
 116                         MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
 117                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 118                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 119                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 120                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 121                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 122                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 123                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 124                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 125                 >;
 126         };
 127
 128         pinctrl_gpmi_nand: gpminandgrp {
 129                 fsl,pins = <
 130                         MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
 131                         MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0x0b0b1
 132                         MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0x0b0b1
 133                         MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
 134                         MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0x0b0b1
 135                         MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0x0b0b1
 136                         MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0x0b0b1
 137                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x0b0b1
 138                         MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0x0b0b1
 139                         MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0x0b0b1
 140                         MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0x0b0b1
 141                         MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0x0b0b1
 142                         MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0x0b0b1
 143                         MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0x0b0b1
 144                         MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0x0b0b1
 145                 >;
 146         };
 147
 148         pinctrl_i2c1: i2cgrp {
 149                 fsl,pins = <
 150                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b8b0
 151                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b8b0
 152                 >;
 153         };
 154
 155         pinctrl_i2c1_gpio: i2c1grp_gpio {
 156                 fsl,pins = <
 157                         MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
 158                         MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
 159                 >;
 160         };
 161
 162         pinctrl_uart1: uart1grp {
 163                 fsl,pins = <
 164                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
 165                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
 166                 >;
 167         };
 168
 169         pinctrl_usdhc1: usdhc1grp {
 170                 fsl,pins = <
 171                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 172                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 173                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 174                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 175                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 176                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 177                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059
 178
 179                 >;
 180         };
 181
 182         pinctrl_usdhc2: usdhc2grp {
 183                 fsl,pins = <
 184                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170f9
 185                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100f9
 186                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0     0x170f9
 187                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1     0x170f9
 188                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2     0x170f9
 189                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3     0x170f9
 190                         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4     0x170f9
 191                         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x170f9
 192                         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x170f9
 193                         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x170f9
 194                         MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170f9
 195                 >;
 196         };
 197 };