arch/arm/dts/omap3.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/pinctrl/omap.h>
  14
  15 / {
  16        compatible = "ti,omap3430", "ti,omap3";
  17        interrupt-parent = <&intc>;
  18        #address-cells = <1>;
  19        #size-cells = <1>;
  20        chosen { };
  21
  22        aliases {
  23                i2c0 = &i2c1;
  24                i2c1 = &i2c2;
  25                i2c2 = &i2c3;
  26                serial0 = &uart1;
  27                serial1 = &uart2;
  28                serial2 = &uart3;
  29        };
  30
  31        cpus {
  32                #address-cells = <1>;
  33                #size-cells = <0>;
  34
  35                cpu@0 {
  36                        compatible = "arm,cortex-a8";
  37                        device_type = "cpu";
  38                        reg = <0x0>;
  39
  40                        clocks = <&dpll1_ck>;
  41                        clock-names = "cpu";
  42
  43                        clock-latency = <300000>; /* From omap-cpufreq driver */
  44                };
  45        };
  46
  47        pmu@54000000 {
  48                compatible = "arm,cortex-a8-pmu";
  49                reg = <0x54000000 0x800000>;
  50                interrupts = <3>;
  51                ti,hwmods = "debugss";
  52        };
  53
  54        /*
  55         * The soc node represents the soc top level view. It is used for IPs
  56         * that are not memory mapped in the MPU view or for the MPU itself.
  57         */
  58        soc {
  59                compatible = "ti,omap-infra";
  60                mpu {
  61                        compatible = "ti,omap3-mpu";
  62                        ti,hwmods = "mpu";
  63                };
  64
  65                iva: iva {
  66                        compatible = "ti,iva2.2";
  67                        ti,hwmods = "iva";
  68
  69                        dsp {
  70                                compatible = "ti,omap3-c64";
  71                        };
  72                };
  73        };
  74
  75        /*
  76         * XXX: Use a flat representation of the OMAP3 interconnect.
  77         * The real OMAP interconnect network is quite complex.
  78         * Since it will not bring real advantage to represent that in DT for
  79         * the moment, just use a fake OCP bus entry to represent the whole bus
  80         * hierarchy.
  81         */
  82        ocp@68000000 {
  83                compatible = "ti,omap3-l3-smx", "simple-bus";
  84                reg = <0x68000000 0x10000>;
  85                interrupts = <9 10>;
  86                #address-cells = <1>;
  87                #size-cells = <1>;
  88                ranges;
  89                ti,hwmods = "l3_main";
  90
  91                l4_core: l4@48000000 {
  92                        compatible = "ti,omap3-l4-core", "simple-bus";
  93                        #address-cells = <1>;
  94                        #size-cells = <1>;
  95                        ranges = <0 0x48000000 0x1000000>;
  96
  97                        scm: scm@2000 {
  98                                compatible = "ti,omap3-scm", "simple-bus";
  99                                reg = <0x2000 0x2000>;
 100                                #address-cells = <1>;
 101                                #size-cells = <1>;
 102                                ranges = <0 0x2000 0x2000>;
 103
 104                                omap3_pmx_core: pinmux@30 {
 105                                        compatible = "ti,omap3-padconf",
 106                                                     "pinctrl-single";
 107                                        reg = <0x30 0x238>;
 108                                        #address-cells = <1>;
 109                                        #size-cells = <0>;
 110                                        #interrupt-cells = <1>;
 111                                        interrupt-controller;
 112                                        pinctrl-single,register-width = <16>;
 113                                        pinctrl-single,function-mask = <0xff1f>;
 114                                };
 115
 116                                scm_conf: scm_conf@270 {
 117                                        compatible = "syscon", "simple-bus";
 118                                        reg = <0x270 0x330>;
 119                                        #address-cells = <1>;
 120                                        #size-cells = <1>;
 121                                        ranges = <0 0x270 0x330>;
 122
 123                                        pbias_regulator: pbias_regulator@2b0 {
 124                                                compatible = "ti,pbias-omap3", "ti,pbias-omap";
 125                                                reg = <0x2b0 0x4>;
 126                                                syscon = <&scm_conf>;
 127                                                pbias_mmc_reg: pbias_mmc_omap2430 {
 128                                                        regulator-name = "pbias_mmc_omap2430";
 129                                                        regulator-min-microvolt = <1800000>;
 130                                                        regulator-max-microvolt = <3000000>;
 131                                                };
 132                                        };
 133
 134                                        scm_clocks: clocks {
 135                                                #address-cells = <1>;
 136                                                #size-cells = <0>;
 137                                        };
 138                                };
 139
 140                                scm_clockdomains: clockdomains {
 141                                };
 142
 143                                omap3_pmx_wkup: pinmux@a00 {
 144                                        compatible = "ti,omap3-padconf",
 145                                                     "pinctrl-single";
 146                                        reg = <0xa00 0x5c>;
 147                                        #address-cells = <1>;
 148                                        #size-cells = <0>;
 149                                        #interrupt-cells = <1>;
 150                                        interrupt-controller;
 151                                        pinctrl-single,register-width = <16>;
 152                                        pinctrl-single,function-mask = <0xff1f>;
 153                                };
 154                        };
 155                };
 156
 157                aes: aes@480c5000 {
 158                        compatible = "ti,omap3-aes";
 159                        ti,hwmods = "aes";
 160                        reg = <0x480c5000 0x50>;
 161                        interrupts = <0>;
 162                        dmas = <&sdma 65 &sdma 66>;
 163                        dma-names = "tx", "rx";
 164                };
 165
 166                prm: prm@48306000 {
 167                        compatible = "ti,omap3-prm";
 168                        reg = <0x48306000 0x4000>;
 169                        interrupts = <11>;
 170
 171                        prm_clocks: clocks {
 172                                #address-cells = <1>;
 173                                #size-cells = <0>;
 174                        };
 175
 176                        prm_clockdomains: clockdomains {
 177                        };
 178                };
 179
 180                cm: cm@48004000 {
 181                        compatible = "ti,omap3-cm";
 182                        reg = <0x48004000 0x4000>;
 183
 184                        cm_clocks: clocks {
 185                                #address-cells = <1>;
 186                                #size-cells = <0>;
 187                        };
 188
 189                        cm_clockdomains: clockdomains {
 190                        };
 191                };
 192
 193                counter32k: counter@48320000 {
 194                        compatible = "ti,omap-counter32k";
 195                        reg = <0x48320000 0x20>;
 196                        ti,hwmods = "counter_32k";
 197                };
 198
 199                intc: interrupt-controller@48200000 {
 200                        compatible = "ti,omap3-intc";
 201                        interrupt-controller;
 202                        #interrupt-cells = <1>;
 203                        reg = <0x48200000 0x1000>;
 204                };
 205
 206                sdma: dma-controller@48056000 {
 207                        compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
 208                        reg = <0x48056000 0x1000>;
 209                        interrupts = <12>,
 210                                     <13>,
 211                                     <14>,
 212                                     <15>;
 213                        #dma-cells = <1>;
 214                        dma-channels = <32>;
 215                        dma-requests = <96>;
 216                };
 217
 218                gpio1: gpio@48310000 {
 219                        compatible = "ti,omap3-gpio";
 220                        reg = <0x48310000 0x200>;
 221                        interrupts = <29>;
 222                        ti,hwmods = "gpio1";
 223                        ti,gpio-always-on;
 224                        gpio-controller;
 225                        #gpio-cells = <2>;
 226                        interrupt-controller;
 227                        #interrupt-cells = <2>;
 228                };
 229
 230                gpio2: gpio@49050000 {
 231                        compatible = "ti,omap3-gpio";
 232                        reg = <0x49050000 0x200>;
 233                        interrupts = <30>;
 234                        ti,hwmods = "gpio2";
 235                        gpio-controller;
 236                        #gpio-cells = <2>;
 237                        interrupt-controller;
 238                        #interrupt-cells = <2>;
 239                };
 240
 241                gpio3: gpio@49052000 {
 242                        compatible = "ti,omap3-gpio";
 243                        reg = <0x49052000 0x200>;
 244                        interrupts = <31>;
 245                        ti,hwmods = "gpio3";
 246                        gpio-controller;
 247                        #gpio-cells = <2>;
 248                        interrupt-controller;
 249                        #interrupt-cells = <2>;
 250                };
 251
 252                gpio4: gpio@49054000 {
 253                        compatible = "ti,omap3-gpio";
 254                        reg = <0x49054000 0x200>;
 255                        interrupts = <32>;
 256                        ti,hwmods = "gpio4";
 257                        gpio-controller;
 258                        #gpio-cells = <2>;
 259                        interrupt-controller;
 260                        #interrupt-cells = <2>;
 261                };
 262
 263                gpio5: gpio@49056000 {
 264                        compatible = "ti,omap3-gpio";
 265                        reg = <0x49056000 0x200>;
 266                        interrupts = <33>;
 267                        ti,hwmods = "gpio5";
 268                        gpio-controller;
 269                        #gpio-cells = <2>;
 270                        interrupt-controller;
 271                        #interrupt-cells = <2>;
 272                };
 273
 274                gpio6: gpio@49058000 {
 275                        compatible = "ti,omap3-gpio";
 276                        reg = <0x49058000 0x200>;
 277                        interrupts = <34>;
 278                        ti,hwmods = "gpio6";
 279                        gpio-controller;
 280                        #gpio-cells = <2>;
 281                        interrupt-controller;
 282                        #interrupt-cells = <2>;
 283                };
 284
 285                uart1: serial@4806a000 {
 286                        compatible = "ti,omap3-uart";
 287                        reg = <0x4806a000 0x2000>;
 288                        reg-shift = <2>;
 289                        interrupts-extended = <&intc 72>;
 290                        dmas = <&sdma 49 &sdma 50>;
 291                        dma-names = "tx", "rx";
 292                        ti,hwmods = "uart1";
 293                        clock-frequency = <48000000>;
 294                };
 295
 296                uart2: serial@4806c000 {
 297                        compatible = "ti,omap3-uart";
 298                        reg = <0x4806c000 0x400>;
 299                        interrupts-extended = <&intc 73>;
 300                        dmas = <&sdma 51 &sdma 52>;
 301                        dma-names = "tx", "rx";
 302                        ti,hwmods = "uart2";
 303                        clock-frequency = <48000000>;
 304                };
 305
 306                uart3: serial@49020000 {
 307                        compatible = "ti,omap3-uart";
 308                        reg = <0x49020000 0x400>;
 309                        interrupts-extended = <&intc 74>;
 310                        dmas = <&sdma 53 &sdma 54>;
 311                        dma-names = "tx", "rx";
 312                        ti,hwmods = "uart3";
 313                        clock-frequency = <48000000>;
 314                };
 315
 316                i2c1: i2c@48070000 {
 317                        compatible = "ti,omap3-i2c";
 318                        reg = <0x48070000 0x80>;
 319                        interrupts = <56>;
 320                        dmas = <&sdma 27 &sdma 28>;
 321                        dma-names = "tx", "rx";
 322                        #address-cells = <1>;
 323                        #size-cells = <0>;
 324                        ti,hwmods = "i2c1";
 325                };
 326
 327                i2c2: i2c@48072000 {
 328                        compatible = "ti,omap3-i2c";
 329                        reg = <0x48072000 0x80>;
 330                        interrupts = <57>;
 331                        dmas = <&sdma 29 &sdma 30>;
 332                        dma-names = "tx", "rx";
 333                        #address-cells = <1>;
 334                        #size-cells = <0>;
 335                        ti,hwmods = "i2c2";
 336                };
 337
 338                i2c3: i2c@48060000 {
 339                        compatible = "ti,omap3-i2c";
 340                        reg = <0x48060000 0x80>;
 341                        interrupts = <61>;
 342                        dmas = <&sdma 25 &sdma 26>;
 343                        dma-names = "tx", "rx";
 344                        #address-cells = <1>;
 345                        #size-cells = <0>;
 346                        ti,hwmods = "i2c3";
 347                };
 348
 349                mailbox: mailbox@48094000 {
 350                        compatible = "ti,omap3-mailbox";
 351                        ti,hwmods = "mailbox";
 352                        reg = <0x48094000 0x200>;
 353                        interrupts = <26>;
 354                        #mbox-cells = <1>;
 355                        ti,mbox-num-users = <2>;
 356                        ti,mbox-num-fifos = <2>;
 357                        mbox_dsp: dsp {
 358                                ti,mbox-tx = <0 0 0>;
 359                                ti,mbox-rx = <1 0 0>;
 360                        };
 361                };
 362
 363                mcspi1: spi@48098000 {
 364                        compatible = "ti,omap2-mcspi";
 365                        reg = <0x48098000 0x100>;
 366                        interrupts = <65>;
 367                        #address-cells = <1>;
 368                        #size-cells = <0>;
 369                        ti,hwmods = "mcspi1";
 370                        ti,spi-num-cs = <4>;
 371                        dmas = <&sdma 35>,
 372                               <&sdma 36>,
 373                               <&sdma 37>,
 374                               <&sdma 38>,
 375                               <&sdma 39>,
 376                               <&sdma 40>,
 377                               <&sdma 41>,
 378                               <&sdma 42>;
 379                        dma-names = "tx0", "rx0", "tx1", "rx1",
 380                                    "tx2", "rx2", "tx3", "rx3";
 381                };
 382
 383                mcspi2: spi@4809a000 {
 384                        compatible = "ti,omap2-mcspi";
 385                        reg = <0x4809a000 0x100>;
 386                        interrupts = <66>;
 387                        #address-cells = <1>;
 388                        #size-cells = <0>;
 389                        ti,hwmods = "mcspi2";
 390                        ti,spi-num-cs = <2>;
 391                        dmas = <&sdma 43>,
 392                               <&sdma 44>,
 393                               <&sdma 45>,
 394                               <&sdma 46>;
 395                        dma-names = "tx0", "rx0", "tx1", "rx1";
 396                };
 397
 398                mcspi3: spi@480b8000 {
 399                        compatible = "ti,omap2-mcspi";
 400                        reg = <0x480b8000 0x100>;
 401                        interrupts = <91>;
 402                        #address-cells = <1>;
 403                        #size-cells = <0>;
 404                        ti,hwmods = "mcspi3";
 405                        ti,spi-num-cs = <2>;
 406                        dmas = <&sdma 15>,
 407                               <&sdma 16>,
 408                               <&sdma 23>,
 409                               <&sdma 24>;
 410                        dma-names = "tx0", "rx0", "tx1", "rx1";
 411                };
 412
 413                mcspi4: spi@480ba000 {
 414                        compatible = "ti,omap2-mcspi";
 415                        reg = <0x480ba000 0x100>;
 416                        interrupts = <48>;
 417                        #address-cells = <1>;
 418                        #size-cells = <0>;
 419                        ti,hwmods = "mcspi4";
 420                        ti,spi-num-cs = <1>;
 421                        dmas = <&sdma 70>, <&sdma 71>;
 422                        dma-names = "tx0", "rx0";
 423                };
 424
 425                hdqw1w: 1w@480b2000 {
 426                        compatible = "ti,omap3-1w";
 427                        reg = <0x480b2000 0x1000>;
 428                        interrupts = <58>;
 429                        ti,hwmods = "hdq1w";
 430                };
 431
 432                mmc1: mmc@4809c000 {
 433                        compatible = "ti,omap3-hsmmc";
 434                        reg = <0x4809c000 0x200>;
 435                        interrupts = <83>;
 436                        ti,hwmods = "mmc1";
 437                        ti,dual-volt;
 438                        dmas = <&sdma 61>, <&sdma 62>;
 439                        dma-names = "tx", "rx";
 440                        pbias-supply = <&pbias_mmc_reg>;
 441                };
 442
 443                mmc2: mmc@480b4000 {
 444                        compatible = "ti,omap3-hsmmc";
 445                        reg = <0x480b4000 0x200>;
 446                        interrupts = <86>;
 447                        ti,hwmods = "mmc2";
 448                        dmas = <&sdma 47>, <&sdma 48>;
 449                        dma-names = "tx", "rx";
 450                };
 451
 452                mmc3: mmc@480ad000 {
 453                        compatible = "ti,omap3-hsmmc";
 454                        reg = <0x480ad000 0x200>;
 455                        interrupts = <94>;
 456                        ti,hwmods = "mmc3";
 457                        dmas = <&sdma 77>, <&sdma 78>;
 458                        dma-names = "tx", "rx";
 459                };
 460
 461                mmu_isp: mmu@480bd400 {
 462                        #iommu-cells = <0>;
 463                        compatible = "ti,omap2-iommu";
 464                        reg = <0x480bd400 0x80>;
 465                        interrupts = <24>;
 466                        ti,hwmods = "mmu_isp";
 467                        ti,#tlb-entries = <8>;
 468                };
 469
 470                mmu_iva: mmu@5d000000 {
 471                        #iommu-cells = <0>;
 472                        compatible = "ti,omap2-iommu";
 473                        reg = <0x5d000000 0x80>;
 474                        interrupts = <28>;
 475                        ti,hwmods = "mmu_iva";
 476                        status = "disabled";
 477                };
 478
 479                wdt2: wdt@48314000 {
 480                        compatible = "ti,omap3-wdt";
 481                        reg = <0x48314000 0x80>;
 482                        ti,hwmods = "wd_timer2";
 483                };
 484
 485                mcbsp1: mcbsp@48074000 {
 486                        compatible = "ti,omap3-mcbsp";
 487                        reg = <0x48074000 0xff>;
 488                        reg-names = "mpu";
 489                        interrupts = <16>, /* OCP compliant interrupt */
 490                                     <59>, /* TX interrupt */
 491                                     <60>; /* RX interrupt */
 492                        interrupt-names = "common", "tx", "rx";
 493                        ti,buffer-size = <128>;
 494                        ti,hwmods = "mcbsp1";
 495                        dmas = <&sdma 31>,
 496                               <&sdma 32>;
 497                        dma-names = "tx", "rx";
 498                        clocks = <&mcbsp1_fck>;
 499                        clock-names = "fck";
 500                        status = "disabled";
 501                };
 502
 503                mcbsp2: mcbsp@49022000 {
 504                        compatible = "ti,omap3-mcbsp";
 505                        reg = <0x49022000 0xff>,
 506                              <0x49028000 0xff>;
 507                        reg-names = "mpu", "sidetone";
 508                        interrupts = <17>, /* OCP compliant interrupt */
 509                                     <62>, /* TX interrupt */
 510                                     <63>, /* RX interrupt */
 511                                     <4>;  /* Sidetone */
 512                        interrupt-names = "common", "tx", "rx", "sidetone";
 513                        ti,buffer-size = <1280>;
 514                        ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
 515                        dmas = <&sdma 33>,
 516                               <&sdma 34>;
 517                        dma-names = "tx", "rx";
 518                        clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
 519                        clock-names = "fck", "ick";
 520                        status = "disabled";
 521                };
 522
 523                mcbsp3: mcbsp@49024000 {
 524                        compatible = "ti,omap3-mcbsp";
 525                        reg = <0x49024000 0xff>,
 526                              <0x4902a000 0xff>;
 527                        reg-names = "mpu", "sidetone";
 528                        interrupts = <22>, /* OCP compliant interrupt */
 529                                     <89>, /* TX interrupt */
 530                                     <90>, /* RX interrupt */
 531                                     <5>;  /* Sidetone */
 532                        interrupt-names = "common", "tx", "rx", "sidetone";
 533                        ti,buffer-size = <128>;
 534                        ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
 535                        dmas = <&sdma 17>,
 536                               <&sdma 18>;
 537                        dma-names = "tx", "rx";
 538                        clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
 539                        clock-names = "fck", "ick";
 540                        status = "disabled";
 541                };
 542
 543                mcbsp4: mcbsp@49026000 {
 544                        compatible = "ti,omap3-mcbsp";
 545                        reg = <0x49026000 0xff>;
 546                        reg-names = "mpu";
 547                        interrupts = <23>, /* OCP compliant interrupt */
 548                                     <54>, /* TX interrupt */
 549                                     <55>; /* RX interrupt */
 550                        interrupt-names = "common", "tx", "rx";
 551                        ti,buffer-size = <128>;
 552                        ti,hwmods = "mcbsp4";
 553                        dmas = <&sdma 19>,
 554                               <&sdma 20>;
 555                        dma-names = "tx", "rx";
 556                        clocks = <&mcbsp4_fck>;
 557                        clock-names = "fck";
 558                        status = "disabled";
 559                };
 560
 561                mcbsp5: mcbsp@48096000 {
 562                        compatible = "ti,omap3-mcbsp";
 563                        reg = <0x48096000 0xff>;
 564                        reg-names = "mpu";
 565                        interrupts = <27>, /* OCP compliant interrupt */
 566                                     <81>, /* TX interrupt */
 567                                     <82>; /* RX interrupt */
 568                        interrupt-names = "common", "tx", "rx";
 569                        ti,buffer-size = <128>;
 570                        ti,hwmods = "mcbsp5";
 571                        dmas = <&sdma 21>,
 572                               <&sdma 22>;
 573                        dma-names = "tx", "rx";
 574                        clocks = <&mcbsp5_fck>;
 575                        clock-names = "fck";
 576                        status = "disabled";
 577                };
 578
 579                sham: sham@480c3000 {
 580                        compatible = "ti,omap3-sham";
 581                        ti,hwmods = "sham";
 582                        reg = <0x480c3000 0x64>;
 583                        interrupts = <49>;
 584                        dmas = <&sdma 69>;
 585                        dma-names = "rx";
 586                };
 587
 588                smartreflex_core: smartreflex@480cb000 {
 589                        compatible = "ti,omap3-smartreflex-core";
 590                        ti,hwmods = "smartreflex_core";
 591                        reg = <0x480cb000 0x400>;
 592                        interrupts = <19>;
 593                };
 594
 595                smartreflex_mpu_iva: smartreflex@480c9000 {
 596                        compatible = "ti,omap3-smartreflex-iva";
 597                        ti,hwmods = "smartreflex_mpu_iva";
 598                        reg = <0x480c9000 0x400>;
 599                        interrupts = <18>;
 600                };
 601
 602                timer1: timer@48318000 {
 603                        compatible = "ti,omap3430-timer";
 604                        reg = <0x48318000 0x400>;
 605                        interrupts = <37>;
 606                        ti,hwmods = "timer1";
 607                        ti,timer-alwon;
 608                };
 609
 610                timer2: timer@49032000 {
 611                        compatible = "ti,omap3430-timer";
 612                        reg = <0x49032000 0x400>;
 613                        interrupts = <38>;
 614                        ti,hwmods = "timer2";
 615                };
 616
 617                timer3: timer@49034000 {
 618                        compatible = "ti,omap3430-timer";
 619                        reg = <0x49034000 0x400>;
 620                        interrupts = <39>;
 621                        ti,hwmods = "timer3";
 622                };
 623
 624                timer4: timer@49036000 {
 625                        compatible = "ti,omap3430-timer";
 626                        reg = <0x49036000 0x400>;
 627                        interrupts = <40>;
 628                        ti,hwmods = "timer4";
 629                };
 630
 631                timer5: timer@49038000 {
 632                        compatible = "ti,omap3430-timer";
 633                        reg = <0x49038000 0x400>;
 634                        interrupts = <41>;
 635                        ti,hwmods = "timer5";
 636                        ti,timer-dsp;
 637                };
 638
 639                timer6: timer@4903a000 {
 640                        compatible = "ti,omap3430-timer";
 641                        reg = <0x4903a000 0x400>;
 642                        interrupts = <42>;
 643                        ti,hwmods = "timer6";
 644                        ti,timer-dsp;
 645                };
 646
 647                timer7: timer@4903c000 {
 648                        compatible = "ti,omap3430-timer";
 649                        reg = <0x4903c000 0x400>;
 650                        interrupts = <43>;
 651                        ti,hwmods = "timer7";
 652                        ti,timer-dsp;
 653                };
 654
 655                timer8: timer@4903e000 {
 656                        compatible = "ti,omap3430-timer";
 657                        reg = <0x4903e000 0x400>;
 658                        interrupts = <44>;
 659                        ti,hwmods = "timer8";
 660                        ti,timer-pwm;
 661                        ti,timer-dsp;
 662                };
 663
 664                timer9: timer@49040000 {
 665                        compatible = "ti,omap3430-timer";
 666                        reg = <0x49040000 0x400>;
 667                        interrupts = <45>;
 668                        ti,hwmods = "timer9";
 669                        ti,timer-pwm;
 670                };
 671
 672                timer10: timer@48086000 {
 673                        compatible = "ti,omap3430-timer";
 674                        reg = <0x48086000 0x400>;
 675                        interrupts = <46>;
 676                        ti,hwmods = "timer10";
 677                        ti,timer-pwm;
 678                };
 679
 680                timer11: timer@48088000 {
 681                        compatible = "ti,omap3430-timer";
 682                        reg = <0x48088000 0x400>;
 683                        interrupts = <47>;
 684                        ti,hwmods = "timer11";
 685                        ti,timer-pwm;
 686                };
 687
 688                timer12: timer@48304000 {
 689                        compatible = "ti,omap3430-timer";
 690                        reg = <0x48304000 0x400>;
 691                        interrupts = <95>;
 692                        ti,hwmods = "timer12";
 693                        ti,timer-alwon;
 694                        ti,timer-secure;
 695                };
 696
 697                usbhstll: usbhstll@48062000 {
 698                        compatible = "ti,usbhs-tll";
 699                        reg = <0x48062000 0x1000>;
 700                        interrupts = <78>;
 701                        ti,hwmods = "usb_tll_hs";
 702                };
 703
 704                usbhshost: usbhshost@48064000 {
 705                        compatible = "ti,usbhs-host";
 706                        reg = <0x48064000 0x400>;
 707                        ti,hwmods = "usb_host_hs";
 708                        #address-cells = <1>;
 709                        #size-cells = <1>;
 710                        ranges;
 711
 712                        usbhsohci: ohci@48064400 {
 713                                compatible = "ti,ohci-omap3";
 714                                reg = <0x48064400 0x400>;
 715                                interrupt-parent = <&intc>;
 716                                interrupts = <76>;
 717                        };
 718
 719                        usbhsehci: ehci@48064800 {
 720                                compatible = "ti,ehci-omap";
 721                                reg = <0x48064800 0x400>;
 722                                interrupt-parent = <&intc>;
 723                                interrupts = <77>;
 724                        };
 725                };
 726
 727                gpmc: gpmc@6e000000 {
 728                        compatible = "ti,omap3430-gpmc";
 729                        ti,hwmods = "gpmc";
 730                        reg = <0x6e000000 0x02d0>;
 731                        interrupts = <20>;
 732                        dmas = <&sdma 4>;
 733                        dma-names = "rxtx";
 734                        gpmc,num-cs = <8>;
 735                        gpmc,num-waitpins = <4>;
 736                        #address-cells = <2>;
 737                        #size-cells = <1>;
 738                        interrupt-controller;
 739                        #interrupt-cells = <2>;
 740                        gpio-controller;
 741                        #gpio-cells = <2>;
 742                };
 743
 744                usb_otg_hs: usb_otg_hs@480ab000 {
 745                        compatible = "ti,omap3-musb";
 746                        reg = <0x480ab000 0x1000>;
 747                        interrupts = <92>, <93>;
 748                        interrupt-names = "mc", "dma";
 749                        ti,hwmods = "usb_otg_hs";
 750                        multipoint = <1>;
 751                        num-eps = <16>;
 752                        ram-bits = <12>;
 753                };
 754
 755                dss: dss@48050000 {
 756                        compatible = "ti,omap3-dss";
 757                        reg = <0x48050000 0x200>;
 758                        status = "disabled";
 759                        ti,hwmods = "dss_core";
 760                        clocks = <&dss1_alwon_fck>;
 761                        clock-names = "fck";
 762                        #address-cells = <1>;
 763                        #size-cells = <1>;
 764                        ranges;
 765
 766                        dispc@48050400 {
 767                                compatible = "ti,omap3-dispc";
 768                                reg = <0x48050400 0x400>;
 769                                interrupts = <25>;
 770                                ti,hwmods = "dss_dispc";
 771                                clocks = <&dss1_alwon_fck>;
 772                                clock-names = "fck";
 773                        };
 774
 775                        dsi: encoder@4804fc00 {
 776                                compatible = "ti,omap3-dsi";
 777                                reg = <0x4804fc00 0x200>,
 778                                      <0x4804fe00 0x40>,
 779                                      <0x4804ff00 0x20>;
 780                                reg-names = "proto", "phy", "pll";
 781                                interrupts = <25>;
 782                                status = "disabled";
 783                                ti,hwmods = "dss_dsi1";
 784                                clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
 785                                clock-names = "fck", "sys_clk";
 786                        };
 787
 788                        rfbi: encoder@48050800 {
 789                                compatible = "ti,omap3-rfbi";
 790                                reg = <0x48050800 0x100>;
 791                                status = "disabled";
 792                                ti,hwmods = "dss_rfbi";
 793                                clocks = <&dss1_alwon_fck>, <&dss_ick>;
 794                                clock-names = "fck", "ick";
 795                        };
 796
 797                        venc: encoder@48050c00 {
 798                                compatible = "ti,omap3-venc";
 799                                reg = <0x48050c00 0x100>;
 800                                status = "disabled";
 801                                ti,hwmods = "dss_venc";
 802                                clocks = <&dss_tv_fck>;
 803                                clock-names = "fck";
 804                        };
 805                };
 806
 807                ssi: ssi-controller@48058000 {
 808                        compatible = "ti,omap3-ssi";
 809                        ti,hwmods = "ssi";
 810
 811                        status = "disabled";
 812
 813                        reg = <0x48058000 0x1000>,
 814                              <0x48059000 0x1000>;
 815                        reg-names = "sys",
 816                                    "gdd";
 817
 818                        interrupts = <71>;
 819                        interrupt-names = "gdd_mpu";
 820
 821                        #address-cells = <1>;
 822                        #size-cells = <1>;
 823                        ranges;
 824
 825                        ssi_port1: ssi-port@4805a000 {
 826                                compatible = "ti,omap3-ssi-port";
 827
 828                                reg = <0x4805a000 0x800>,
 829                                      <0x4805a800 0x800>;
 830                                reg-names = "tx",
 831                                            "rx";
 832
 833                                interrupt-parent = <&intc>;
 834                                interrupts = <67>,
 835                                             <68>;
 836                        };
 837
 838                        ssi_port2: ssi-port@4805b000 {
 839                                compatible = "ti,omap3-ssi-port";
 840
 841                                reg = <0x4805b000 0x800>,
 842                                      <0x4805b800 0x800>;
 843                                reg-names = "tx",
 844                                            "rx";
 845
 846                                interrupt-parent = <&intc>;
 847                                interrupts = <69>,
 848                                             <70>;
 849                        };
 850                };
 851        };
 852 };
 853
 854 /include/ "omap3xxx-clocks.dtsi"