2 * Copyright (C) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt7629-clk.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/mt7629-power.h>
13 #include <dt-bindings/reset/mt7629-reset.h>
14 #include <dt-bindings/phy/phy.h>
15 #include "skeleton.dtsi"
18 compatible = "mediatek,mt7629";
19 interrupt-parent = <&sysirq>;
26 enable-method = "mediatek,mt6589-smp";
30 compatible = "arm,cortex-a7";
32 clock-frequency = <1250000000>;
37 compatible = "arm,cortex-a7";
39 clock-frequency = <1250000000>;
43 clk20m: oscillator@0 {
44 compatible = "fixed-clock";
46 clock-frequency = <20000000>;
47 clock-output-names = "clk20m";
50 clk40m: oscillator@1 {
51 compatible = "fixed-clock";
53 clock-frequency = <40000000>;
54 clock-output-names = "clkxtal";
58 compatible = "arm,armv7-timer";
59 interrupt-parent = <&gic>;
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
64 clock-frequency = <20000000>;
65 arm,cpu-registers-not-fw-configured;
68 infracfg: syscon@10000000 {
69 compatible = "mediatek,mt7629-infracfg", "syscon";
70 reg = <0x10000000 0x1000>;
74 pericfg: syscon@10002000 {
75 compatible = "mediatek,mt7629-pericfg", "syscon";
76 reg = <0x10002000 0x1000>;
80 timer0: timer@10004000 {
81 compatible = "mediatek,timer";
82 reg = <0x10004000 0x80>;
83 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
84 clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
85 <&topckgen CLK_TOP_10M_SEL>;
86 clock-names = "mux", "src";
89 scpsys: scpsys@10006000 {
90 compatible = "mediatek,mt7629-scpsys";
91 reg = <0x10006000 0x1000>;
92 clocks = <&topckgen CLK_TOP_HIF_SEL>;
93 clock-names = "hif_sel";
94 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
95 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
96 #power-domain-cells = <1>;
97 infracfg = <&infracfg>;
100 mcucfg: syscon@10200000 {
101 compatible = "mediatek,mt7629-mcucfg", "syscon";
102 reg = <0x10200000 0x1000>;
106 sysirq: interrupt-controller@10200a80 {
107 compatible = "mediatek,sysirq";
108 reg = <0x10200a80 0x20>;
109 interrupt-controller;
110 #interrupt-cells = <3>;
111 interrupt-parent = <&gic>;
114 dramc: dramc@10203000 {
115 compatible = "mediatek,mt7629-dramc";
116 reg = <0x10203000 0x600>, /* EMI */
117 <0x10213000 0x1000>, /* DDRPHY */
118 <0x10214000 0xd00>; /* DRAMC_AO */
119 clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
120 <&topckgen CLK_TOP_SYSPLL1_D8>,
121 <&topckgen CLK_TOP_MEM_SEL>,
122 <&topckgen CLK_TOP_DMPLL>;
123 clock-names = "phy", "phy_mux", "mem", "mem_mux";
126 apmixedsys: clock-controller@10209000 {
127 compatible = "mediatek,mt7629-apmixedsys";
128 reg = <0x10209000 0x1000>;
132 topckgen: clock-controller@10210000 {
133 compatible = "mediatek,mt7629-topckgen";
134 reg = <0x10210000 0x1000>;
138 watchdog: watchdog@10212000 {
139 compatible = "mediatek,wdt";
140 reg = <0x10212000 0x600>;
141 interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_FALLING>;
147 compatible = "wdt-reboot";
151 pinctrl: pinctrl@10217000 {
152 compatible = "mediatek,mt7629-pinctrl";
153 reg = <0x10217000 0x8000>;
155 gpio: gpio-controller {
161 gic: interrupt-controller@10300000 {
162 compatible = "arm,gic-400";
163 interrupt-controller;
164 #interrupt-cells = <3>;
165 interrupt-parent = <&gic>;
166 reg = <0x10310000 0x1000>,
172 uart0: serial@11002000 {
173 compatible = "mediatek,hsuart";
174 reg = <0x11002000 0x400>;
176 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
177 clocks = <&topckgen CLK_TOP_UART_SEL>,
178 <&pericfg CLK_PERI_UART0_PD>;
179 clock-names = "baud", "bus";
181 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
182 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
185 uart1: serial@11003000 {
186 compatible = "mediatek,hsuart";
187 reg = <0x11003000 0x400>;
189 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
190 clocks = <&topckgen CLK_TOP_UART_SEL>,
191 <&pericfg CLK_PERI_UART1_PD>;
192 clock-names = "baud", "bus";
193 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
194 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
198 uart2: serial@11004000 {
199 compatible = "mediatek,hsuart";
200 reg = <0x11004000 0x400>;
202 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
203 clocks = <&topckgen CLK_TOP_UART_SEL>,
204 <&pericfg CLK_PERI_UART2_PD>;
205 clock-names = "baud", "bus";
206 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
207 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
211 snfi: snfi@1100d000 {
212 compatible = "mediatek,mtk-snfi-spi";
213 reg = <0x1100d000 0x2000>;
214 clocks = <&pericfg CLK_PERI_NFI_PD>,
215 <&pericfg CLK_PERI_SNFI_PD>;
216 clock-names = "nfi_clk", "pad_clk";
217 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
218 <&topckgen CLK_TOP_NFI_INFRA_SEL>;
219 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
220 <&topckgen CLK_TOP_UNIVPLL2_D8>;
222 #address-cells = <1>;
226 ssusbsys: ssusbsys@1a000000 {
227 compatible = "mediatek,mt7629-ssusbsys", "syscon";
228 reg = <0x1a000000 0x1000>;
233 compatible = "mediatek,mt7629-xhci", "mediatek,mtk-xhci";
234 reg = <0x1a0c0000 0x1000>, <0x1a0c3e00 0x0100>;
235 reg-names = "mac", "ippc";
236 power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
237 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
238 <&ssusbsys CLK_SSUSB_REF_EN>,
239 <&ssusbsys CLK_SSUSB_MCU_EN>,
240 <&ssusbsys CLK_SSUSB_DMA_EN>;
241 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
242 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
246 u3phy: usb-phy@1a0c4000 {
247 compatible = "mediatek,mt7629-tphy", "mediatek,generic-tphy-v2";
248 #address-cells = <1>;
250 ranges = <0 0x1a0c4000 0x1000>;
256 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
260 u3port0: usb-phy@700 {
261 reg = <0x0700 0x0700>;
266 ethsys: syscon@1b000000 {
267 compatible = "mediatek,mt7629-ethsys", "syscon";
268 reg = <0x1b000000 0x1000>;
273 eth: ethernet@1b100000 {
274 compatible = "mediatek,mt7629-eth", "syscon";
275 reg = <0x1b100000 0x20000>;
276 clocks = <&topckgen CLK_TOP_ETH_SEL>,
277 <&topckgen CLK_TOP_F10M_REF_SEL>,
278 <ðsys CLK_ETH_ESW_EN>,
279 <ðsys CLK_ETH_GP0_EN>,
280 <ðsys CLK_ETH_GP1_EN>,
281 <ðsys CLK_ETH_GP2_EN>,
282 <ðsys CLK_ETH_FE_EN>,
283 <&sgmiisys0 CLK_SGMII_TX_EN>,
284 <&sgmiisys0 CLK_SGMII_RX_EN>,
285 <&sgmiisys0 CLK_SGMII_CDR_REF>,
286 <&sgmiisys0 CLK_SGMII_CDR_FB>,
287 <&sgmiisys1 CLK_SGMII_TX_EN>,
288 <&sgmiisys1 CLK_SGMII_RX_EN>,
289 <&sgmiisys1 CLK_SGMII_CDR_REF>,
290 <&sgmiisys1 CLK_SGMII_CDR_FB>,
291 <&apmixedsys CLK_APMIXED_SGMIPLL>,
292 <&apmixedsys CLK_APMIXED_ETH2PLL>;
293 clock-names = "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2",
294 "fe", "sgmii_tx250m", "sgmii_rx250m",
295 "sgmii_cdr_ref", "sgmii_cdr_fb",
296 "sgmii2_tx250m", "sgmii2_rx250m",
297 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
298 "sgmii_ck", "eth2pll";
299 assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
300 <&topckgen CLK_TOP_F10M_REF_SEL>;
301 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
302 <&topckgen CLK_TOP_SGMIIPLL_D2>;
303 power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
304 resets = <ðsys ETHSYS_FE_RST>;
306 mediatek,ethsys = <ðsys>;
307 mediatek,sgmiisys = <&sgmiisys0>;
308 mediatek,infracfg = <&infracfg>;
309 #address-cells = <1>;
314 sgmiisys0: syscon@1b128000 {
315 compatible = "mediatek,mt7629-sgmiisys", "syscon";
316 reg = <0x1b128000 0x1000>;
320 sgmiisys1: syscon@1b130000 {
321 compatible = "mediatek,mt7629-sgmiisys", "syscon";
322 reg = <0x1b130000 0x1000>;
327 compatible = "mediatek,mt7629-pwm";
328 reg = <0x11006000 0x1000>;
331 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
332 clocks = <&topckgen CLK_TOP_PWM_SEL>,
333 <&pericfg CLK_PERI_PWM_PD>,
334 <&pericfg CLK_PERI_PWM1_PD>;
335 clock-names = "top", "main", "pwm1";
336 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
337 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>;