arch/arm/dts/mt7623.dtsi

   1 /*
   2  * Copyright (C) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 #include <dt-bindings/clock/mt7623-clk.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/power/mt7623-power.h>
  13 #include "skeleton.dtsi"
  14
  15 / {
  16         compatible = "mediatek,mt7623";
  17         interrupt-parent = <&sysirq>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24                 enable-method = "mediatek,mt6589-smp";
  25
  26                 cpu0: cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a7";
  29                         reg = <0x0>;
  30                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  31                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  32                         clock-names = "cpu", "intermediate";
  33                         clock-frequency = <1300000000>;
  34                 };
  35
  36                 cpu1: cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a7";
  39                         reg = <0x1>;
  40                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  41                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  42                         clock-names = "cpu", "intermediate";
  43                         clock-frequency = <1300000000>;
  44                 };
  45
  46                 cpu2: cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a7";
  49                         reg = <0x2>;
  50                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  51                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  52                         clock-names = "cpu", "intermediate";
  53                         clock-frequency = <1300000000>;
  54                 };
  55
  56                 cpu3: cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a7";
  59                         reg = <0x3>;
  60                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  61                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  62                         clock-names = "cpu", "intermediate";
  63                         clock-frequency = <1300000000>;
  64                 };
  65         };
  66
  67         system_clk: dummy13m {
  68                 compatible = "fixed-clock";
  69                 clock-frequency = <13000000>;
  70                 #clock-cells = <0>;
  71         };
  72
  73         rtc32k: oscillator-1 {
  74                 compatible = "fixed-clock";
  75                 #clock-cells = <0>;
  76                 clock-frequency = <32000>;
  77                 clock-output-names = "rtc32k";
  78         };
  79
  80         clk26m: oscillator-0 {
  81                 compatible = "fixed-clock";
  82                 #clock-cells = <0>;
  83                 clock-frequency = <26000000>;
  84                 clock-output-names = "clk26m";
  85         };
  86
  87         timer {
  88                 compatible = "arm,armv7-timer";
  89                 interrupt-parent = <&gic>;
  90                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  91                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  92                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  93                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  94                 clock-frequency = <13000000>;
  95                 arm,cpu-registers-not-fw-configured;
  96         };
  97
  98         topckgen: clock-controller@10000000 {
  99                 compatible = "mediatek,mt7623-topckgen";
 100                 reg = <0x10000000 0x1000>;
 101                 #clock-cells = <1>;
 102                 u-boot,dm-pre-reloc;
 103         };
 104
 105         infracfg: syscon@10001000 {
 106                 compatible = "mediatek,mt7623-infracfg", "syscon";
 107                 reg = <0x10001000 0x1000>;
 108                 #clock-cells = <1>;
 109                 u-boot,dm-pre-reloc;
 110         };
 111
 112         pericfg: syscon@10003000 {
 113                 compatible = "mediatek,mt7623-pericfg", "syscon";
 114                 reg = <0x10003000 0x1000>;
 115                 #clock-cells = <1>;
 116                 u-boot,dm-pre-reloc;
 117         };
 118
 119         pinctrl: pinctrl@10005000 {
 120                 compatible = "mediatek,mt7623-pinctrl";
 121                 reg = <0x10005000 0x1000>;
 122
 123                 gpio: gpio-controller {
 124                         gpio-controller;
 125                         #gpio-cells = <2>;
 126                 };
 127         };
 128
 129         scpsys: scpsys@10006000 {
 130                 compatible = "mediatek,mt7623-scpsys";
 131                 #power-domain-cells = <1>;
 132                 reg = <0x10006000 0x1000>;
 133                 infracfg = <&infracfg>;
 134                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 135                          <&topckgen CLK_TOP_MFG_SEL>,
 136                          <&topckgen CLK_TOP_ETHIF_SEL>;
 137                 clock-names = "mm", "mfg", "ethif";
 138         };
 139
 140         watchdog: watchdog@10007000 {
 141                 compatible = "mediatek,wdt";
 142                 reg = <0x10007000 0x100>;
 143         };
 144
 145         wdt-reboot {
 146                 compatible = "wdt-reboot";
 147                 wdt = <&watchdog>;
 148         };
 149
 150         timer0: timer@10008000 {
 151                 compatible = "mediatek,timer";
 152                 reg = <0x10008000 0x80>;
 153                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 154                 clocks = <&system_clk>;
 155                 clock-names = "system-clk";
 156                 u-boot,dm-pre-reloc;
 157         };
 158
 159         sysirq: interrupt-controller@10200100 {
 160                 compatible = "mediatek,sysirq";
 161                 interrupt-controller;
 162                 #interrupt-cells = <3>;
 163                 interrupt-parent = <&gic>;
 164                 reg = <0x10200100 0x1c>;
 165         };
 166
 167         apmixedsys: clock-controller@10209000 {
 168                 compatible = "mediatek,mt7623-apmixedsys";
 169                 reg = <0x10209000 0x1000>;
 170                 #clock-cells = <1>;
 171                 u-boot,dm-pre-reloc;
 172         };
 173
 174         gic: interrupt-controller@10211000 {
 175                 compatible = "arm,cortex-a7-gic";
 176                 interrupt-controller;
 177                 #interrupt-cells = <3>;
 178                 interrupt-parent = <&gic>;
 179                 reg = <0x10211000 0x1000>,
 180                       <0x10212000 0x1000>,
 181                       <0x10214000 0x2000>,
 182                       <0x10216000 0x2000>;
 183         };
 184
 185         uart0: serial@11002000 {
 186                 compatible = "mediatek,hsuart";
 187                 reg = <0x11002000 0x400>;
 188                 reg-shift = <2>;
 189                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 190                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 191                          <&pericfg CLK_PERI_UART0>;
 192                 clock-names = "baud", "bus";
 193                 status = "disabled";
 194         };
 195
 196         uart1: serial@11003000 {
 197                 compatible = "mediatek,hsuart";
 198                 reg = <0x11003000 0x400>;
 199                 reg-shift = <2>;
 200                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 201                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 202                          <&pericfg CLK_PERI_UART1>;
 203                 clock-names = "baud", "bus";
 204                 status = "disabled";
 205         };
 206
 207         uart2: serial@11004000 {
 208                 compatible = "mediatek,hsuart";
 209                 reg = <0x11004000 0x400>;
 210                 reg-shift = <2>;
 211                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 212                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 213                          <&pericfg CLK_PERI_UART2>;
 214                 clock-names = "baud", "bus";
 215                 status = "disabled";
 216                 u-boot,dm-pre-reloc;
 217         };
 218
 219         uart3: serial@11005000 {
 220                 compatible = "mediatek,hsuart";
 221                 reg = <0x11005000 0x400>;
 222                 reg-shift = <2>;
 223                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 224                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 225                          <&pericfg CLK_PERI_UART3>;
 226                 clock-names = "baud", "bus";
 227                 status = "disabled";
 228         };
 229
 230         mmc0: mmc@11230000 {
 231                 compatible = "mediatek,mt7623-mmc";
 232                 reg = <0x11230000 0x1000>;
 233                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 234                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 235                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 236                 clock-names = "source", "hclk";
 237                 status = "disabled";
 238         };
 239
 240         mmc1: mmc@11240000 {
 241                 compatible = "mediatek,mt7623-mmc";
 242                 reg = <0x11240000 0x1000>;
 243                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 244                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 245                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 246                 clock-names = "source", "hclk";
 247                 status = "disabled";
 248         };
 249
 250         ethsys: syscon@1b000000 {
 251                 compatible = "mediatek,mt7623-ethsys";
 252                 reg = <0x1b000000 0x1000>;
 253                 #clock-cells = <1>;
 254         };
 255 };