arch/arm/dts/mt7623.dtsi

   1 /*
   2  * Copyright (C) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 #include <dt-bindings/clock/mt7623-clk.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/power/mt7623-power.h>
  14 #include <dt-bindings/reset/mt7623-reset.h>
  15 #include "skeleton.dtsi"
  16
  17 / {
  18         compatible = "mediatek,mt7623";
  19         interrupt-parent = <&sysirq>;
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26                 enable-method = "mediatek,mt6589-smp";
  27
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a7";
  31                         reg = <0x0>;
  32                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  33                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  34                         clock-names = "cpu", "intermediate";
  35                         clock-frequency = <1300000000>;
  36                 };
  37
  38                 cpu1: cpu@1 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a7";
  41                         reg = <0x1>;
  42                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  43                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  44                         clock-names = "cpu", "intermediate";
  45                         clock-frequency = <1300000000>;
  46                 };
  47
  48                 cpu2: cpu@2 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a7";
  51                         reg = <0x2>;
  52                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  53                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  54                         clock-names = "cpu", "intermediate";
  55                         clock-frequency = <1300000000>;
  56                 };
  57
  58                 cpu3: cpu@3 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a7";
  61                         reg = <0x3>;
  62                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  63                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  64                         clock-names = "cpu", "intermediate";
  65                         clock-frequency = <1300000000>;
  66                 };
  67         };
  68
  69         system_clk: dummy13m {
  70                 compatible = "fixed-clock";
  71                 clock-frequency = <13000000>;
  72                 #clock-cells = <0>;
  73         };
  74
  75         rtc32k: oscillator-1 {
  76                 compatible = "fixed-clock";
  77                 #clock-cells = <0>;
  78                 clock-frequency = <32000>;
  79                 clock-output-names = "rtc32k";
  80         };
  81
  82         clk26m: oscillator-0 {
  83                 compatible = "fixed-clock";
  84                 #clock-cells = <0>;
  85                 clock-frequency = <26000000>;
  86                 clock-output-names = "clk26m";
  87         };
  88
  89         timer {
  90                 compatible = "arm,armv7-timer";
  91                 interrupt-parent = <&gic>;
  92                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  93                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  94                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  95                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  96                 clock-frequency = <13000000>;
  97                 arm,cpu-registers-not-fw-configured;
  98         };
  99
 100         topckgen: clock-controller@10000000 {
 101                 compatible = "mediatek,mt7623-topckgen";
 102                 reg = <0x10000000 0x1000>;
 103                 #clock-cells = <1>;
 104                 u-boot,dm-pre-reloc;
 105         };
 106
 107         infracfg: syscon@10001000 {
 108                 compatible = "mediatek,mt7623-infracfg", "syscon";
 109                 reg = <0x10001000 0x1000>;
 110                 #clock-cells = <1>;
 111                 u-boot,dm-pre-reloc;
 112         };
 113
 114         pericfg: syscon@10003000 {
 115                 compatible = "mediatek,mt7623-pericfg", "syscon";
 116                 reg = <0x10003000 0x1000>;
 117                 #clock-cells = <1>;
 118                 u-boot,dm-pre-reloc;
 119         };
 120
 121         pinctrl: pinctrl@10005000 {
 122                 compatible = "mediatek,mt7623-pinctrl";
 123                 reg = <0x10005000 0x1000>;
 124
 125                 gpio: gpio-controller {
 126                         gpio-controller;
 127                         #gpio-cells = <2>;
 128                 };
 129         };
 130
 131         scpsys: scpsys@10006000 {
 132                 compatible = "mediatek,mt7623-scpsys";
 133                 #power-domain-cells = <1>;
 134                 reg = <0x10006000 0x1000>;
 135                 infracfg = <&infracfg>;
 136                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 137                          <&topckgen CLK_TOP_MFG_SEL>,
 138                          <&topckgen CLK_TOP_ETHIF_SEL>;
 139                 clock-names = "mm", "mfg", "ethif";
 140         };
 141
 142         watchdog: watchdog@10007000 {
 143                 compatible = "mediatek,wdt";
 144                 reg = <0x10007000 0x100>;
 145         };
 146
 147         wdt-reboot {
 148                 compatible = "wdt-reboot";
 149                 wdt = <&watchdog>;
 150         };
 151
 152         timer0: timer@10008000 {
 153                 compatible = "mediatek,timer";
 154                 reg = <0x10008000 0x80>;
 155                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 156                 clocks = <&system_clk>;
 157                 clock-names = "system-clk";
 158                 u-boot,dm-pre-reloc;
 159         };
 160
 161         sysirq: interrupt-controller@10200100 {
 162                 compatible = "mediatek,sysirq";
 163                 interrupt-controller;
 164                 #interrupt-cells = <3>;
 165                 interrupt-parent = <&gic>;
 166                 reg = <0x10200100 0x1c>;
 167         };
 168
 169         apmixedsys: clock-controller@10209000 {
 170                 compatible = "mediatek,mt7623-apmixedsys";
 171                 reg = <0x10209000 0x1000>;
 172                 #clock-cells = <1>;
 173                 u-boot,dm-pre-reloc;
 174         };
 175
 176         gic: interrupt-controller@10211000 {
 177                 compatible = "arm,cortex-a7-gic";
 178                 interrupt-controller;
 179                 #interrupt-cells = <3>;
 180                 interrupt-parent = <&gic>;
 181                 reg = <0x10211000 0x1000>,
 182                       <0x10212000 0x1000>,
 183                       <0x10214000 0x2000>,
 184                       <0x10216000 0x2000>;
 185         };
 186
 187         uart0: serial@11002000 {
 188                 compatible = "mediatek,hsuart";
 189                 reg = <0x11002000 0x400>;
 190                 reg-shift = <2>;
 191                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 192                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 193                          <&pericfg CLK_PERI_UART0>;
 194                 clock-names = "baud", "bus";
 195                 status = "disabled";
 196         };
 197
 198         uart1: serial@11003000 {
 199                 compatible = "mediatek,hsuart";
 200                 reg = <0x11003000 0x400>;
 201                 reg-shift = <2>;
 202                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 203                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 204                          <&pericfg CLK_PERI_UART1>;
 205                 clock-names = "baud", "bus";
 206                 status = "disabled";
 207         };
 208
 209         uart2: serial@11004000 {
 210                 compatible = "mediatek,hsuart";
 211                 reg = <0x11004000 0x400>;
 212                 reg-shift = <2>;
 213                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 214                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 215                          <&pericfg CLK_PERI_UART2>;
 216                 clock-names = "baud", "bus";
 217                 status = "disabled";
 218                 u-boot,dm-pre-reloc;
 219         };
 220
 221         uart3: serial@11005000 {
 222                 compatible = "mediatek,hsuart";
 223                 reg = <0x11005000 0x400>;
 224                 reg-shift = <2>;
 225                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 226                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 227                          <&pericfg CLK_PERI_UART3>;
 228                 clock-names = "baud", "bus";
 229                 status = "disabled";
 230         };
 231
 232         mmc0: mmc@11230000 {
 233                 compatible = "mediatek,mt7623-mmc";
 234                 reg = <0x11230000 0x1000>;
 235                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 236                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 237                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 238                 clock-names = "source", "hclk";
 239                 status = "disabled";
 240         };
 241
 242         mmc1: mmc@11240000 {
 243                 compatible = "mediatek,mt7623-mmc";
 244                 reg = <0x11240000 0x1000>;
 245                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 246                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 247                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 248                 clock-names = "source", "hclk";
 249                 status = "disabled";
 250         };
 251
 252         hifsys: syscon@1a000000 {
 253                 compatible = "mediatek,mt7623-hifsys", "syscon";
 254                 reg = <0x1a000000 0x1000>;
 255                 #clock-cells = <1>;
 256                 #reset-cells = <1>;
 257         };
 258
 259         pcie: pcie@1a140000 {
 260                 compatible = "mediatek,mt7623-pcie";
 261                 device_type = "pci";
 262                 reg = <0x1a140000 0x1000>, /* PCIe shared registers */
 263                       <0x1a142000 0x1000>, /* Port0 registers */
 264                       <0x1a143000 0x1000>, /* Port1 registers */
 265                       <0x1a144000 0x1000>; /* Port2 registers */
 266                 reg-names = "subsys", "port0", "port1", "port2";
 267                 #address-cells = <3>;
 268                 #size-cells = <2>;
 269                 #interrupt-cells = <1>;
 270                 interrupt-map-mask = <0xf800 0 0 0>;
 271                 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
 272                                 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
 273                                 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 274                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 275                          <&hifsys CLK_HIFSYS_PCIE0>,
 276                          <&hifsys CLK_HIFSYS_PCIE1>,
 277                          <&hifsys CLK_HIFSYS_PCIE2>;
 278                 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
 279                 resets = <&hifsys HIFSYS_PCIE0_RST>,
 280                          <&hifsys HIFSYS_PCIE1_RST>,
 281                          <&hifsys HIFSYS_PCIE2_RST>;
 282                 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
 283                 phys = <&pcie0_port PHY_TYPE_PCIE>,
 284                        <&pcie1_port PHY_TYPE_PCIE>,
 285                        <&u3port1 PHY_TYPE_PCIE>;
 286                 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
 287                 power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
 288                 bus-range = <0x00 0xff>;
 289                 status = "disabled";
 290                 ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000
 291                           0x83000000 0 0x60000000 0x60000000 0 0x10000000>;
 292
 293                 pcie@0,0 {
 294                         reg = <0x0000 0 0 0 0>;
 295                         #address-cells = <3>;
 296                         #size-cells = <2>;
 297                         #interrupt-cells = <1>;
 298                         interrupt-map-mask = <0 0 0 0>;
 299                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
 300                         ranges;
 301                         status = "disabled";
 302                 };
 303
 304                 pcie@1,0 {
 305                         reg = <0x0800 0 0 0 0>;
 306                         #address-cells = <3>;
 307                         #size-cells = <2>;
 308                         #interrupt-cells = <1>;
 309                         interrupt-map-mask = <0 0 0 0>;
 310                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
 311                         ranges;
 312                         status = "disabled";
 313                 };
 314
 315                 pcie@2,0 {
 316                         reg = <0x1000 0 0 0 0>;
 317                         #address-cells = <3>;
 318                         #size-cells = <2>;
 319                         #interrupt-cells = <1>;
 320                         interrupt-map-mask = <0 0 0 0>;
 321                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 322                         ranges;
 323                         status = "disabled";
 324                 };
 325         };
 326
 327         pcie0_phy: pcie-phy@1a149000 {
 328                 compatible = "mediatek,generic-tphy-v1";
 329                 reg = <0x1a149000 0x0700>;
 330                 #address-cells = <1>;
 331                 #size-cells = <1>;
 332                 ranges;
 333                 status = "disabled";
 334
 335                 pcie0_port: pcie-phy@1a149900 {
 336                         reg = <0x1a149900 0x0700>;
 337                         clocks = <&clk26m>;
 338                         clock-names = "ref";
 339                         #phy-cells = <1>;
 340                         status = "okay";
 341                 };
 342         };
 343
 344         pcie1_phy: pcie-phy@1a14a000 {
 345                 compatible = "mediatek,generic-tphy-v1";
 346                 reg = <0x1a14a000 0x0700>;
 347                 #address-cells = <1>;
 348                 #size-cells = <1>;
 349                 ranges;
 350                 status = "disabled";
 351
 352                 pcie1_port: pcie-phy@1a14a900 {
 353                         reg = <0x1a14a900 0x0700>;
 354                         clocks = <&clk26m>;
 355                         clock-names = "ref";
 356                         #phy-cells = <1>;
 357                         status = "okay";
 358                 };
 359         };
 360
 361         u3phy2: usb-phy@1a244000 {
 362                 compatible = "mediatek,generic-tphy-v1";
 363                 reg = <0x1a244000 0x0700>;
 364                 #address-cells = <1>;
 365                 #size-cells = <1>;
 366                 ranges;
 367                 status = "disabled";
 368
 369                 u2port1: usb-phy@1a244800 {
 370                         reg = <0x1a244800 0x0100>;
 371                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 372                         clock-names = "ref";
 373                         #phy-cells = <1>;
 374                         status = "okay";
 375                 };
 376
 377                 u3port1: usb-phy@1a244900 {
 378                         reg = <0x1a244900 0x0700>;
 379                         clocks = <&clk26m>;
 380                         clock-names = "ref";
 381                         #phy-cells = <1>;
 382                         status = "okay";
 383                 };
 384         };
 385
 386         ethsys: syscon@1b000000 {
 387                 compatible = "mediatek,mt7623-ethsys", "syscon";
 388                 reg = <0x1b000000 0x1000>;
 389                 #clock-cells = <1>;
 390                 #reset-cells = <1>;
 391         };
 392
 393         eth: ethernet@1b100000 {
 394                 compatible = "mediatek,mt7623-eth", "syscon";
 395                 reg = <0x1b100000 0x20000>;
 396                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 397                          <&ethsys CLK_ETHSYS_ESW>,
 398                          <&ethsys CLK_ETHSYS_GP1>,
 399                          <&ethsys CLK_ETHSYS_GP2>,
 400                          <&apmixedsys CLK_APMIXED_TRGPLL>;
 401                 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 402                 power-domains = <&scpsys MT7623_POWER_DOMAIN_ETH>;
 403                 resets = <&ethsys ETHSYS_FE_RST>,
 404                          <&ethsys ETHSYS_MCM_RST>;
 405                 reset-names = "fe", "mcm";
 406                 mediatek,ethsys = <&ethsys>;
 407                 status = "disabled";
 408         };
 409 };