1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
19 compatible = "amlogic,meson-gxl-dwc3";
24 clocks = <&clkc CLKID_USB>;
25 clock-names = "usb_general";
26 resets = <&reset RESET_USB_OTG>;
27 reset-names = "usb_otg";
30 compatible = "snps,dwc3";
31 reg = <0x0 0xc9000000 0x0 0x100000>;
32 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
34 maximum-speed = "high-speed";
35 snps,dis_u2_susphy_quirk;
36 phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
43 usb2_phy0: phy@78000 {
44 compatible = "amlogic,meson-gxl-usb2-phy";
46 reg = <0x0 0x78000 0x0 0x20>;
47 clocks = <&clkc CLKID_USB>;
49 resets = <&reset RESET_USB_OTG>;
54 usb2_phy1: phy@78020 {
55 compatible = "amlogic,meson-gxl-usb2-phy";
57 reg = <0x0 0x78020 0x0 0x20>;
58 clocks = <&clkc CLKID_USB>;
60 resets = <&reset RESET_USB_OTG>;
66 compatible = "amlogic,meson-gxl-usb3-phy";
68 reg = <0x0 0x78080 0x0 0x20>;
69 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
70 clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
71 clock-names = "phy", "peripheral";
72 resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
73 reset-names = "phy", "peripheral";
79 reg = <0x0 0xc9410000 0x0 0x10000
80 0x0 0xc8834540 0x0 0x4>;
82 clocks = <&clkc CLKID_ETH>,
83 <&clkc CLKID_FCLK_DIV2>,
85 clock-names = "stmmaceth", "clkin0", "clkin1";
90 compatible = "snps,dwmac-mdio";
95 pinctrl_aobus: pinctrl@14 {
96 compatible = "amlogic,meson-gxl-aobus-pinctrl";
102 reg = <0x0 0x00014 0x0 0x8>,
103 <0x0 0x0002c 0x0 0x4>,
104 <0x0 0x00024 0x0 0x8>;
105 reg-names = "mux", "pull", "gpio";
108 gpio-ranges = <&pinctrl_aobus 0 0 14>;
111 uart_ao_a_pins: uart_ao_a {
113 groups = "uart_tx_ao_a", "uart_rx_ao_a";
114 function = "uart_ao";
118 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
120 groups = "uart_cts_ao_a",
122 function = "uart_ao";
126 uart_ao_b_pins: uart_ao_b {
128 groups = "uart_tx_ao_b", "uart_rx_ao_b";
129 function = "uart_ao_b";
133 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
135 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
136 function = "uart_ao_b";
140 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
142 groups = "uart_cts_ao_b",
144 function = "uart_ao_b";
148 remote_input_ao_pins: remote_input_ao {
150 groups = "remote_input_ao";
151 function = "remote_input_ao";
155 i2c_ao_pins: i2c_ao {
157 groups = "i2c_sck_ao",
163 pwm_ao_a_3_pins: pwm_ao_a_3 {
165 groups = "pwm_ao_a_3";
166 function = "pwm_ao_a";
170 pwm_ao_a_8_pins: pwm_ao_a_8 {
172 groups = "pwm_ao_a_8";
173 function = "pwm_ao_a";
177 pwm_ao_b_pins: pwm_ao_b {
180 function = "pwm_ao_b";
184 pwm_ao_b_6_pins: pwm_ao_b_6 {
186 groups = "pwm_ao_b_6";
187 function = "pwm_ao_b";
191 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
193 groups = "i2s_out_ch23_ao";
194 function = "i2s_out_ao";
198 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
200 groups = "i2s_out_ch45_ao";
201 function = "i2s_out_ao";
205 spdif_out_ao_6_pins: spdif_out_ao_6 {
207 groups = "spdif_out_ao_6";
208 function = "spdif_out_ao";
212 spdif_out_ao_9_pins: spdif_out_ao_9 {
214 groups = "spdif_out_ao_9";
215 function = "spdif_out_ao";
219 ao_cec_pins: ao_cec {
226 ee_cec_pins: ee_cec {
236 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
237 clock-names = "core";
241 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
245 compatible = "amlogic,meson-gpio-intc",
246 "amlogic,meson-gxl-gpio-intc";
251 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
252 resets = <&reset RESET_HDMITX_CAPB3>,
253 <&reset RESET_HDMI_SYSTEM_RESET>,
254 <&reset RESET_HDMI_TX>;
255 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
256 clocks = <&clkc CLKID_HDMI_PCLK>,
258 <&clkc CLKID_GCLK_VENCI_INT0>;
259 clock-names = "isfr", "iahb", "venci";
263 clkc: clock-controller {
264 compatible = "amlogic,gxl-clkc";
270 clocks = <&clkc CLKID_I2C>;
274 clocks = <&clkc CLKID_AO_I2C>;
278 clocks = <&clkc CLKID_I2C>;
282 clocks = <&clkc CLKID_I2C>;
286 pinctrl_periphs: pinctrl@4b0 {
287 compatible = "amlogic,meson-gxl-periphs-pinctrl";
288 #address-cells = <2>;
293 reg = <0x0 0x004b0 0x0 0x28>,
294 <0x0 0x004e8 0x0 0x14>,
295 <0x0 0x00520 0x0 0x14>,
296 <0x0 0x00430 0x0 0x40>;
297 reg-names = "mux", "pull", "pull-enable", "gpio";
300 gpio-ranges = <&pinctrl_periphs 0 0 100>;
305 groups = "emmc_nand_d07",
312 emmc_ds_pins: emmc-ds {
319 emmc_clk_gate_pins: emmc_clk_gate {
322 function = "gpio_periphs";
349 spi_ss0_pins: spi-ss0 {
356 sdcard_pins: sdcard {
358 groups = "sdcard_d0",
368 sdcard_clk_gate_pins: sdcard_clk_gate {
371 function = "gpio_periphs";
391 sdio_clk_gate_pins: sdio_clk_gate {
394 function = "gpio_periphs";
402 sdio_irq_pins: sdio_irq {
409 uart_a_pins: uart_a {
411 groups = "uart_tx_a",
417 uart_a_cts_rts_pins: uart_a_cts_rts {
419 groups = "uart_cts_a",
425 uart_b_pins: uart_b {
427 groups = "uart_tx_b",
433 uart_b_cts_rts_pins: uart_b_cts_rts {
435 groups = "uart_cts_b",
441 uart_c_pins: uart_c {
443 groups = "uart_tx_c",
449 uart_c_cts_rts_pins: uart_c_cts_rts {
451 groups = "uart_cts_c",
459 groups = "i2c_sck_a",
467 groups = "i2c_sck_b",
475 groups = "i2c_sck_c",
501 eth_link_led_pins: eth_link_led {
503 groups = "eth_link_led";
504 function = "eth_led";
508 eth_act_led_pins: eth_act_led {
510 groups = "eth_act_led";
511 function = "eth_led";
550 pwm_f_clk_pins: pwm_f_clk {
552 groups = "pwm_f_clk";
557 pwm_f_x_pins: pwm_f_x {
564 hdmi_hpd_pins: hdmi_hpd {
567 function = "hdmi_hpd";
571 hdmi_i2c_pins: hdmi_i2c {
573 groups = "hdmi_sda", "hdmi_scl";
574 function = "hdmi_i2c";
578 i2s_am_clk_pins: i2s_am_clk {
580 groups = "i2s_am_clk";
581 function = "i2s_out";
585 i2s_out_ao_clk_pins: i2s_out_ao_clk {
587 groups = "i2s_out_ao_clk";
588 function = "i2s_out";
592 i2s_out_lr_clk_pins: i2s_out_lr_clk {
594 groups = "i2s_out_lr_clk";
595 function = "i2s_out";
599 i2s_out_ch01_pins: i2s_out_ch01 {
601 groups = "i2s_out_ch01";
602 function = "i2s_out";
605 i2sout_ch23_z_pins: i2sout_ch23_z {
607 groups = "i2sout_ch23_z";
608 function = "i2s_out";
612 i2sout_ch45_z_pins: i2sout_ch45_z {
614 groups = "i2sout_ch45_z";
615 function = "i2s_out";
619 i2sout_ch67_z_pins: i2sout_ch67_z {
621 groups = "i2sout_ch67_z";
622 function = "i2s_out";
626 spdif_out_h_pins: spdif_out_ao_h {
628 groups = "spdif_out_h";
629 function = "spdif_out";
635 compatible = "mdio-mux-mmioreg", "mdio-mux";
636 #address-cells = <1>;
638 reg = <0x0 0x55c 0x0 0x4>;
639 mux-mask = <0xffffffff>;
640 mdio-parent-bus = <&mdio0>;
642 internal_mdio: mdio@e40908ff {
644 #address-cells = <1>;
647 internal_phy: ethernet-phy@8 {
648 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
649 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
655 external_mdio: mdio@2009087f {
657 #address-cells = <1>;
664 resets = <&reset RESET_VIU>,
666 <&reset RESET_VCBUS>,
667 <&reset RESET_BT656>,
668 <&reset RESET_DVIN_RESET>,
670 <&reset RESET_VENCI>,
671 <&reset RESET_VENCP>,
674 <&reset RESET_VENCL>,
675 <&reset RESET_VID_LOCK>;
676 clocks = <&clkc CLKID_VPU>,
678 clock-names = "vpu", "vapb";
680 * VPU clocking is provided by two identical clock paths
681 * VPU_0 and VPU_1 muxed to a single clock by a glitch
682 * free mux to safely change frequency while running.
683 * Same for VAPB but with a final gate after the glitch free mux.
685 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
687 <&clkc CLKID_VPU>, /* Glitch free mux */
688 <&clkc CLKID_VAPB_0_SEL>,
689 <&clkc CLKID_VAPB_0>,
690 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
691 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
692 <0>, /* Do Nothing */
694 <&clkc CLKID_FCLK_DIV4>,
695 <0>, /* Do Nothing */
696 <&clkc CLKID_VAPB_0>;
697 assigned-clock-rates = <0>, /* Do Nothing */
699 <0>, /* Do Nothing */
700 <0>, /* Do Nothing */
702 <0>; /* Do Nothing */
706 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
708 <&clkc CLKID_SAR_ADC>,
709 <&clkc CLKID_SAR_ADC_CLK>,
710 <&clkc CLKID_SAR_ADC_SEL>;
711 clock-names = "clkin", "core", "adc_clk", "adc_sel";
715 clocks = <&clkc CLKID_SD_EMMC_A>,
716 <&clkc CLKID_SD_EMMC_A_CLK0>,
717 <&clkc CLKID_FCLK_DIV2>;
718 clock-names = "core", "clkin0", "clkin1";
719 resets = <&reset RESET_SD_EMMC_A>;
723 clocks = <&clkc CLKID_SD_EMMC_B>,
724 <&clkc CLKID_SD_EMMC_B_CLK0>,
725 <&clkc CLKID_FCLK_DIV2>;
726 clock-names = "core", "clkin0", "clkin1";
727 resets = <&reset RESET_SD_EMMC_B>;
731 clocks = <&clkc CLKID_SD_EMMC_C>,
732 <&clkc CLKID_SD_EMMC_C_CLK0>,
733 <&clkc CLKID_FCLK_DIV2>;
734 clock-names = "core", "clkin0", "clkin1";
735 resets = <&reset RESET_SD_EMMC_C>;
739 clocks = <&clkc CLKID_SPICC>;
740 clock-names = "core";
741 resets = <&reset RESET_PERIPHS_SPICC>;
746 clocks = <&clkc CLKID_SPI>;
750 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
751 clock-names = "xtal", "pclk", "baud";
755 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
756 clock-names = "xtal", "pclk", "baud";
760 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
761 clock-names = "xtal", "pclk", "baud";
765 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
766 clock-names = "xtal", "pclk", "baud";
770 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
771 clock-names = "xtal", "pclk", "baud";
775 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
776 power-domains = <&pwrc_vpu>;