1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Andreas Färber
6 #include "meson-gx.dtsi"
7 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
8 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9 #include <dt-bindings/clock/gxbb-clkc.h>
10 #include <dt-bindings/clock/gxbb-aoclkc.h>
11 #include <dt-bindings/reset/gxbb-aoclkc.h>
14 compatible = "amlogic,meson-gxbb";
17 usb0_phy: phy@c0000000 {
18 compatible = "amlogic,meson-gxbb-usb2-phy";
20 reg = <0x0 0xc0000000 0x0 0x20>;
21 resets = <&reset RESET_USB_OTG>;
22 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23 clock-names = "usb_general", "usb";
27 usb1_phy: phy@c0000020 {
28 compatible = "amlogic,meson-gxbb-usb2-phy";
30 reg = <0x0 0xc0000020 0x0 0x20>;
31 resets = <&reset RESET_USB_OTG>;
32 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33 clock-names = "usb_general", "usb";
38 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
39 reg = <0x0 0xc9000000 0x0 0x40000>;
40 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
44 phy-names = "usb2-phy";
50 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
51 reg = <0x0 0xc9100000 0x0 0x40000>;
52 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
53 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
56 phy-names = "usb2-phy";
64 pinctrl_aobus: pinctrl@14 {
65 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
71 reg = <0x0 0x00014 0x0 0x8>,
72 <0x0 0x0002c 0x0 0x4>,
73 <0x0 0x00024 0x0 0x8>;
74 reg-names = "mux", "pull", "gpio";
77 gpio-ranges = <&pinctrl_aobus 0 0 14>;
80 uart_ao_a_pins: uart_ao_a {
82 groups = "uart_tx_ao_a", "uart_rx_ao_a";
87 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
89 groups = "uart_cts_ao_a",
95 uart_ao_b_pins: uart_ao_b {
97 groups = "uart_tx_ao_b", "uart_rx_ao_b";
98 function = "uart_ao_b";
102 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
104 groups = "uart_cts_ao_b",
106 function = "uart_ao_b";
110 remote_input_ao_pins: remote_input_ao {
112 groups = "remote_input_ao";
113 function = "remote_input_ao";
117 i2c_ao_pins: i2c_ao {
119 groups = "i2c_sck_ao",
125 pwm_ao_a_3_pins: pwm_ao_a_3 {
127 groups = "pwm_ao_a_3";
128 function = "pwm_ao_a_3";
132 pwm_ao_a_6_pins: pwm_ao_a_6 {
134 groups = "pwm_ao_a_6";
135 function = "pwm_ao_a_6";
139 pwm_ao_a_12_pins: pwm_ao_a_12 {
141 groups = "pwm_ao_a_12";
142 function = "pwm_ao_a_12";
146 pwm_ao_b_pins: pwm_ao_b {
149 function = "pwm_ao_b";
153 i2s_am_clk_pins: i2s_am_clk {
155 groups = "i2s_am_clk";
156 function = "i2s_out_ao";
160 i2s_out_ao_clk_pins: i2s_out_ao_clk {
162 groups = "i2s_out_ao_clk";
163 function = "i2s_out_ao";
167 i2s_out_lr_clk_pins: i2s_out_lr_clk {
169 groups = "i2s_out_lr_clk";
170 function = "i2s_out_ao";
174 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
176 groups = "i2s_out_ch01_ao";
177 function = "i2s_out_ao";
181 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
183 groups = "i2s_out_ch23_ao";
184 function = "i2s_out_ao";
188 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
190 groups = "i2s_out_ch45_ao";
191 function = "i2s_out_ao";
195 spdif_out_ao_6_pins: spdif_out_ao_6 {
197 groups = "spdif_out_ao_6";
198 function = "spdif_out_ao";
202 spdif_out_ao_13_pins: spdif_out_ao_13 {
204 groups = "spdif_out_ao_13";
205 function = "spdif_out_ao";
209 ao_cec_pins: ao_cec {
216 ee_cec_pins: ee_cec {
227 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
228 reg = <0x0 0xc0000 0x0 0x40000>;
229 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
239 interrupt-names = "gp", "gpmmu", "pp", "pmu",
240 "pp0", "ppmmu0", "pp1", "ppmmu1",
242 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
243 clock-names = "bus", "core";
246 * Mali clocking is provided by two identical clock paths
247 * MALI_0 and MALI_1 muxed to a single clock by a glitch
248 * free mux to safely change frequency while running.
250 assigned-clocks = <&clkc CLKID_GP0_PLL>,
251 <&clkc CLKID_MALI_0_SEL>,
252 <&clkc CLKID_MALI_0>,
253 <&clkc CLKID_MALI>; /* Glitch free mux */
254 assigned-clock-parents = <0>, /* Do Nothing */
255 <&clkc CLKID_GP0_PLL>,
256 <0>, /* Do Nothing */
257 <&clkc CLKID_MALI_0>;
258 assigned-clock-rates = <744000000>,
259 <0>, /* Do Nothing */
261 <0>; /* Do Nothing */
267 compatible = "amlogic,meson-gxbb-spifc";
268 reg = <0x0 0x08c80 0x0 0x80>;
269 #address-cells = <1>;
271 clocks = <&clkc CLKID_SPI>;
277 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
278 clock-names = "core";
282 compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
286 clocks = <&clkc CLKID_ETH>,
287 <&clkc CLKID_FCLK_DIV2>,
289 clock-names = "stmmaceth", "clkin0", "clkin1";
293 compatible = "amlogic,meson-gpio-intc",
294 "amlogic,meson-gxbb-gpio-intc";
299 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
300 resets = <&reset RESET_HDMITX_CAPB3>,
301 <&reset RESET_HDMI_SYSTEM_RESET>,
302 <&reset RESET_HDMI_TX>;
303 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
304 clocks = <&clkc CLKID_HDMI_PCLK>,
306 <&clkc CLKID_GCLK_VENCI_INT0>;
307 clock-names = "isfr", "iahb", "venci";
311 clkc: clock-controller {
312 compatible = "amlogic,gxbb-clkc";
318 clocks = <&clkc CLKID_RNG0>;
319 clock-names = "core";
323 clocks = <&clkc CLKID_I2C>;
327 clocks = <&clkc CLKID_AO_I2C>;
331 clocks = <&clkc CLKID_I2C>;
335 clocks = <&clkc CLKID_I2C>;
339 pinctrl_periphs: pinctrl@4b0 {
340 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
341 #address-cells = <2>;
346 reg = <0x0 0x004b0 0x0 0x28>,
347 <0x0 0x004e8 0x0 0x14>,
348 <0x0 0x00520 0x0 0x14>,
349 <0x0 0x00430 0x0 0x40>;
350 reg-names = "mux", "pull", "pull-enable", "gpio";
353 gpio-ranges = <&pinctrl_periphs 0 0 119>;
358 groups = "emmc_nand_d07",
365 emmc_ds_pins: emmc-ds {
372 emmc_clk_gate_pins: emmc_clk_gate {
375 function = "gpio_periphs";
402 spi_ss0_pins: spi-ss0 {
409 sdcard_pins: sdcard {
411 groups = "sdcard_d0",
421 sdcard_clk_gate_pins: sdcard_clk_gate {
424 function = "gpio_periphs";
444 sdio_clk_gate_pins: sdio_clk_gate {
447 function = "gpio_periphs";
455 sdio_irq_pins: sdio_irq {
462 uart_a_pins: uart_a {
464 groups = "uart_tx_a",
470 uart_a_cts_rts_pins: uart_a_cts_rts {
472 groups = "uart_cts_a",
478 uart_b_pins: uart_b {
480 groups = "uart_tx_b",
486 uart_b_cts_rts_pins: uart_b_cts_rts {
488 groups = "uart_cts_b",
494 uart_c_pins: uart_c {
496 groups = "uart_tx_c",
502 uart_c_cts_rts_pins: uart_c_cts_rts {
504 groups = "uart_cts_c",
512 groups = "i2c_sck_a",
520 groups = "i2c_sck_b",
528 groups = "i2c_sck_c",
534 eth_rgmii_pins: eth-rgmii {
554 eth_rmii_pins: eth-rmii {
569 pwm_a_x_pins: pwm_a_x {
572 function = "pwm_a_x";
576 pwm_a_y_pins: pwm_a_y {
579 function = "pwm_a_y";
604 pwm_f_x_pins: pwm_f_x {
607 function = "pwm_f_x";
611 pwm_f_y_pins: pwm_f_y {
614 function = "pwm_f_y";
618 hdmi_hpd_pins: hdmi_hpd {
621 function = "hdmi_hpd";
625 hdmi_i2c_pins: hdmi_i2c {
627 groups = "hdmi_sda", "hdmi_scl";
628 function = "hdmi_i2c";
632 i2sout_ch23_y_pins: i2sout_ch23_y {
634 groups = "i2sout_ch23_y";
635 function = "i2s_out";
639 i2sout_ch45_y_pins: i2sout_ch45_y {
641 groups = "i2sout_ch45_y";
642 function = "i2s_out";
646 i2sout_ch67_y_pins: i2sout_ch67_y {
648 groups = "i2sout_ch67_y";
649 function = "i2s_out";
653 spdif_out_y_pins: spdif_out_y {
655 groups = "spdif_out_y";
656 function = "spdif_out";
663 resets = <&reset RESET_VIU>,
665 <&reset RESET_VCBUS>,
666 <&reset RESET_BT656>,
667 <&reset RESET_DVIN_RESET>,
669 <&reset RESET_VENCI>,
670 <&reset RESET_VENCP>,
673 <&reset RESET_VENCL>,
674 <&reset RESET_VID_LOCK>;
675 clocks = <&clkc CLKID_VPU>,
677 clock-names = "vpu", "vapb";
679 * VPU clocking is provided by two identical clock paths
680 * VPU_0 and VPU_1 muxed to a single clock by a glitch
681 * free mux to safely change frequency while running.
682 * Same for VAPB but with a final gate after the glitch free mux.
684 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
686 <&clkc CLKID_VPU>, /* Glitch free mux */
687 <&clkc CLKID_VAPB_0_SEL>,
688 <&clkc CLKID_VAPB_0>,
689 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
690 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
691 <0>, /* Do Nothing */
693 <&clkc CLKID_FCLK_DIV4>,
694 <0>, /* Do Nothing */
695 <&clkc CLKID_VAPB_0>;
696 assigned-clock-rates = <0>, /* Do Nothing */
698 <0>, /* Do Nothing */
699 <0>, /* Do Nothing */
701 <0>; /* Do Nothing */
705 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
707 <&clkc CLKID_SAR_ADC>,
708 <&clkc CLKID_SAR_ADC_CLK>,
709 <&clkc CLKID_SAR_ADC_SEL>;
710 clock-names = "clkin", "core", "adc_clk", "adc_sel";
714 clocks = <&clkc CLKID_SD_EMMC_A>,
715 <&clkc CLKID_SD_EMMC_A_CLK0>,
716 <&clkc CLKID_FCLK_DIV2>;
717 clock-names = "core", "clkin0", "clkin1";
718 resets = <&reset RESET_SD_EMMC_A>;
722 clocks = <&clkc CLKID_SD_EMMC_B>,
723 <&clkc CLKID_SD_EMMC_B_CLK0>,
724 <&clkc CLKID_FCLK_DIV2>;
725 clock-names = "core", "clkin0", "clkin1";
726 resets = <&reset RESET_SD_EMMC_B>;
730 clocks = <&clkc CLKID_SD_EMMC_C>,
731 <&clkc CLKID_SD_EMMC_C_CLK0>,
732 <&clkc CLKID_FCLK_DIV2>;
733 clock-names = "core", "clkin0", "clkin1";
734 resets = <&reset RESET_SD_EMMC_C>;
738 clocks = <&clkc CLKID_SPICC>;
739 clock-names = "core";
740 resets = <&reset RESET_PERIPHS_SPICC>;
745 clocks = <&clkc CLKID_SPI>;
749 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
750 clock-names = "xtal", "pclk", "baud";
754 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
755 clock-names = "xtal", "pclk", "baud";
759 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
760 clock-names = "xtal", "pclk", "baud";
764 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
765 clock-names = "xtal", "pclk", "baud";
769 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
770 clock-names = "xtal", "pclk", "baud";
774 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
775 power-domains = <&pwrc_vpu>;