1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Andreas Färber
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
8 * Copyright (c) 2016 Endless Computers, Inc.
9 * Author: Carlo Caione <carlo@endlessm.com>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
26 /* 16 MiB reserved for Hardware ROM Firmware */
27 hwrom_reserved: hwrom@0 {
28 reg = <0x0 0x0 0x0 0x1000000>;
32 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
33 secmon_reserved: secmon@10000000 {
34 reg = <0x0 0x10000000 0x0 0x200000>;
38 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
39 secmon_reserved_alt: secmon@5000000 {
40 reg = <0x0 0x05000000 0x0 0x300000>;
45 compatible = "shared-dma-pool";
47 size = <0x0 0x10000000>;
48 alignment = <0x0 0x400000>;
54 #address-cells = <0x2>;
59 compatible = "arm,cortex-a53", "arm,armv8";
61 enable-method = "psci";
62 next-level-cache = <&l2>;
63 clocks = <&scpi_dvfs 0>;
68 compatible = "arm,cortex-a53", "arm,armv8";
70 enable-method = "psci";
71 next-level-cache = <&l2>;
72 clocks = <&scpi_dvfs 0>;
77 compatible = "arm,cortex-a53", "arm,armv8";
79 enable-method = "psci";
80 next-level-cache = <&l2>;
81 clocks = <&scpi_dvfs 0>;
86 compatible = "arm,cortex-a53", "arm,armv8";
88 enable-method = "psci";
89 next-level-cache = <&l2>;
90 clocks = <&scpi_dvfs 0>;
99 compatible = "arm,cortex-a53-pmu";
100 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
104 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
108 compatible = "arm,psci-0.2";
113 compatible = "arm,armv8-timer";
114 interrupts = <GIC_PPI 13
115 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
117 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
119 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
121 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
125 compatible = "fixed-clock";
126 clock-frequency = <24000000>;
127 clock-output-names = "xtal";
133 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
138 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
139 #address-cells = <1>;
147 eth_mac: eth_mac@34 {
157 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
158 mboxes = <&mailbox 1 &mailbox 2>;
159 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
161 scpi_clocks: clocks {
162 compatible = "arm,scpi-clocks";
164 scpi_dvfs: scpi_clocks@0 {
165 compatible = "arm,scpi-dvfs-clocks";
168 clock-output-names = "vcpu";
172 scpi_sensors: sensors {
173 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
174 #thermal-sensor-cells = <1>;
179 compatible = "simple-bus";
180 #address-cells = <2>;
185 compatible = "simple-bus";
186 reg = <0x0 0xc1100000 0x0 0x100000>;
187 #address-cells = <2>;
189 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
191 gpio_intc: interrupt-controller@9880 {
192 compatible = "amlogic,meson-gpio-intc";
193 reg = <0x0 0x9880 0x0 0x10>;
194 interrupt-controller;
195 #interrupt-cells = <2>;
196 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
200 reset: reset-controller@4404 {
201 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
202 reg = <0x0 0x04404 0x0 0x9c>;
206 uart_A: serial@84c0 {
207 compatible = "amlogic,meson-gx-uart";
208 reg = <0x0 0x84c0 0x0 0x18>;
209 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
213 uart_B: serial@84dc {
214 compatible = "amlogic,meson-gx-uart";
215 reg = <0x0 0x84dc 0x0 0x18>;
216 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
221 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
222 reg = <0x0 0x08500 0x0 0x20>;
223 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
224 #address-cells = <1>;
230 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
231 reg = <0x0 0x08550 0x0 0x10>;
237 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
238 reg = <0x0 0x08650 0x0 0x10>;
244 compatible = "amlogic,meson-saradc";
245 reg = <0x0 0x8680 0x0 0x34>;
246 #io-channel-cells = <1>;
247 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
252 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
253 reg = <0x0 0x086c0 0x0 0x10>;
258 uart_C: serial@8700 {
259 compatible = "amlogic,meson-gx-uart";
260 reg = <0x0 0x8700 0x0 0x18>;
261 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
266 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
267 reg = <0x0 0x087c0 0x0 0x20>;
268 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
269 #address-cells = <1>;
275 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
276 reg = <0x0 0x087e0 0x0 0x20>;
277 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
278 #address-cells = <1>;
284 compatible = "amlogic,meson-gx-spicc";
285 reg = <0x0 0x08d80 0x0 0x80>;
286 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
287 #address-cells = <1>;
293 compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
294 reg = <0x0 0x08c80 0x0 0x80>;
295 #address-cells = <1>;
301 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
302 reg = <0x0 0x098d0 0x0 0x10>;
307 gic: interrupt-controller@c4301000 {
308 compatible = "arm,gic-400";
309 reg = <0x0 0xc4301000 0 0x1000>,
310 <0x0 0xc4302000 0 0x2000>,
311 <0x0 0xc4304000 0 0x2000>,
312 <0x0 0xc4306000 0 0x2000>;
313 interrupt-controller;
314 interrupts = <GIC_PPI 9
315 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
316 #interrupt-cells = <3>;
317 #address-cells = <0>;
320 sram: sram@c8000000 {
321 compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
322 reg = <0x0 0xc8000000 0x0 0x14000>;
324 #address-cells = <1>;
326 ranges = <0 0x0 0xc8000000 0x14000>;
328 cpu_scp_lpri: scp-shmem@0 {
329 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
330 reg = <0x13000 0x400>;
333 cpu_scp_hpri: scp-shmem@200 {
334 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
335 reg = <0x13400 0x400>;
339 aobus: bus@c8100000 {
340 compatible = "simple-bus";
341 reg = <0x0 0xc8100000 0x0 0x100000>;
342 #address-cells = <2>;
344 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
346 sysctrl_AO: sys-ctrl@0 {
347 compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
348 reg = <0x0 0x0 0x0 0x100>;
350 pwrc_vpu: power-controller-vpu {
351 compatible = "amlogic,meson-gx-pwrc-vpu";
352 #power-domain-cells = <0>;
353 amlogic,hhi-sysctrl = <&sysctrl>;
356 clkc_AO: clock-controller {
357 compatible = "amlogic,meson-gx-aoclkc";
364 compatible = "amlogic,meson-gx-ao-cec";
365 reg = <0x0 0x00100 0x0 0x14>;
366 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
369 sec_AO: ao-secure@140 {
370 compatible = "amlogic,meson-gx-ao-secure", "syscon";
371 reg = <0x0 0x140 0x0 0x140>;
375 uart_AO: serial@4c0 {
376 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
377 reg = <0x0 0x004c0 0x0 0x18>;
378 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
382 uart_AO_B: serial@4e0 {
383 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
384 reg = <0x0 0x004e0 0x0 0x18>;
385 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
390 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
391 reg = <0x0 0x500 0x0 0x20>;
392 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
393 #address-cells = <1>;
399 compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
400 reg = <0x0 0x00550 0x0 0x10>;
406 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
407 reg = <0x0 0x00580 0x0 0x40>;
408 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
413 periphs: periphs@c8834000 {
414 compatible = "simple-bus";
415 reg = <0x0 0xc8834000 0x0 0x2000>;
416 #address-cells = <2>;
418 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
421 compatible = "amlogic,meson-rng";
422 reg = <0x0 0x0 0x0 0x4>;
426 dmcbus: bus@c8838000 {
427 compatible = "simple-bus";
428 reg = <0x0 0xc8838000 0x0 0x400>;
429 #address-cells = <2>;
431 ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
433 canvas: video-lut@48 {
434 compatible = "amlogic,canvas";
435 reg = <0x0 0x48 0x0 0x14>;
439 hiubus: bus@c883c000 {
440 compatible = "simple-bus";
441 reg = <0x0 0xc883c000 0x0 0x2000>;
442 #address-cells = <2>;
444 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
446 sysctrl: system-controller@0 {
447 compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
451 mailbox: mailbox@404 {
452 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
453 reg = <0 0x404 0 0x4c>;
454 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
455 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
456 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
461 ethmac: ethernet@c9410000 {
462 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
463 reg = <0x0 0xc9410000 0x0 0x10000
464 0x0 0xc8834540 0x0 0x4>;
465 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
466 interrupt-names = "macirq";
471 compatible = "simple-bus";
472 reg = <0x0 0xd0000000 0x0 0x200000>;
473 #address-cells = <2>;
475 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
477 sd_emmc_a: mmc@70000 {
478 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
479 reg = <0x0 0x70000 0x0 0x800>;
480 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
484 sd_emmc_b: mmc@72000 {
485 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
486 reg = <0x0 0x72000 0x0 0x800>;
487 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
491 sd_emmc_c: mmc@74000 {
492 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
493 reg = <0x0 0x74000 0x0 0x800>;
494 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
500 compatible = "amlogic,meson-gx-vpu";
501 reg = <0x0 0xd0100000 0x0 0x100000>,
502 <0x0 0xc883c000 0x0 0x1000>,
503 <0x0 0xc8838000 0x0 0x1000>;
504 reg-names = "vpu", "hhi", "dmc";
505 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
506 #address-cells = <1>;
509 /* CVBS VDAC output port */
510 cvbs_vdac_port: port@0 {
514 /* HDMI-TX output port */
515 hdmi_tx_port: port@1 {
518 hdmi_tx_out: endpoint {
519 remote-endpoint = <&hdmi_tx_in>;
524 hdmi_tx: hdmi-tx@c883a000 {
525 compatible = "amlogic,meson-gx-dw-hdmi";
526 reg = <0x0 0xc883a000 0x0 0x1c>;
527 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
528 #address-cells = <1>;
533 hdmi_tx_venc_port: port@0 {
536 hdmi_tx_in: endpoint {
537 remote-endpoint = <&hdmi_tx_out>;
542 hdmi_tx_tmds_port: port@1 {