1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "amlogic,g12a";
13 interrupt-parent = <&gic>;
18 #address-cells = <0x2>;
23 compatible = "arm,cortex-a53";
25 enable-method = "psci";
26 next-level-cache = <&l2>;
31 compatible = "arm,cortex-a53";
33 enable-method = "psci";
34 next-level-cache = <&l2>;
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 next-level-cache = <&l2>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 next-level-cache = <&l2>;
59 compatible = "arm,psci-1.0";
68 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
69 secmon_reserved: secmon@5000000 {
70 reg = <0x0 0x05000000 0x0 0x300000>;
76 compatible = "simple-bus";
82 compatible = "simple-bus";
83 reg = <0x0 0xff600000 0x0 0x200000>;
86 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
89 compatible = "simple-bus";
90 reg = <0x0 0x34400 0x0 0x400>;
93 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
97 compatible = "simple-bus";
98 reg = <0x0 0x3c000 0x0 0x1400>;
101 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
103 hhi: system-controller@0 {
104 compatible = "amlogic,meson-gx-hhi-sysctrl",
105 "simple-mfd", "syscon";
108 clkc: clock-controller {
109 compatible = "amlogic,g12a-clkc";
112 clock-names = "xtal";
118 aobus: bus@ff800000 {
119 compatible = "simple-bus";
120 reg = <0x0 0xff800000 0x0 0x100000>;
121 #address-cells = <2>;
123 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
125 uart_AO: serial@3000 {
126 compatible = "amlogic,meson-gx-uart",
127 "amlogic,meson-ao-uart";
128 reg = <0x0 0x3000 0x0 0x18>;
129 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
130 clocks = <&xtal>, <&xtal>, <&xtal>;
131 clock-names = "xtal", "pclk", "baud";
135 uart_AO_B: serial@4000 {
136 compatible = "amlogic,meson-gx-uart",
137 "amlogic,meson-ao-uart";
138 reg = <0x0 0x4000 0x0 0x18>;
139 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
140 clocks = <&xtal>, <&xtal>, <&xtal>;
141 clock-names = "xtal", "pclk", "baud";
146 gic: interrupt-controller@ffc01000 {
147 compatible = "arm,gic-400";
148 reg = <0x0 0xffc01000 0 0x1000>,
149 <0x0 0xffc02000 0 0x2000>,
150 <0x0 0xffc04000 0 0x2000>,
151 <0x0 0xffc06000 0 0x2000>;
152 interrupt-controller;
153 interrupts = <GIC_PPI 9
154 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
155 #interrupt-cells = <3>;
156 #address-cells = <0>;
160 compatible = "simple-bus";
161 reg = <0x0 0xffd00000 0x0 0x100000>;
162 #address-cells = <2>;
164 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
166 clk_msr: clock-measure@18000 {
167 compatible = "amlogic,meson-g12a-clk-measure";
168 reg = <0x0 0x18000 0x0 0x10>;
174 compatible = "arm,armv8-timer";
175 interrupts = <GIC_PPI 13
176 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
178 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
180 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
182 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
186 compatible = "fixed-clock";
187 clock-frequency = <24000000>;
188 clock-output-names = "xtal";