1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
6 #include <dt-bindings/clock/axg-aoclkc.h>
7 #include <dt-bindings/clock/axg-audio-clkc.h>
8 #include <dt-bindings/clock/axg-clkc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/gpio/meson-axg-gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
17 compatible = "amlogic,meson-axg";
19 interrupt-parent = <&gic>;
23 tdmif_a: audio-controller@0 {
24 compatible = "amlogic,axg-tdm-iface";
25 #sound-dai-cells = <0>;
26 sound-name-prefix = "TDM_A";
27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
30 clock-names = "mclk", "sclk", "lrclk";
34 tdmif_b: audio-controller@1 {
35 compatible = "amlogic,axg-tdm-iface";
36 #sound-dai-cells = <0>;
37 sound-name-prefix = "TDM_B";
38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
41 clock-names = "mclk", "sclk", "lrclk";
45 tdmif_c: audio-controller@2 {
46 compatible = "amlogic,axg-tdm-iface";
47 #sound-dai-cells = <0>;
48 sound-name-prefix = "TDM_C";
49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
52 clock-names = "mclk", "sclk", "lrclk";
56 ao_alt_xtal: ao_alt_xtal-clk {
57 compatible = "fixed-clock";
58 clock-frequency = <32000000>;
59 clock-output-names = "ao_alt_xtal";
64 compatible = "arm,cortex-a53-pmu";
65 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
73 #address-cells = <0x2>;
78 compatible = "arm,cortex-a53", "arm,armv8";
80 enable-method = "psci";
81 next-level-cache = <&l2>;
86 compatible = "arm,cortex-a53", "arm,armv8";
88 enable-method = "psci";
89 next-level-cache = <&l2>;
94 compatible = "arm,cortex-a53", "arm,armv8";
96 enable-method = "psci";
97 next-level-cache = <&l2>;
102 compatible = "arm,cortex-a53", "arm,armv8";
104 enable-method = "psci";
105 next-level-cache = <&l2>;
109 compatible = "cache";
114 compatible = "arm,psci-1.0";
119 #address-cells = <2>;
123 /* 16 MiB reserved for Hardware ROM Firmware */
124 hwrom_reserved: hwrom@0 {
125 reg = <0x0 0x0 0x0 0x1000000>;
129 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
130 secmon_reserved: secmon@5000000 {
131 reg = <0x0 0x05000000 0x0 0x300000>;
137 compatible = "simple-bus";
138 #address-cells = <2>;
142 ethmac: ethernet@ff3f0000 {
143 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
144 reg = <0x0 0xff3f0000 0x0 0x10000
145 0x0 0xff634540 0x0 0x8>;
146 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
147 interrupt-names = "macirq";
148 clocks = <&clkc CLKID_ETH>,
149 <&clkc CLKID_FCLK_DIV2>,
151 clock-names = "stmmaceth", "clkin0", "clkin1";
155 pdm: audio-controller@ff632000 {
156 compatible = "amlogic,axg-pdm";
157 reg = <0x0 0xff632000 0x0 0x34>;
158 #sound-dai-cells = <0>;
159 sound-name-prefix = "PDM";
160 clocks = <&clkc_audio AUD_CLKID_PDM>,
161 <&clkc_audio AUD_CLKID_PDM_DCLK>,
162 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
163 clock-names = "pclk", "dclk", "sysclk";
167 periphs: bus@ff634000 {
168 compatible = "simple-bus";
169 reg = <0x0 0xff634000 0x0 0x2000>;
170 #address-cells = <2>;
172 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
175 compatible = "amlogic,meson-rng";
176 reg = <0x0 0x18 0x0 0x4>;
177 clocks = <&clkc CLKID_RNG0>;
178 clock-names = "core";
181 pinctrl_periphs: pinctrl@480 {
182 compatible = "amlogic,meson-axg-periphs-pinctrl";
183 #address-cells = <2>;
188 reg = <0x0 0x00480 0x0 0x40>,
189 <0x0 0x004e8 0x0 0x14>,
190 <0x0 0x00520 0x0 0x14>,
191 <0x0 0x00430 0x0 0x3c>;
192 reg-names = "mux", "pull", "pull-enable", "gpio";
195 gpio-ranges = <&pinctrl_periphs 0 0 86>;
206 i2c1_x_pins: i2c1_x {
208 groups = "i2c1_sck_x",
214 i2c1_z_pins: i2c1_z {
216 groups = "i2c1_sck_z",
222 i2c2_a_pins: i2c2_a {
224 groups = "i2c2_sck_a",
230 i2c2_x_pins: i2c2_x {
232 groups = "i2c2_sck_x",
238 i2c3_a6_pins: i2c3_a6 {
240 groups = "i2c3_sda_a6",
246 i2c3_a12_pins: i2c3_a12 {
248 groups = "i2c3_sda_a12",
254 i2c3_a19_pins: i2c3_a19 {
256 groups = "i2c3_sda_a19",
264 groups = "emmc_nand_d0",
279 emmc_clk_gate_pins: emmc_clk_gate {
282 function = "gpio_periphs";
290 eth_rgmii_x_pins: eth-x-rgmii {
292 groups = "eth_mdio_x",
294 "eth_rgmii_rx_clk_x",
310 eth_rgmii_y_pins: eth-y-rgmii {
312 groups = "eth_mdio_y",
314 "eth_rgmii_rx_clk_y",
330 eth_rmii_x_pins: eth-x-rmii {
332 groups = "eth_mdio_x",
334 "eth_rgmii_rx_clk_x",
345 eth_rmii_y_pins: eth-y-rmii {
347 groups = "eth_mdio_y",
349 "eth_rgmii_rx_clk_y",
360 mclk_b_pins: mclk_b {
367 mclk_c_pins: mclk_c {
374 pdm_dclk_a14_pins: pdm_dclk_a14 {
376 groups = "pdm_dclk_a14";
381 pdm_dclk_a19_pins: pdm_dclk_a19 {
383 groups = "pdm_dclk_a19";
388 pdm_din0_pins: pdm_din0 {
395 pdm_din1_pins: pdm_din1 {
402 pdm_din2_pins: pdm_din2 {
409 pdm_din3_pins: pdm_din3 {
416 pwm_a_a_pins: pwm_a_a {
423 pwm_a_x18_pins: pwm_a_x18 {
425 groups = "pwm_a_x18";
430 pwm_a_x20_pins: pwm_a_x20 {
432 groups = "pwm_a_x20";
437 pwm_a_z_pins: pwm_a_z {
444 pwm_b_a_pins: pwm_b_a {
451 pwm_b_x_pins: pwm_b_x {
458 pwm_b_z_pins: pwm_b_z {
465 pwm_c_a_pins: pwm_c_a {
472 pwm_c_x10_pins: pwm_c_x10 {
474 groups = "pwm_c_x10";
479 pwm_c_x17_pins: pwm_c_x17 {
481 groups = "pwm_c_x17";
486 pwm_d_x11_pins: pwm_d_x11 {
488 groups = "pwm_d_x11";
493 pwm_d_x16_pins: pwm_d_x16 {
495 groups = "pwm_d_x16";
512 sdio_clk_gate_pins: sdio_clk_gate {
515 function = "gpio_periphs";
523 spdif_in_z_pins: spdif_in_z {
525 groups = "spdif_in_z";
526 function = "spdif_in";
530 spdif_in_a1_pins: spdif_in_a1 {
532 groups = "spdif_in_a1";
533 function = "spdif_in";
537 spdif_in_a7_pins: spdif_in_a7 {
539 groups = "spdif_in_a7";
540 function = "spdif_in";
544 spdif_in_a19_pins: spdif_in_a19 {
546 groups = "spdif_in_a19";
547 function = "spdif_in";
551 spdif_in_a20_pins: spdif_in_a20 {
553 groups = "spdif_in_a20";
554 function = "spdif_in";
558 spdif_out_a1_pins: spdif_out_a1 {
560 groups = "spdif_out_a1";
561 function = "spdif_out";
565 spdif_out_a11_pins: spdif_out_a11 {
567 groups = "spdif_out_a11";
568 function = "spdif_out";
572 spdif_out_a19_pins: spdif_out_a19 {
574 groups = "spdif_out_a19";
575 function = "spdif_out";
579 spdif_out_a20_pins: spdif_out_a20 {
581 groups = "spdif_out_a20";
582 function = "spdif_out";
586 spdif_out_z_pins: spdif_out_z {
588 groups = "spdif_out_z";
589 function = "spdif_out";
595 groups = "spi0_miso",
602 spi0_ss0_pins: spi0_ss0 {
609 spi0_ss1_pins: spi0_ss1 {
616 spi0_ss2_pins: spi0_ss2 {
623 spi1_a_pins: spi1_a {
625 groups = "spi1_miso_a",
632 spi1_ss0_a_pins: spi1_ss0_a {
634 groups = "spi1_ss0_a";
639 spi1_ss1_pins: spi1_ss1 {
646 spi1_x_pins: spi1_x {
648 groups = "spi1_miso_x",
655 spi1_ss0_x_pins: spi1_ss0_x {
657 groups = "spi1_ss0_x";
662 tdma_din0_pins: tdma_din0 {
664 groups = "tdma_din0";
669 tdma_dout0_x14_pins: tdma_dout0_x14 {
671 groups = "tdma_dout0_x14";
676 tdma_dout0_x15_pins: tdma_dout0_x15 {
678 groups = "tdma_dout0_x15";
683 tdma_dout1_pins: tdma_dout1 {
685 groups = "tdma_dout1";
690 tdma_din1_pins: tdma_din1 {
692 groups = "tdma_din1";
697 tdma_fs_pins: tdma_fs {
704 tdma_fs_slv_pins: tdma_fs_slv {
706 groups = "tdma_fs_slv";
711 tdma_sclk_pins: tdma_sclk {
713 groups = "tdma_sclk";
718 tdma_sclk_slv_pins: tdma_sclk_slv {
720 groups = "tdma_sclk_slv";
725 tdmb_din0_pins: tdmb_din0 {
727 groups = "tdmb_din0";
732 tdmb_din1_pins: tdmb_din1 {
734 groups = "tdmb_din1";
739 tdmb_din2_pins: tdmb_din2 {
741 groups = "tdmb_din2";
746 tdmb_din3_pins: tdmb_din3 {
748 groups = "tdmb_din3";
753 tdmb_dout0_pins: tdmb_dout0 {
755 groups = "tdmb_dout0";
760 tdmb_dout1_pins: tdmb_dout1 {
762 groups = "tdmb_dout1";
767 tdmb_dout2_pins: tdmb_dout2 {
769 groups = "tdmb_dout2";
774 tdmb_dout3_pins: tdmb_dout3 {
776 groups = "tdmb_dout3";
781 tdmb_fs_pins: tdmb_fs {
788 tdmb_fs_slv_pins: tdmb_fs_slv {
790 groups = "tdmb_fs_slv";
795 tdmb_sclk_pins: tdmb_sclk {
797 groups = "tdmb_sclk";
802 tdmb_sclk_slv_pins: tdmb_sclk_slv {
804 groups = "tdmb_sclk_slv";
809 tdmc_fs_pins: tdmc_fs {
816 tdmc_fs_slv_pins: tdmc_fs_slv {
818 groups = "tdmc_fs_slv";
823 tdmc_sclk_pins: tdmc_sclk {
825 groups = "tdmc_sclk";
830 tdmc_sclk_slv_pins: tdmc_sclk_slv {
832 groups = "tdmc_sclk_slv";
837 tdmc_din0_pins: tdmc_din0 {
839 groups = "tdmc_din0";
844 tdmc_din1_pins: tdmc_din1 {
846 groups = "tdmc_din1";
851 tdmc_din2_pins: tdmc_din2 {
853 groups = "tdmc_din2";
858 tdmc_din3_pins: tdmc_din3 {
860 groups = "tdmc_din3";
865 tdmc_dout0_pins: tdmc_dout0 {
867 groups = "tdmc_dout0";
872 tdmc_dout1_pins: tdmc_dout1 {
874 groups = "tdmc_dout1";
879 tdmc_dout2_pins: tdmc_dout2 {
881 groups = "tdmc_dout2";
886 tdmc_dout3_pins: tdmc_dout3 {
888 groups = "tdmc_dout3";
893 uart_a_pins: uart_a {
895 groups = "uart_tx_a",
901 uart_a_cts_rts_pins: uart_a_cts_rts {
903 groups = "uart_cts_a",
909 uart_b_x_pins: uart_b_x {
911 groups = "uart_tx_b_x",
917 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
919 groups = "uart_cts_b_x",
925 uart_b_z_pins: uart_b_z {
927 groups = "uart_tx_b_z",
933 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
935 groups = "uart_cts_b_z",
941 uart_ao_b_z_pins: uart_ao_b_z {
943 groups = "uart_ao_tx_b_z",
945 function = "uart_ao_b_z";
949 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
951 groups = "uart_ao_cts_b_z",
953 function = "uart_ao_b_z";
959 hiubus: bus@ff63c000 {
960 compatible = "simple-bus";
961 reg = <0x0 0xff63c000 0x0 0x1c00>;
962 #address-cells = <2>;
964 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
966 sysctrl: system-controller@0 {
967 compatible = "amlogic,meson-axg-hhi-sysctrl",
968 "simple-mfd", "syscon";
971 clkc: clock-controller {
972 compatible = "amlogic,axg-clkc";
978 mailbox: mailbox@ff63dc00 {
979 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
980 reg = <0 0xff63dc00 0 0x400>;
981 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
982 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
983 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
987 audio: bus@ff642000 {
988 compatible = "simple-bus";
989 reg = <0x0 0xff642000 0x0 0x2000>;
990 #address-cells = <2>;
992 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
994 clkc_audio: clock-controller@0 {
995 compatible = "amlogic,axg-audio-clkc";
996 reg = <0x0 0x0 0x0 0xb4>;
999 clocks = <&clkc CLKID_AUDIO>,
1000 <&clkc CLKID_MPLL0>,
1001 <&clkc CLKID_MPLL1>,
1002 <&clkc CLKID_MPLL2>,
1003 <&clkc CLKID_MPLL3>,
1004 <&clkc CLKID_HIFI_PLL>,
1005 <&clkc CLKID_FCLK_DIV3>,
1006 <&clkc CLKID_FCLK_DIV4>,
1007 <&clkc CLKID_GP0_PLL>;
1008 clock-names = "pclk",
1018 resets = <&reset RESET_AUDIO>;
1021 toddr_a: audio-controller@100 {
1022 compatible = "amlogic,axg-toddr";
1023 reg = <0x0 0x100 0x0 0x1c>;
1024 #sound-dai-cells = <0>;
1025 sound-name-prefix = "TODDR_A";
1026 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1027 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1028 resets = <&arb AXG_ARB_TODDR_A>;
1029 status = "disabled";
1032 toddr_b: audio-controller@140 {
1033 compatible = "amlogic,axg-toddr";
1034 reg = <0x0 0x140 0x0 0x1c>;
1035 #sound-dai-cells = <0>;
1036 sound-name-prefix = "TODDR_B";
1037 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1038 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1039 resets = <&arb AXG_ARB_TODDR_B>;
1040 status = "disabled";
1043 toddr_c: audio-controller@180 {
1044 compatible = "amlogic,axg-toddr";
1045 reg = <0x0 0x180 0x0 0x1c>;
1046 #sound-dai-cells = <0>;
1047 sound-name-prefix = "TODDR_C";
1048 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1049 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1050 resets = <&arb AXG_ARB_TODDR_C>;
1051 status = "disabled";
1054 frddr_a: audio-controller@1c0 {
1055 compatible = "amlogic,axg-frddr";
1056 reg = <0x0 0x1c0 0x0 0x1c>;
1057 #sound-dai-cells = <0>;
1058 sound-name-prefix = "FRDDR_A";
1059 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1060 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1061 resets = <&arb AXG_ARB_FRDDR_A>;
1062 status = "disabled";
1065 frddr_b: audio-controller@200 {
1066 compatible = "amlogic,axg-frddr";
1067 reg = <0x0 0x200 0x0 0x1c>;
1068 #sound-dai-cells = <0>;
1069 sound-name-prefix = "FRDDR_B";
1070 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1071 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1072 resets = <&arb AXG_ARB_FRDDR_B>;
1073 status = "disabled";
1076 frddr_c: audio-controller@240 {
1077 compatible = "amlogic,axg-frddr";
1078 reg = <0x0 0x240 0x0 0x1c>;
1079 #sound-dai-cells = <0>;
1080 sound-name-prefix = "FRDDR_C";
1081 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1082 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1083 resets = <&arb AXG_ARB_FRDDR_C>;
1084 status = "disabled";
1087 arb: reset-controller@280 {
1088 compatible = "amlogic,meson-axg-audio-arb";
1089 reg = <0x0 0x280 0x0 0x4>;
1091 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1094 tdmin_a: audio-controller@300 {
1095 compatible = "amlogic,axg-tdmin";
1096 reg = <0x0 0x300 0x0 0x40>;
1097 sound-name-prefix = "TDMIN_A";
1098 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1099 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1100 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1101 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1102 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1103 clock-names = "pclk", "sclk", "sclk_sel",
1104 "lrclk", "lrclk_sel";
1105 status = "disabled";
1108 tdmin_b: audio-controller@340 {
1109 compatible = "amlogic,axg-tdmin";
1110 reg = <0x0 0x340 0x0 0x40>;
1111 sound-name-prefix = "TDMIN_B";
1112 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1113 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1114 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1115 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1116 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1117 clock-names = "pclk", "sclk", "sclk_sel",
1118 "lrclk", "lrclk_sel";
1119 status = "disabled";
1122 tdmin_c: audio-controller@380 {
1123 compatible = "amlogic,axg-tdmin";
1124 reg = <0x0 0x380 0x0 0x40>;
1125 sound-name-prefix = "TDMIN_C";
1126 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1127 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1128 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1129 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1130 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1131 clock-names = "pclk", "sclk", "sclk_sel",
1132 "lrclk", "lrclk_sel";
1133 status = "disabled";
1136 tdmin_lb: audio-controller@3c0 {
1137 compatible = "amlogic,axg-tdmin";
1138 reg = <0x0 0x3c0 0x0 0x40>;
1139 sound-name-prefix = "TDMIN_LB";
1140 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1141 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1142 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1143 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1144 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1145 clock-names = "pclk", "sclk", "sclk_sel",
1146 "lrclk", "lrclk_sel";
1147 status = "disabled";
1150 spdifout: audio-controller@480 {
1151 compatible = "amlogic,axg-spdifout";
1152 reg = <0x0 0x480 0x0 0x50>;
1153 #sound-dai-cells = <0>;
1154 sound-name-prefix = "SPDIFOUT";
1155 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1156 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1157 clock-names = "pclk", "mclk";
1158 status = "disabled";
1161 tdmout_a: audio-controller@500 {
1162 compatible = "amlogic,axg-tdmout";
1163 reg = <0x0 0x500 0x0 0x40>;
1164 sound-name-prefix = "TDMOUT_A";
1165 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1166 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1167 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1168 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1169 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1170 clock-names = "pclk", "sclk", "sclk_sel",
1171 "lrclk", "lrclk_sel";
1172 status = "disabled";
1175 tdmout_b: audio-controller@540 {
1176 compatible = "amlogic,axg-tdmout";
1177 reg = <0x0 0x540 0x0 0x40>;
1178 sound-name-prefix = "TDMOUT_B";
1179 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1180 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1181 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1182 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1183 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1184 clock-names = "pclk", "sclk", "sclk_sel",
1185 "lrclk", "lrclk_sel";
1186 status = "disabled";
1189 tdmout_c: audio-controller@580 {
1190 compatible = "amlogic,axg-tdmout";
1191 reg = <0x0 0x580 0x0 0x40>;
1192 sound-name-prefix = "TDMOUT_C";
1193 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1194 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1195 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1196 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1197 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1198 clock-names = "pclk", "sclk", "sclk_sel",
1199 "lrclk", "lrclk_sel";
1200 status = "disabled";
1204 aobus: bus@ff800000 {
1205 compatible = "simple-bus";
1206 reg = <0x0 0xff800000 0x0 0x100000>;
1207 #address-cells = <2>;
1209 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1211 sysctrl_AO: sys-ctrl@0 {
1212 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1213 reg = <0x0 0x0 0x0 0x100>;
1215 clkc_AO: clock-controller {
1216 compatible = "amlogic,meson-axg-aoclkc";
1222 pinctrl_aobus: pinctrl@14 {
1223 compatible = "amlogic,meson-axg-aobus-pinctrl";
1224 #address-cells = <2>;
1229 reg = <0x0 0x00014 0x0 0x8>,
1230 <0x0 0x0002c 0x0 0x4>,
1231 <0x0 0x00024 0x0 0x8>;
1232 reg-names = "mux", "pull", "gpio";
1235 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1238 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1240 groups = "i2c_ao_sck_4";
1241 function = "i2c_ao";
1245 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1247 groups = "i2c_ao_sck_8";
1248 function = "i2c_ao";
1252 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1254 groups = "i2c_ao_sck_10";
1255 function = "i2c_ao";
1259 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1261 groups = "i2c_ao_sda_5";
1262 function = "i2c_ao";
1266 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1268 groups = "i2c_ao_sda_9";
1269 function = "i2c_ao";
1273 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1275 groups = "i2c_ao_sda_11";
1276 function = "i2c_ao";
1280 remote_input_ao_pins: remote_input_ao {
1282 groups = "remote_input_ao";
1283 function = "remote_input_ao";
1287 uart_ao_a_pins: uart_ao_a {
1289 groups = "uart_ao_tx_a",
1291 function = "uart_ao_a";
1295 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1297 groups = "uart_ao_cts_a",
1299 function = "uart_ao_a";
1303 uart_ao_b_pins: uart_ao_b {
1305 groups = "uart_ao_tx_b",
1307 function = "uart_ao_b";
1311 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1313 groups = "uart_ao_cts_b",
1315 function = "uart_ao_b";
1320 sec_AO: ao-secure@140 {
1321 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1322 reg = <0x0 0x140 0x0 0x140>;
1323 amlogic,has-chip-id;
1326 pwm_AO_cd: pwm@2000 {
1327 compatible = "amlogic,meson-axg-ao-pwm";
1328 reg = <0x0 0x02000 0x0 0x20>;
1330 status = "disabled";
1333 uart_AO: serial@3000 {
1334 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1335 reg = <0x0 0x3000 0x0 0x18>;
1336 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1337 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1338 clock-names = "xtal", "pclk", "baud";
1339 status = "disabled";
1342 uart_AO_B: serial@4000 {
1343 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1344 reg = <0x0 0x4000 0x0 0x18>;
1345 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1346 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1347 clock-names = "xtal", "pclk", "baud";
1348 status = "disabled";
1352 compatible = "amlogic,meson-axg-i2c";
1353 reg = <0x0 0x05000 0x0 0x20>;
1354 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1355 clocks = <&clkc CLKID_AO_I2C>;
1356 #address-cells = <1>;
1358 status = "disabled";
1361 pwm_AO_ab: pwm@7000 {
1362 compatible = "amlogic,meson-axg-ao-pwm";
1363 reg = <0x0 0x07000 0x0 0x20>;
1365 status = "disabled";
1369 compatible = "amlogic,meson-gxbb-ir";
1370 reg = <0x0 0x8000 0x0 0x20>;
1371 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1372 status = "disabled";
1376 compatible = "amlogic,meson-axg-saradc",
1377 "amlogic,meson-saradc";
1378 reg = <0x0 0x9000 0x0 0x38>;
1379 #io-channel-cells = <1>;
1380 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1382 <&clkc_AO CLKID_AO_SAR_ADC>,
1383 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1384 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1385 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1386 status = "disabled";
1390 gic: interrupt-controller@ffc01000 {
1391 compatible = "arm,gic-400";
1392 reg = <0x0 0xffc01000 0 0x1000>,
1393 <0x0 0xffc02000 0 0x2000>,
1394 <0x0 0xffc04000 0 0x2000>,
1395 <0x0 0xffc06000 0 0x2000>;
1396 interrupt-controller;
1397 interrupts = <GIC_PPI 9
1398 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1399 #interrupt-cells = <3>;
1400 #address-cells = <0>;
1403 cbus: bus@ffd00000 {
1404 compatible = "simple-bus";
1405 reg = <0x0 0xffd00000 0x0 0x25000>;
1406 #address-cells = <2>;
1408 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1410 reset: reset-controller@1004 {
1411 compatible = "amlogic,meson-axg-reset";
1412 reg = <0x0 0x01004 0x0 0x9c>;
1416 gpio_intc: interrupt-controller@f080 {
1417 compatible = "amlogic,meson-gpio-intc";
1418 reg = <0x0 0xf080 0x0 0x10>;
1419 interrupt-controller;
1420 #interrupt-cells = <2>;
1421 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1422 status = "disabled";
1426 compatible = "amlogic,meson-axg-ee-pwm";
1427 reg = <0x0 0x1b000 0x0 0x20>;
1429 status = "disabled";
1433 compatible = "amlogic,meson-axg-ee-pwm";
1434 reg = <0x0 0x1a000 0x0 0x20>;
1436 status = "disabled";
1440 compatible = "amlogic,meson-axg-spicc";
1441 reg = <0x0 0x13000 0x0 0x3c>;
1442 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1443 clocks = <&clkc CLKID_SPICC0>;
1444 clock-names = "core";
1445 #address-cells = <1>;
1447 status = "disabled";
1451 compatible = "amlogic,meson-axg-spicc";
1452 reg = <0x0 0x15000 0x0 0x3c>;
1453 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1454 clocks = <&clkc CLKID_SPICC1>;
1455 clock-names = "core";
1456 #address-cells = <1>;
1458 status = "disabled";
1462 compatible = "amlogic,meson-axg-i2c";
1463 reg = <0x0 0x1c000 0x0 0x20>;
1464 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1465 clocks = <&clkc CLKID_I2C>;
1466 #address-cells = <1>;
1468 status = "disabled";
1472 compatible = "amlogic,meson-axg-i2c";
1473 reg = <0x0 0x1d000 0x0 0x20>;
1474 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1475 clocks = <&clkc CLKID_I2C>;
1476 #address-cells = <1>;
1478 status = "disabled";
1482 compatible = "amlogic,meson-axg-i2c";
1483 reg = <0x0 0x1e000 0x0 0x20>;
1484 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1485 clocks = <&clkc CLKID_I2C>;
1486 #address-cells = <1>;
1488 status = "disabled";
1492 compatible = "amlogic,meson-axg-i2c";
1493 reg = <0x0 0x1f000 0x0 0x20>;
1494 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1495 clocks = <&clkc CLKID_I2C>;
1496 #address-cells = <1>;
1498 status = "disabled";
1501 uart_B: serial@23000 {
1502 compatible = "amlogic,meson-gx-uart";
1503 reg = <0x0 0x23000 0x0 0x18>;
1504 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1505 status = "disabled";
1506 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1507 clock-names = "xtal", "pclk", "baud";
1510 uart_A: serial@24000 {
1511 compatible = "amlogic,meson-gx-uart";
1512 reg = <0x0 0x24000 0x0 0x18>;
1513 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1514 status = "disabled";
1515 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1516 clock-names = "xtal", "pclk", "baud";
1521 compatible = "simple-bus";
1522 reg = <0x0 0xffe00000 0x0 0x200000>;
1523 #address-cells = <2>;
1525 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1527 sd_emmc_b: sd@5000 {
1528 compatible = "amlogic,meson-axg-mmc";
1529 reg = <0x0 0x5000 0x0 0x800>;
1530 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1531 status = "disabled";
1532 clocks = <&clkc CLKID_SD_EMMC_B>,
1533 <&clkc CLKID_SD_EMMC_B_CLK0>,
1534 <&clkc CLKID_FCLK_DIV2>;
1535 clock-names = "core", "clkin0", "clkin1";
1536 resets = <&reset RESET_SD_EMMC_B>;
1539 sd_emmc_c: mmc@7000 {
1540 compatible = "amlogic,meson-axg-mmc";
1541 reg = <0x0 0x7000 0x0 0x800>;
1542 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1543 status = "disabled";
1544 clocks = <&clkc CLKID_SD_EMMC_C>,
1545 <&clkc CLKID_SD_EMMC_C_CLK0>,
1546 <&clkc CLKID_FCLK_DIV2>;
1547 clock-names = "core", "clkin0", "clkin1";
1548 resets = <&reset RESET_SD_EMMC_C>;
1552 sram: sram@fffc0000 {
1553 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1554 reg = <0x0 0xfffc0000 0x0 0x20000>;
1555 #address-cells = <1>;
1557 ranges = <0 0x0 0xfffc0000 0x20000>;
1559 cpu_scp_lpri: scp-shmem@0 {
1560 compatible = "amlogic,meson-axg-scp-shmem";
1561 reg = <0x13000 0x400>;
1564 cpu_scp_hpri: scp-shmem@200 {
1565 compatible = "amlogic,meson-axg-scp-shmem";
1566 reg = <0x13400 0x400>;
1572 compatible = "arm,armv8-timer";
1573 interrupts = <GIC_PPI 13
1574 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1576 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1578 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1580 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1584 compatible = "fixed-clock";
1585 clock-frequency = <24000000>;
1586 clock-output-names = "xtal";