arch/arm/dts/ls1021a.dtsi

   1 /*
   2  * Freescale ls1021a SOC common device tree source
   3  *
   4  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include "skeleton.dtsi"
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         compatible = "fsl,ls1021a";
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 serial0 = &lpuart0;
  18                 serial1 = &lpuart1;
  19                 serial2 = &lpuart2;
  20                 serial3 = &lpuart3;
  21                 serial4 = &lpuart4;
  22                 serial5 = &lpuart5;
  23                 sysclk = &sysclk;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu@f00 {
  31                         compatible = "arm,cortex-a7";
  32                         device_type = "cpu";
  33                         reg = <0xf00>;
  34                         clocks = <&cluster1_clk>;
  35                 };
  36
  37                 cpu@f01 {
  38                         compatible = "arm,cortex-a7";
  39                         device_type = "cpu";
  40                         reg = <0xf01>;
  41                         clocks = <&cluster1_clk>;
  42                 };
  43         };
  44
  45         timer {
  46                 compatible = "arm,armv7-timer";
  47                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  48                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  51         };
  52
  53         pmu {
  54                 compatible = "arm,cortex-a7-pmu";
  55                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  56                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
  57         };
  58
  59         soc {
  60                 compatible = "simple-bus";
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 device_type = "soc";
  64                 interrupt-parent = <&gic>;
  65                 ranges;
  66
  67                 gic: interrupt-controller@1400000 {
  68                         compatible = "arm,cortex-a7-gic";
  69                         #interrupt-cells = <3>;
  70                         interrupt-controller;
  71                         reg = <0x1401000 0x1000>,
  72                               <0x1402000 0x1000>,
  73                               <0x1404000 0x2000>,
  74                               <0x1406000 0x2000>;
  75                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  76
  77                 };
  78
  79                 ifc: ifc@1530000 {
  80                         compatible = "fsl,ifc", "simple-bus";
  81                         reg = <0x1530000 0x10000>;
  82                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  83                 };
  84
  85                 dcfg: dcfg@1ee0000 {
  86                         compatible = "fsl,ls1021a-dcfg", "syscon";
  87                         reg = <0x1ee0000 0x10000>;
  88                         big-endian;
  89                 };
  90
  91                 esdhc: esdhc@1560000 {
  92                         compatible = "fsl,esdhc";
  93                         reg = <0x1560000 0x10000>;
  94                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
  95                         clock-frequency = <0>;
  96                         voltage-ranges = <1800 1800 3300 3300>;
  97                         sdhci,auto-cmd12;
  98                         big-endian;
  99                         bus-width = <4>;
 100                         status = "disabled";
 101                 };
 102
 103                 scfg: scfg@1570000 {
 104                         compatible = "fsl,ls1021a-scfg", "syscon";
 105                         reg = <0x1570000 0x10000>;
 106                         big-endian;
 107                 };
 108
 109                 clockgen: clocking@1ee1000 {
 110                         #address-cells = <1>;
 111                         #size-cells = <1>;
 112                         ranges = <0x0 0x1ee1000 0x10000>;
 113
 114                         sysclk: sysclk {
 115                                 compatible = "fixed-clock";
 116                                 #clock-cells = <0>;
 117                                 clock-output-names = "sysclk";
 118                         };
 119
 120                         cga_pll1: pll@800 {
 121                                 compatible = "fsl,qoriq-core-pll-2.0";
 122                                 #clock-cells = <1>;
 123                                 reg = <0x800 0x10>;
 124                                 clocks = <&sysclk>;
 125                                 clock-output-names = "cga-pll1", "cga-pll1-div2",
 126                                                      "cga-pll1-div4";
 127                         };
 128
 129                         platform_clk: pll@c00 {
 130                                 compatible = "fsl,qoriq-core-pll-2.0";
 131                                 #clock-cells = <1>;
 132                                 reg = <0xc00 0x10>;
 133                                 clocks = <&sysclk>;
 134                                 clock-output-names = "platform-clk", "platform-clk-div2";
 135                         };
 136
 137                         cluster1_clk: clk0c0@0 {
 138                                 compatible = "fsl,qoriq-core-mux-2.0";
 139                                 #clock-cells = <0>;
 140                                 reg = <0x0 0x10>;
 141                                 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
 142                                 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
 143                                 clock-output-names = "cluster1-clk";
 144                         };
 145                 };
 146
 147                 dspi0: dspi@2100000 {
 148                         compatible = "fsl,vf610-dspi";
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         reg = <0x2100000 0x10000>;
 152                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 153                         clock-names = "dspi";
 154                         clocks = <&platform_clk 1>;
 155                         num-cs = <6>;
 156                         big-endian;
 157                         status = "disabled";
 158                 };
 159
 160                 dspi1: dspi@2110000 {
 161                         compatible = "fsl,vf610-dspi";
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         reg = <0x2110000 0x10000>;
 165                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 166                         clock-names = "dspi";
 167                         clocks = <&platform_clk 1>;
 168                         num-cs = <6>;
 169                         big-endian;
 170                         status = "disabled";
 171                 };
 172
 173                 qspi: quadspi@1550000 {
 174                         compatible = "fsl,vf610-qspi";
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         reg = <0x1550000 0x10000>,
 178                                 <0x40000000 0x4000000>;
 179                         reg-names = "QuadSPI", "QuadSPI-memory";
 180                         num-cs = <2>;
 181                         big-endian;
 182                         status = "disabled";
 183                 };
 184
 185                 i2c0: i2c@2180000 {
 186                         compatible = "fsl,vf610-i2c";
 187                         #address-cells = <1>;
 188                         #size-cells = <0>;
 189                         reg = <0x2180000 0x10000>;
 190                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 191                         clock-names = "i2c";
 192                         clocks = <&platform_clk 1>;
 193                         status = "disabled";
 194                 };
 195
 196                 i2c1: i2c@2190000 {
 197                         compatible = "fsl,vf610-i2c";
 198                         #address-cells = <1>;
 199                         #size-cells = <0>;
 200                         reg = <0x2190000 0x10000>;
 201                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 202                         clock-names = "i2c";
 203                         clocks = <&platform_clk 1>;
 204                         status = "disabled";
 205                 };
 206
 207                 i2c2: i2c@21a0000 {
 208                         compatible = "fsl,vf610-i2c";
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                         reg = <0x21a0000 0x10000>;
 212                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 213                         clock-names = "i2c";
 214                         clocks = <&platform_clk 1>;
 215                         status = "disabled";
 216                 };
 217
 218                 uart0: serial@21c0500 {
 219                         compatible = "fsl,16550-FIFO64", "ns16550a";
 220                         reg = <0x21c0500 0x100>;
 221                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 222                         fifo-size = <15>;
 223                         status = "disabled";
 224                 };
 225
 226                 uart1: serial@21c0600 {
 227                         compatible = "fsl,16550-FIFO64", "ns16550a";
 228                         reg = <0x21c0600 0x100>;
 229                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 230                         fifo-size = <15>;
 231                         status = "disabled";
 232                 };
 233
 234                 uart2: serial@21d0500 {
 235                         compatible = "fsl,16550-FIFO64", "ns16550a";
 236                         reg = <0x21d0500 0x100>;
 237                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 238                         fifo-size = <15>;
 239                         status = "disabled";
 240                 };
 241
 242                 uart3: serial@21d0600 {
 243                         compatible = "fsl,16550-FIFO64", "ns16550a";
 244                         reg = <0x21d0600 0x100>;
 245                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 246                         fifo-size = <15>;
 247                         status = "disabled";
 248                 };
 249
 250                 lpuart0: serial@2950000 {
 251                         compatible = "fsl,ls1021a-lpuart";
 252                         reg = <0x2950000 0x1000>;
 253                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 254                         clocks = <&sysclk>;
 255                         clock-names = "ipg";
 256                         status = "disabled";
 257                 };
 258
 259                 lpuart1: serial@2960000 {
 260                         compatible = "fsl,ls1021a-lpuart";
 261                         reg = <0x2960000 0x1000>;
 262                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 263                         clocks = <&platform_clk 1>;
 264                         clock-names = "ipg";
 265                         status = "disabled";
 266                 };
 267
 268                 lpuart2: serial@2970000 {
 269                         compatible = "fsl,ls1021a-lpuart";
 270                         reg = <0x2970000 0x1000>;
 271                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 272                         clocks = <&platform_clk 1>;
 273                         clock-names = "ipg";
 274                         status = "disabled";
 275                 };
 276
 277                 lpuart3: serial@2980000 {
 278                         compatible = "fsl,ls1021a-lpuart";
 279                         reg = <0x2980000 0x1000>;
 280                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 281                         clocks = <&platform_clk 1>;
 282                         clock-names = "ipg";
 283                         status = "disabled";
 284                 };
 285
 286                 lpuart4: serial@2990000 {
 287                         compatible = "fsl,ls1021a-lpuart";
 288                         reg = <0x2990000 0x1000>;
 289                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 290                         clocks = <&platform_clk 1>;
 291                         clock-names = "ipg";
 292                         status = "disabled";
 293                 };
 294
 295                 lpuart5: serial@29a0000 {
 296                         compatible = "fsl,ls1021a-lpuart";
 297                         reg = <0x29a0000 0x1000>;
 298                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 299                         clocks = <&platform_clk 1>;
 300                         clock-names = "ipg";
 301                         status = "disabled";
 302                 };
 303
 304                 wdog0: watchdog@2ad0000 {
 305                         compatible = "fsl,imx21-wdt";
 306                         reg = <0x2ad0000 0x10000>;
 307                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 308                         clocks = <&platform_clk 1>;
 309                         clock-names = "wdog-en";
 310                         big-endian;
 311                 };
 312
 313                 sai1: sai@2b50000 {
 314                         compatible = "fsl,vf610-sai";
 315                         reg = <0x2b50000 0x10000>;
 316                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&platform_clk 1>;
 318                         clock-names = "sai";
 319                         dma-names = "tx", "rx";
 320                         dmas = <&edma0 1 47>,
 321                                <&edma0 1 46>;
 322                         big-endian;
 323                         status = "disabled";
 324                 };
 325
 326                 sai2: sai@2b60000 {
 327                         compatible = "fsl,vf610-sai";
 328                         reg = <0x2b60000 0x10000>;
 329                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 330                         clocks = <&platform_clk 1>;
 331                         clock-names = "sai";
 332                         dma-names = "tx", "rx";
 333                         dmas = <&edma0 1 45>,
 334                                <&edma0 1 44>;
 335                         big-endian;
 336                         status = "disabled";
 337                 };
 338
 339                 edma0: edma@2c00000 {
 340                         #dma-cells = <2>;
 341                         compatible = "fsl,vf610-edma";
 342                         reg = <0x2c00000 0x10000>,
 343                               <0x2c10000 0x10000>,
 344                               <0x2c20000 0x10000>;
 345                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 346                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 347                         interrupt-names = "edma-tx", "edma-err";
 348                         dma-channels = <32>;
 349                         big-endian;
 350                         clock-names = "dmamux0", "dmamux1";
 351                         clocks = <&platform_clk 1>,
 352                                  <&platform_clk 1>;
 353                 };
 354
 355                 mdio0: mdio@2d24000 {
 356                         compatible = "gianfar";
 357                         device_type = "mdio";
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         reg = <0x2d24000 0x4000>;
 361                 };
 362
 363                 usb@8600000 {
 364                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 365                         reg = <0x8600000 0x1000>;
 366                         interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 367                         dr_mode = "host";
 368                         phy_type = "ulpi";
 369                 };
 370
 371                 usb3@3100000 {
 372                         compatible = "fsl,layerscape-dwc3";
 373                         reg = <0x3100000 0x10000>;
 374                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 375                         dr_mode = "host";
 376                 };
 377
 378                 pcie@3400000 {
 379                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
 380                         reg = <0x03400000 0x20000   /* dbi registers */
 381                                0x01570000 0x10000   /* pf controls registers */
 382                                0x24000000 0x20000>; /* configuration space */
 383                         reg-names = "dbi", "ctrl", "config";
 384                         big-endian;
 385                         #address-cells = <3>;
 386                         #size-cells = <2>;
 387                         device_type = "pci";
 388                         bus-range = <0x0 0xff>;
 389                         ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000   /* downstream I/O */
 390                                   0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
 391                 };
 392
 393                 pcie@3500000 {
 394                         compatible = "fsl,ls-pcie", "snps,dw-pcie";
 395                         reg = <0x03500000 0x10000    /* dbi registers */
 396                                0x01570000 0x10000    /* pf controls registers */
 397                                0x34000000 0x20000>;  /* configuration space */
 398                         reg-names = "dbi", "ctrl", "config";
 399                         big-endian;
 400                         #address-cells = <3>;
 401                         #size-cells = <2>;
 402                         device_type = "pci";
 403                         num-lanes = <2>;
 404                         bus-range = <0x0 0xff>;
 405                         ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000   /* downstream I/O */
 406                                   0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
 407                 };
 408         };
 409 };