1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale ls1021a SOC common device tree source
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
8 #include "skeleton.dtsi"
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "fsl,ls1021a";
13 interrupt-parent = <&gic>;
30 compatible = "arm,cortex-a7";
33 clocks = <&cluster1_clk>;
37 compatible = "arm,cortex-a7";
40 clocks = <&cluster1_clk>;
45 compatible = "arm,armv7-timer";
46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 compatible = "arm,cortex-a7-pmu";
54 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
59 compatible = "simple-bus";
63 interrupt-parent = <&gic>;
66 gic: interrupt-controller@1400000 {
67 compatible = "arm,cortex-a7-gic";
68 #interrupt-cells = <3>;
70 reg = <0x1401000 0x1000>,
74 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
79 compatible = "fsl,ifc", "simple-bus";
80 reg = <0x1530000 0x10000>;
81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
85 compatible = "fsl,ls1021a-dcfg", "syscon";
86 reg = <0x1ee0000 0x10000>;
90 esdhc: esdhc@1560000 {
91 compatible = "fsl,esdhc";
92 reg = <0x1560000 0x10000>;
93 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
94 clock-frequency = <0>;
95 voltage-ranges = <1800 1800 3300 3300>;
102 compatible = "fsl,ls1021a-scfg", "syscon";
103 reg = <0x1570000 0x10000>;
107 clockgen: clocking@1ee1000 {
108 #address-cells = <1>;
110 ranges = <0x0 0x1ee1000 0x10000>;
113 compatible = "fixed-clock";
115 clock-output-names = "sysclk";
119 compatible = "fsl,qoriq-core-pll-2.0";
123 clock-output-names = "cga-pll1", "cga-pll1-div2",
127 platform_clk: pll@c00 {
128 compatible = "fsl,qoriq-core-pll-2.0";
132 clock-output-names = "platform-clk", "platform-clk-div2";
135 cluster1_clk: clk0c0@0 {
136 compatible = "fsl,qoriq-core-mux-2.0";
139 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
140 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
141 clock-output-names = "cluster1-clk";
145 dspi0: dspi@2100000 {
146 compatible = "fsl,vf610-dspi";
147 #address-cells = <1>;
149 reg = <0x2100000 0x10000>;
150 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
151 clock-names = "dspi";
152 clocks = <&platform_clk 1>;
158 dspi1: dspi@2110000 {
159 compatible = "fsl,vf610-dspi";
160 #address-cells = <1>;
162 reg = <0x2110000 0x10000>;
163 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
164 clock-names = "dspi";
165 clocks = <&platform_clk 1>;
171 qspi: quadspi@1550000 {
172 compatible = "fsl,vf610-qspi";
173 #address-cells = <1>;
175 reg = <0x1550000 0x10000>,
176 <0x40000000 0x4000000>;
177 reg-names = "QuadSPI", "QuadSPI-memory";
184 compatible = "fsl,vf610-i2c";
185 #address-cells = <1>;
187 reg = <0x2180000 0x10000>;
188 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&platform_clk 1>;
195 compatible = "fsl,vf610-i2c";
196 #address-cells = <1>;
198 reg = <0x2190000 0x10000>;
199 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&platform_clk 1>;
206 compatible = "fsl,vf610-i2c";
207 #address-cells = <1>;
209 reg = <0x21a0000 0x10000>;
210 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&platform_clk 1>;
216 uart0: serial@21c0500 {
217 compatible = "fsl,16550-FIFO64", "ns16550a";
218 reg = <0x21c0500 0x100>;
219 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
224 uart1: serial@21c0600 {
225 compatible = "fsl,16550-FIFO64", "ns16550a";
226 reg = <0x21c0600 0x100>;
227 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
232 uart2: serial@21d0500 {
233 compatible = "fsl,16550-FIFO64", "ns16550a";
234 reg = <0x21d0500 0x100>;
235 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
240 uart3: serial@21d0600 {
241 compatible = "fsl,16550-FIFO64", "ns16550a";
242 reg = <0x21d0600 0x100>;
243 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
248 lpuart0: serial@2950000 {
249 compatible = "fsl,ls1021a-lpuart";
250 reg = <0x2950000 0x1000>;
251 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
257 lpuart1: serial@2960000 {
258 compatible = "fsl,ls1021a-lpuart";
259 reg = <0x2960000 0x1000>;
260 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&platform_clk 1>;
266 lpuart2: serial@2970000 {
267 compatible = "fsl,ls1021a-lpuart";
268 reg = <0x2970000 0x1000>;
269 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&platform_clk 1>;
275 lpuart3: serial@2980000 {
276 compatible = "fsl,ls1021a-lpuart";
277 reg = <0x2980000 0x1000>;
278 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&platform_clk 1>;
284 lpuart4: serial@2990000 {
285 compatible = "fsl,ls1021a-lpuart";
286 reg = <0x2990000 0x1000>;
287 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&platform_clk 1>;
293 lpuart5: serial@29a0000 {
294 compatible = "fsl,ls1021a-lpuart";
295 reg = <0x29a0000 0x1000>;
296 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&platform_clk 1>;
302 wdog0: watchdog@2ad0000 {
303 compatible = "fsl,imx21-wdt";
304 reg = <0x2ad0000 0x10000>;
305 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&platform_clk 1>;
307 clock-names = "wdog-en";
312 compatible = "fsl,vf610-sai";
313 reg = <0x2b50000 0x10000>;
314 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&platform_clk 1>;
317 dma-names = "tx", "rx";
318 dmas = <&edma0 1 47>,
325 compatible = "fsl,vf610-sai";
326 reg = <0x2b60000 0x10000>;
327 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&platform_clk 1>;
330 dma-names = "tx", "rx";
331 dmas = <&edma0 1 45>,
337 edma0: edma@2c00000 {
339 compatible = "fsl,vf610-edma";
340 reg = <0x2c00000 0x10000>,
343 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
345 interrupt-names = "edma-tx", "edma-err";
348 clock-names = "dmamux0", "dmamux1";
349 clocks = <&platform_clk 1>,
353 mdio0: mdio@2d24000 {
354 compatible = "gianfar";
355 device_type = "mdio";
356 #address-cells = <1>;
358 reg = <0x2d24000 0x4000>;
362 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
363 reg = <0x8600000 0x1000>;
364 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
370 compatible = "fsl,layerscape-dwc3";
371 reg = <0x3100000 0x10000>;
372 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
377 compatible = "fsl,ls-pcie", "snps,dw-pcie";
378 reg = <0x03400000 0x20000 /* dbi registers */
379 0x01570000 0x10000 /* pf controls registers */
380 0x24000000 0x20000>; /* configuration space */
381 reg-names = "dbi", "ctrl", "config";
383 #address-cells = <3>;
386 bus-range = <0x0 0xff>;
387 ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */
388 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
392 compatible = "fsl,ls-pcie", "snps,dw-pcie";
393 reg = <0x03500000 0x10000 /* dbi registers */
394 0x01570000 0x10000 /* pf controls registers */
395 0x34000000 0x20000>; /* configuration space */
396 reg-names = "dbi", "ctrl", "config";
398 #address-cells = <3>;
402 bus-range = <0x0 0xff>;
403 ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */
404 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
408 compatible = "fsl,ls1021a-ahci";
409 reg = <0x3200000 0x10000 0x20220520 0x4>;
410 reg-names = "sata-base", "ecc-addr";
411 interrupts = <0 101 4>;