1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale ls1021a SOC common device tree source
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
8 #include "skeleton.dtsi"
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "fsl,ls1021a";
13 interrupt-parent = <&gic>;
30 compatible = "arm,cortex-a7";
33 clocks = <&cluster1_clk>;
37 compatible = "arm,cortex-a7";
40 clocks = <&cluster1_clk>;
45 compatible = "arm,armv7-timer";
46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 compatible = "arm,cortex-a7-pmu";
54 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
59 compatible = "simple-bus";
63 interrupt-parent = <&gic>;
66 gic: interrupt-controller@1400000 {
67 compatible = "arm,cortex-a7-gic";
68 #interrupt-cells = <3>;
70 reg = <0x1401000 0x1000>,
74 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
79 compatible = "fsl,ifc", "simple-bus";
80 reg = <0x1530000 0x10000>;
81 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
85 compatible = "fsl,ls1021a-dcfg", "syscon";
86 reg = <0x1ee0000 0x10000>;
90 esdhc: esdhc@1560000 {
91 compatible = "fsl,esdhc";
92 reg = <0x1560000 0x10000>;
93 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
94 clock-frequency = <0>;
95 voltage-ranges = <1800 1800 3300 3300>;
102 compatible = "fsl,ls1021a-scfg", "syscon";
103 reg = <0x1570000 0x10000>;
107 clockgen: clocking@1ee1000 {
108 #address-cells = <1>;
110 ranges = <0x0 0x1ee1000 0x10000>;
113 compatible = "fixed-clock";
115 clock-output-names = "sysclk";
119 compatible = "fsl,qoriq-core-pll-2.0";
123 clock-output-names = "cga-pll1", "cga-pll1-div2",
127 platform_clk: pll@c00 {
128 compatible = "fsl,qoriq-core-pll-2.0";
132 clock-output-names = "platform-clk", "platform-clk-div2";
135 cluster1_clk: clk0c0@0 {
136 compatible = "fsl,qoriq-core-mux-2.0";
139 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
140 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
141 clock-output-names = "cluster1-clk";
145 dspi0: dspi@2100000 {
146 compatible = "fsl,vf610-dspi";
147 #address-cells = <1>;
149 reg = <0x2100000 0x10000>;
150 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
151 clock-names = "dspi";
152 clocks = <&platform_clk 1>;
158 dspi1: dspi@2110000 {
159 compatible = "fsl,vf610-dspi";
160 #address-cells = <1>;
162 reg = <0x2110000 0x10000>;
163 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
164 clock-names = "dspi";
165 clocks = <&platform_clk 1>;
171 qspi: quadspi@1550000 {
172 compatible = "fsl,ls1021a-qspi";
173 #address-cells = <1>;
175 reg = <0x1550000 0x10000>,
176 <0x40000000 0x1000000>;
177 reg-names = "QuadSPI", "QuadSPI-memory";
182 compatible = "fsl,vf610-i2c";
183 #address-cells = <1>;
185 reg = <0x2180000 0x10000>;
186 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&platform_clk 1>;
193 compatible = "fsl,vf610-i2c";
194 #address-cells = <1>;
196 reg = <0x2190000 0x10000>;
197 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&platform_clk 1>;
204 compatible = "fsl,vf610-i2c";
205 #address-cells = <1>;
207 reg = <0x21a0000 0x10000>;
208 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&platform_clk 1>;
214 uart0: serial@21c0500 {
215 compatible = "fsl,16550-FIFO64", "ns16550a";
216 reg = <0x21c0500 0x100>;
217 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
222 uart1: serial@21c0600 {
223 compatible = "fsl,16550-FIFO64", "ns16550a";
224 reg = <0x21c0600 0x100>;
225 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
230 uart2: serial@21d0500 {
231 compatible = "fsl,16550-FIFO64", "ns16550a";
232 reg = <0x21d0500 0x100>;
233 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
238 uart3: serial@21d0600 {
239 compatible = "fsl,16550-FIFO64", "ns16550a";
240 reg = <0x21d0600 0x100>;
241 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
246 lpuart0: serial@2950000 {
247 compatible = "fsl,ls1021a-lpuart";
248 reg = <0x2950000 0x1000>;
249 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
255 lpuart1: serial@2960000 {
256 compatible = "fsl,ls1021a-lpuart";
257 reg = <0x2960000 0x1000>;
258 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&platform_clk 1>;
264 lpuart2: serial@2970000 {
265 compatible = "fsl,ls1021a-lpuart";
266 reg = <0x2970000 0x1000>;
267 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&platform_clk 1>;
273 lpuart3: serial@2980000 {
274 compatible = "fsl,ls1021a-lpuart";
275 reg = <0x2980000 0x1000>;
276 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&platform_clk 1>;
282 lpuart4: serial@2990000 {
283 compatible = "fsl,ls1021a-lpuart";
284 reg = <0x2990000 0x1000>;
285 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&platform_clk 1>;
291 lpuart5: serial@29a0000 {
292 compatible = "fsl,ls1021a-lpuart";
293 reg = <0x29a0000 0x1000>;
294 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&platform_clk 1>;
300 wdog0: watchdog@2ad0000 {
301 compatible = "fsl,imx21-wdt";
302 reg = <0x2ad0000 0x10000>;
303 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&platform_clk 1>;
305 clock-names = "wdog-en";
310 compatible = "fsl,vf610-sai";
311 reg = <0x2b50000 0x10000>;
312 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&platform_clk 1>;
315 dma-names = "tx", "rx";
316 dmas = <&edma0 1 47>,
323 compatible = "fsl,vf610-sai";
324 reg = <0x2b60000 0x10000>;
325 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&platform_clk 1>;
328 dma-names = "tx", "rx";
329 dmas = <&edma0 1 45>,
335 edma0: edma@2c00000 {
337 compatible = "fsl,vf610-edma";
338 reg = <0x2c00000 0x10000>,
341 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-names = "edma-tx", "edma-err";
346 clock-names = "dmamux0", "dmamux1";
347 clocks = <&platform_clk 1>,
351 enet0: ethernet@2d10000 {
352 compatible = "fsl,etsec2";
353 reg = <0x2d10000 0x1000>;
357 enet1: ethernet@2d50000 {
358 compatible = "fsl,etsec2";
359 reg = <0x2d50000 0x1000>;
363 enet2: ethernet@2d90000 {
364 compatible = "fsl,etsec2";
365 reg = <0x2d90000 0x1000>;
369 mdio0: mdio@2d24000 {
370 compatible = "fsl,etsec2-mdio";
371 reg = <0x2d24000 0x4000>;
372 #address-cells = <1>;
376 mdio1: mdio@2d64000 {
377 compatible = "fsl,etsec2-mdio";
378 reg = <0x2d64000 0x4000>;
379 #address-cells = <1>;
384 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
385 reg = <0x8600000 0x1000>;
386 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
392 compatible = "fsl,layerscape-dwc3";
393 reg = <0x3100000 0x10000>;
394 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
399 compatible = "fsl,ls-pcie", "snps,dw-pcie";
400 reg = <0x03400000 0x20000 /* dbi registers */
401 0x01570000 0x10000 /* pf controls registers */
402 0x24000000 0x20000>; /* configuration space */
403 reg-names = "dbi", "ctrl", "config";
405 #address-cells = <3>;
408 bus-range = <0x0 0xff>;
409 ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */
410 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
414 compatible = "fsl,ls-pcie", "snps,dw-pcie";
415 reg = <0x03500000 0x10000 /* dbi registers */
416 0x01570000 0x10000 /* pf controls registers */
417 0x34000000 0x20000>; /* configuration space */
418 reg-names = "dbi", "ctrl", "config";
420 #address-cells = <3>;
424 bus-range = <0x0 0xff>;
425 ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */
426 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
430 compatible = "fsl,ls1021a-ahci";
431 reg = <0x3200000 0x10000 0x20220520 0x4>;
432 reg-names = "sata-base", "ecc-addr";
433 interrupts = <0 101 4>;