arch/arm/dts/ls1021a-twr.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale ls1021a TWR board common device tree source
   4  *
   5  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include "ls1021a.dtsi"
   9
  10 / {
  11         model = "LS1021A TWR Board";
  12
  13         aliases {
  14                 enet2-rgmii-phy = &rgmii_phy1;
  15                 enet0-sgmii-phy = &sgmii_phy2;
  16                 enet1-sgmii-phy = &sgmii_phy0;
  17                 spi0 = &qspi;
  18                 spi1 = &dspi1;
  19         };
  20
  21         chosen {
  22                 stdout-path = &uart0;
  23         };
  24 };
  25
  26 &qspi {
  27         bus-num = <0>;
  28         status = "okay";
  29
  30         qflash0: n25q128a13@0 {
  31                 #address-cells = <1>;
  32                 #size-cells = <1>;
  33                 compatible = "jedec,spi-nor";
  34                 spi-max-frequency = <20000000>;
  35                 reg = <0>;
  36         };
  37 };
  38
  39 &dspi1 {
  40         bus-num = <0>;
  41         status = "okay";
  42
  43         dspiflash: at26df081a@0 {
  44                 #address-cells = <1>;
  45                 #size-cells = <1>;
  46                 compatible = "jedec,spi-nor";
  47                 spi-max-frequency = <16000000>;
  48                 spi-cpol;
  49                 spi-cpha;
  50                 reg = <0>;
  51         };
  52 };
  53
  54 &enet0 {
  55         tbi-handle = <&tbi0>;
  56         phy-handle = <&sgmii_phy2>;
  57         phy-connection-type = "sgmii";
  58         status = "okay";
  59 };
  60
  61 &enet1 {
  62         tbi-handle = <&tbi1>;
  63         phy-handle = <&sgmii_phy0>;
  64         phy-connection-type = "sgmii";
  65         status = "okay";
  66 };
  67
  68 &enet2 {
  69         phy-handle = <&rgmii_phy1>;
  70         phy-connection-type = "rgmii-id";
  71         status = "okay";
  72 };
  73
  74 &i2c0 {
  75         status = "okay";
  76 };
  77
  78 &i2c1 {
  79         status = "okay";
  80 };
  81
  82 &ifc {
  83         #address-cells = <2>;
  84         #size-cells = <1>;
  85         /* NOR Flash on board */
  86         ranges = <0x0 0x0 0x60000000 0x08000000>;
  87         status = "okay";
  88
  89         nor@0,0 {
  90                 #address-cells = <1>;
  91                 #size-cells = <1>;
  92                 compatible = "cfi-flash";
  93                 reg = <0x0 0x0 0x8000000>;
  94                 bank-width = <2>;
  95                 device-width = <1>;
  96         };
  97 };
  98
  99 &lpuart0 {
 100         status = "okay";
 101 };
 102
 103 &mdio0 {
 104         sgmii_phy0: ethernet-phy@0 {
 105                 reg = <0x0>;
 106         };
 107
 108         rgmii_phy1: ethernet-phy@1 {
 109                 reg = <0x1>;
 110         };
 111
 112         sgmii_phy2: ethernet-phy@2 {
 113                 reg = <0x2>;
 114         };
 115
 116         /* SGMII PCS for enet0 */
 117         tbi0: tbi-phy@1f {
 118                 reg = <0x1f>;
 119                 device_type = "tbi-phy";
 120         };
 121 };
 122
 123 &mdio1 {
 124         /* SGMII PCS for enet1 */
 125         tbi1: tbi-phy@1f {
 126                 reg = <0x1f>;
 127                 device_type = "tbi-phy";
 128         };
 129 };
 130
 131 &uart0 {
 132         status = "okay";
 133 };
 134
 135 &uart1 {
 136         status = "okay";
 137 };
 138
 139 &sata {
 140         status = "okay";
 141 };