1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale ls1021a QDS board common device tree source
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
8 #include "ls1021a.dtsi"
11 model = "LS1021A QDS Board";
14 enet0-rgmii-phy = &rgmii_phy1;
15 enet1-rgmii-phy = &rgmii_phy2;
16 enet2-rgmii-phy = &rgmii_phy3;
17 enet0-sgmii-phy = &sgmii_phy1c;
18 enet1-sgmii-phy = &sgmii_phy1d;
28 dspiflash: at45db021d@0 {
31 compatible = "atmel,dataflash";
32 spi-max-frequency = <16000000>;
43 qflash0: s25fl128s@0 {
46 compatible = "jedec,spi-nor";
47 spi-max-frequency = <20000000>;
66 compatible = "dallas,ds3232";
68 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
78 compatible = "ti,ina220";
80 shunt-resistor = <1000>;
84 compatible = "ti,ina220";
86 shunt-resistor = <1000>;
96 compatible = "atmel,24c512";
101 compatible = "atmel,24c512";
106 compatible = "adi,adt7461a";
114 #address-cells = <2>;
116 /* NOR, NAND Flashes and FPGA on board */
117 ranges = <0x0 0x0 0x60000000 0x08000000
118 0x2 0x0 0x7e800000 0x00010000
119 0x3 0x0 0x7fb00000 0x00000100>;
123 #address-cells = <1>;
125 compatible = "cfi-flash";
126 reg = <0x0 0x0 0x8000000>;
131 fpga: board-control@3,0 {
132 #address-cells = <1>;
134 compatible = "simple-bus";
135 reg = <0x3 0x0 0x0000100>;
138 ranges = <0 3 0 0x100>;
141 compatible = "mdio-mux-mmioreg";
142 mdio-parent-bus = <&mdio0>;
143 #address-cells = <1>;
145 reg = <0x54 1>; /* BRDCFG4 */
146 mux-mask = <0xe0>; /* EMI1[2:0] */
149 ls1021amdio0: mdio@0 {
151 #address-cells = <1>;
153 rgmii_phy1: ethernet-phy@1 {
158 ls1021amdio1: mdio@20 {
160 #address-cells = <1>;
162 rgmii_phy2: ethernet-phy@2 {
167 ls1021amdio2: mdio@40 {
169 #address-cells = <1>;
171 rgmii_phy3: ethernet-phy@3 {
176 ls1021amdio3: mdio@60 {
178 #address-cells = <1>;
180 sgmii_phy1c: ethernet-phy@1c {
185 ls1021amdio4: mdio@80 {
187 #address-cells = <1>;
189 sgmii_phy1d: ethernet-phy@1d {
204 device_type = "tbi-phy";