arch/arm/dts/ls1021a-iot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale ls1021a IOT board device tree source
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  */
   7
   8
   9 #include "ls1021a.dtsi"
  10
  11 / {
  12         model = "LS1021A IOT Board";
  13
  14         aliases {
  15                 enet2-rgmii-phy = &rgmii_phy1;
  16                 enet0-sgmii-phy = &sgmii_phy2;
  17                 enet1-sgmii-phy = &sgmii_phy0;
  18                 spi0 = &qspi;
  19                 spi1 = &dspi1;
  20         };
  21 };
  22
  23 &qspi {
  24         bus-num = <0>;
  25         status = "okay";
  26
  27         qflash0: n25q128a13@0 {
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30                 compatible = "jedec,spi-nor";
  31                 spi-max-frequency = <20000000>;
  32                 reg = <0>;
  33         };
  34 };
  35
  36 &dspi1 {
  37         bus-num = <0>;
  38         status = "okay";
  39
  40         dspiflash: at26df081a@0 {
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 compatible = "jedec,spi-nor";
  44                 spi-max-frequency = <16000000>;
  45                 spi-cpol;
  46                 spi-cpha;
  47                 reg = <0>;
  48         };
  49 };
  50
  51 &i2c0 {
  52         status = "okay";
  53 };
  54
  55 &i2c1 {
  56         status = "okay";
  57 };
  58
  59 &ifc {
  60         #address-cells = <2>;
  61         #size-cells = <1>;
  62         /* NOR Flash on board */
  63         ranges = <0x0 0x0 0x60000000 0x08000000>;
  64         status = "okay";
  65
  66         nor@0,0 {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 compatible = "cfi-flash";
  70                 reg = <0x0 0x0 0x8000000>;
  71                 bank-width = <2>;
  72                 device-width = <1>;
  73         };
  74 };
  75
  76 &lpuart0 {
  77         status = "okay";
  78 };
  79
  80 &mdio0 {
  81         sgmii_phy0: ethernet-phy@0 {
  82                 reg = <0x0>;
  83         };
  84         rgmii_phy1: ethernet-phy@1 {
  85                 reg = <0x1>;
  86         };
  87         sgmii_phy2: ethernet-phy@2 {
  88                 reg = <0x2>;
  89         };
  90         tbi1: tbi-phy@1f {
  91                 reg = <0x1f>;
  92                 device_type = "tbi-phy";
  93         };
  94 };
  95
  96 &uart0 {
  97         status = "okay";
  98 };
  99
 100 &uart1 {
 101         status = "okay";
 102 };