arch/arm/dts/logicpd-torpedo-som.dtsi

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  */
   6
   7 #include <dt-bindings/input/input.h>
   8
   9 / {
  10         cpus {
  11                 cpu@0 {
  12                         cpu0-supply = <&vcc>;
  13                 };
  14         };
  15
  16         memory@80000000 {
  17                 device_type = "memory";
  18                 reg = <0x80000000 0>;
  19         };
  20
  21         leds {
  22                 compatible = "gpio-leds";
  23                 user0 {
  24                         label = "user0";
  25                         gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
  26                         linux,default-trigger = "none";
  27                 };
  28         };
  29
  30         wl12xx_vmmc: wl12xx_vmmc {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "vwl1271";
  33                 regulator-min-microvolt = <1800000>;
  34                 regulator-max-microvolt = <1800000>;
  35                 gpio = <&gpio5 29 0>;   /* gpio157 */
  36                 startup-delay-us = <70000>;
  37                 enable-active-high;
  38                 vin-supply = <&vmmc2>;
  39         };
  40 };
  41
  42 &gpmc {
  43         ranges = <0 0 0x30000000 0x1000000>;    /* CS0: 16MB for NAND */
  44
  45         nand@0,0 {
  46                 compatible = "ti,omap2-nand";
  47                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  48                 interrupt-parent = <&gpmc>;
  49                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  50                              <1 IRQ_TYPE_NONE>; /* termcount */
  51                 linux,mtd-name = "micron,mt29f4g16abbda3w";
  52                 nand-bus-width = <16>;
  53                 ti,nand-ecc-opt = "bch8";
  54                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  55                 gpmc,sync-clk-ps = <0>;
  56                 gpmc,cs-on-ns = <0>;
  57                 gpmc,cs-rd-off-ns = <44>;
  58                 gpmc,cs-wr-off-ns = <44>;
  59                 gpmc,adv-on-ns = <6>;
  60                 gpmc,adv-rd-off-ns = <34>;
  61                 gpmc,adv-wr-off-ns = <44>;
  62                 gpmc,we-off-ns = <40>;
  63                 gpmc,oe-off-ns = <54>;
  64                 gpmc,access-ns = <64>;
  65                 gpmc,rd-cycle-ns = <82>;
  66                 gpmc,wr-cycle-ns = <82>;
  67                 gpmc,wr-access-ns = <40>;
  68                 gpmc,wr-data-mux-bus-ns = <0>;
  69                 gpmc,device-width = <2>;
  70                 #address-cells = <1>;
  71                 #size-cells = <1>;
  72         };
  73 };
  74
  75 &i2c1 {
  76         clock-frequency = <400000>;
  77
  78         twl: twl@48 {
  79                 reg = <0x48>;
  80                 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
  81                 interrupt-parent = <&intc>;
  82                 twl_audio: audio {
  83                         compatible = "ti,twl4030-audio";
  84                         codec {
  85                         };
  86                 };
  87         };
  88 };
  89
  90 &i2c2 {
  91         clock-frequency = <400000>;
  92 };
  93
  94 &i2c3 {
  95         clock-frequency = <400000>;
  96         at24@50 {
  97                 compatible = "at24,24c02";
  98                 readonly;
  99                 reg = <0x50>;
 100         };
 101 };
 102
 103 /*
 104  * Only found on the wireless SOM. For the SOM without wireless, the pins for
 105  * MMC3 can be routed with jumpers to the second MMC slot on the devkit and
 106  * gpio157 is not connected. So this should be OK to keep common for now,
 107  * probably device tree overlays is the way to go with the various SOM and
 108  * jumpering combinations for the long run.
 109  */
 110 &mmc3 {
 111         interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
 112         pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>;
 113         pinctrl-names = "default";
 114         vmmc-supply = <&wl12xx_vmmc>;
 115         non-removable;
 116         bus-width = <4>;
 117         cap-power-off-card;
 118         #address-cells = <1>;
 119         #size-cells = <0>;
 120         wlcore: wlcore@2 {
 121                 compatible = "ti,wl1283";
 122                 reg = <2>;
 123                 interrupt-parent = <&gpio5>;
 124                 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; /* gpio 152 */
 125                 ref-clock-frequency = <26000000>;
 126                 tcxo-clock-frequency = <26000000>;
 127         };
 128 };
 129
 130 &omap3_pmx_core {
 131         mmc3_pins: pinmux_mm3_pins {
 132                 pinctrl-single,pins = <
 133                         OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
 134                         OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
 135                         OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
 136                         OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
 137                         OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */
 138                         OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4)       /* mcbsp1_fsr.gpio_157 */
 139                 >;
 140         };
 141         mcbsp2_pins: pinmux_mcbsp2_pins {
 142                 pinctrl-single,pins = <
 143                         OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0)        /* mcbsp2_fsx */
 144                         OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0)        /* mcbsp2_clkx */
 145                         OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0)        /* mcbsp2_dr */
 146                         OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0)       /* mcbsp2_dx */
 147                 >;
 148         };
 149         uart2_pins: pinmux_uart2_pins {
 150                 pinctrl-single,pins = <
 151                         OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0)        /* uart2_cts.uart2_cts */
 152                         OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0)       /* uart2_rts .uart2_rts*/
 153                         OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)       /* uart2_tx.uart2_tx */
 154                         OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)        /* uart2_rx.uart2_rx */
 155                         OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)       /* GPIO_162,BT_EN */
 156                 >;
 157         };
 158         mcspi1_pins: pinmux_mcspi1_pins {
 159                 pinctrl-single,pins = <
 160                         OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0)        /* mcspi1_clk.mcspi1_clk */
 161                         OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_simo.mcspi1_simo */
 162                         OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
 163                         OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0)       /* mcspi1_cs0.mcspi1_cs0 */
 164                 >;
 165         };
 166         hsusb_otg_pins: pinmux_hsusb_otg_pins {
 167                 pinctrl-single,pins = <
 168                         OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0)        /* hsusb0_clk.hsusb0_clk */
 169                         OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)       /* hsusb0_stp.hsusb0_stp */
 170                         OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0)        /* hsusb0_dir.hsusb0_dir */
 171                         OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0)        /* hsusb0_nxt.hsusb0_nxt */
 172
 173                         OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0)        /* hsusb0_data0.hsusb0_data0 */
 174                         OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0)        /* hsusb0_data1.hsusb0_data1 */
 175                         OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0)        /* hsusb0_data2.hsusb0_data2 */
 176                         OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0)        /* hsusb0_data3.hsusb0_data3 */
 177                         OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0)        /* hsusb0_data4.hsusb0_data4 */
 178                         OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0)        /* hsusb0_data5.hsusb0_data5 */
 179                         OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0)        /* hsusb0_data6.hsusb0_data6 */
 180                         OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0)        /* hsusb0_data7.hsusb0_data7 */
 181                 >;
 182         };
 183 };
 184
 185 &uart2 {
 186         interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&uart2_pins>;
 189 };
 190
 191 &mcspi1 {
 192         pinctrl-names = "default";
 193         pinctrl-0 = <&mcspi1_pins>;
 194 };
 195
 196 &omap3_pmx_core2 {
 197         mmc3_core2_pins: pinmux_mmc3_core2_pins {
 198                 pinctrl-single,pins = <
 199                         OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2)   /* etk_clk.sdmmc3_clk */
 200                         OMAP3630_CORE2_IOPAD(0x25da, PIN_INPUT_PULLUP | MUX_MODE2)   /* etk_ctl.sdmmc3_cmd */
 201                 >;
 202         };
 203 };
 204
 205 #include "twl4030.dtsi"
 206 #include "twl4030_omap3.dtsi"
 207
 208 &twl {
 209         twl_power: power {
 210                 compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
 211                 ti,use_poweroff;
 212         };
 213 };
 214
 215 &twl_gpio {
 216         ti,use-leds;
 217 };