arch/arm/dts/k3-j721e.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for J721E SoC Family
   4  *
   5  * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/pinctrl/k3.h>
  11 #include <dt-bindings/soc/ti,sci_pm_domain.h>
  12
  13 / {
  14         model = "Texas Instruments K3 J721E SoC";
  15         compatible = "ti,j721e";
  16         interrupt-parent = <&gic500>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 serial0 = &wkup_uart0;
  22                 serial1 = &mcu_uart0;
  23                 serial2 = &main_uart0;
  24                 serial3 = &main_uart1;
  25                 serial4 = &main_uart2;
  26                 serial5 = &main_uart3;
  27                 serial6 = &main_uart4;
  28                 serial7 = &main_uart5;
  29                 serial8 = &main_uart6;
  30                 serial9 = &main_uart7;
  31                 serial10 = &main_uart8;
  32                 serial11 = &main_uart9;
  33                 i2c0 = &wkup_i2c0;
  34                 i2c1 = &mcu_i2c0;
  35                 i2c2 = &mcu_i2c1;
  36                 i2c3 = &main_i2c0;
  37                 i2c4 = &main_i2c1;
  38                 i2c5 = &main_i2c2;
  39                 i2c6 = &main_i2c3;
  40                 i2c7 = &main_i2c4;
  41                 i2c8 = &main_i2c5;
  42                 i2c9 = &main_i2c6;
  43                 spi0 = &ospi0;
  44                 spi1 = &ospi1;
  45         };
  46
  47         chosen { };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52                 cpu-map {
  53                         cluster0: cluster0 {
  54                                 core0 {
  55                                         cpu = <&cpu0>;
  56                                 };
  57
  58                                 core1 {
  59                                         cpu = <&cpu1>;
  60                                 };
  61                         };
  62
  63                 };
  64
  65                 cpu0: cpu@0 {
  66                         compatible = "arm,cortex-a72";
  67                         reg = <0x000>;
  68                         device_type = "cpu";
  69                         enable-method = "psci";
  70                         i-cache-size = <0xC000>;
  71                         i-cache-line-size = <64>;
  72                         i-cache-sets = <256>;
  73                         d-cache-size = <0x8000>;
  74                         d-cache-line-size = <64>;
  75                         d-cache-sets = <128>;
  76                         next-level-cache = <&L2_0>;
  77                 };
  78
  79                 cpu1: cpu@1 {
  80                         compatible = "arm,cortex-a72";
  81                         reg = <0x001>;
  82                         device_type = "cpu";
  83                         enable-method = "psci";
  84                         i-cache-size = <0xC000>;
  85                         i-cache-line-size = <64>;
  86                         i-cache-sets = <256>;
  87                         d-cache-size = <0x8000>;
  88                         d-cache-line-size = <64>;
  89                         d-cache-sets = <128>;
  90                         next-level-cache = <&L2_0>;
  91                 };
  92         };
  93
  94         L2_0: l2-cache0 {
  95                 compatible = "cache";
  96                 cache-level = <2>;
  97                 cache-size = <0x100000>;
  98                 cache-line-size = <64>;
  99                 cache-sets = <2048>;
 100                 next-level-cache = <&msmc_l3>;
 101         };
 102
 103         msmc_l3: l3-cache0 {
 104                 compatible = "cache";
 105                 cache-level = <3>;
 106         };
 107
 108         firmware {
 109                 optee {
 110                         compatible = "linaro,optee-tz";
 111                         method = "smc";
 112                 };
 113
 114                 psci: psci {
 115                         compatible = "arm,psci-1.0";
 116                         method = "smc";
 117                 };
 118         };
 119
 120         a72_timer0: timer-cl0-cpu0 {
 121                 compatible = "arm,armv8-timer";
 122                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
 123                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
 124                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
 125                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
 126         };
 127
 128         pmu: pmu {
 129                 compatible = "arm,armv8-pmuv3";
 130                 /* Recommendation from GIC500 TRM Table A.3 */
 131                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 132         };
 133
 134         cbass_main: interconnect@100000 {
 135                 compatible = "simple-bus";
 136                 #address-cells = <2>;
 137                 #size-cells = <2>;
 138                 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
 139                          <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
 140                          <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
 141                          <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
 142                          <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
 143                          <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
 144                          <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
 145                          <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
 146                          <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
 147                          <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
 148                          <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
 149                          <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
 150                          <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
 151                          /* MCUSS_WKUP Range */
 152                          <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
 153                          <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
 154                          <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
 155                          <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
 156                          <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
 157                          <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
 158                          <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
 159                          <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
 160                          <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
 161                          <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
 162                          <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
 163                          <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>,
 164                          <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
 165                          <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
 166
 167                 cbass_mcu_wakeup: interconnect@28380000 {
 168                         compatible = "simple-bus";
 169                         #address-cells = <2>;
 170                         #size-cells = <2>;
 171                         ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
 172                                  <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
 173                                  <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
 174                                  <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
 175                                  <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
 176                                  <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
 177                                  <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
 178                                  <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
 179                                  <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
 180                                  <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
 181                                  <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
 182                                  <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
 183                                  <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
 184                 };
 185         };
 186 };
 187
 188 /* Now include the peripherals for each bus segments */
 189 #include "k3-j721e-main.dtsi"
 190 #include "k3-j721e-mcu-wakeup.dtsi"